CN1932949A - Circuit for realizing liquid crystal greyscale utilizing frame rate control method - Google Patents
Circuit for realizing liquid crystal greyscale utilizing frame rate control method Download PDFInfo
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Abstract
A circuit using frame and frank control method realizes liquid crystal gray-level and relates to impulse production unit, gray-level modulation unit, gray-level data reading control unit, data storage and frame synchronization production unit. The impulse production unit uses for producing seasonal impulse waveform and row synchronization signal. The impulse production unit owns one sub-frame counter and its different place brings impulse waveform with different pulse width after inputting the clock signal and row synchronization signal. The gray-level data reading control unit selects address and reads gray-level data as the input of gray-level modulation unit form data storage. The data storage stores gray-level data. The frame synchronization production unit incepts row synchronization signal and produces frame synchronization signal. The gray-level modulation unit unites each segment of gray-level data and output. It relates to some selectors and each level of them takes impulse waveform as select signal to data, and takes the inputting data of selector as gray-level data and the output of foregoing selector. It also takes much simpler circuit to realize gray-level modulation of FRC.
Description
Technical field
The present invention relates to a kind of liquid crystal greyscale control and realize circuit, in particular a kind of circuit structure of realizing the gray modulation of liquid crystal display in the Frame-rate Control mode.
Background technology
The luminous mechanism of prior liquid crystal display is to realize different brightness by the electric field difference that is added on certain picture element.Present chip for driving generally is to adopt the dynamic driving method, is divided into column electrode and row electrode.Generally column electrode is lined by line scan, the row electrode is applied signal bright or that do not work synchronously with the frame frequency more than the 30Hz.
Making voltage gating or gating not on the row electrode, is to give analog drive circuit by the pulse signal that Digital Logic produces different in width to realize.When the pulse width of sending is 0, gating not just, when the pulse width of sending was not 0, with regard to the corresponding time span of gating, also just corresponding different light and shade grade was called gray scale.Therefore from the Design of Digital Circuit angle, how long the pulse width of just giving analog drive circuit of care continues.The longest lasting level of pulse width, the highest gray scale that can realize exactly.
Any color all is to be mixed according to different proportion by RGB (RGB) three primary colours to obtain, if R, G, B have X, Y, Z kind probable value respectively, then can reach X*Y*Z kind color altogether, for example R, G, B respectively have 64 kinds of gray scales to select, and then total 64*64*64=262144 kind may make up.Because the realization circuit striking resemblances of R, G, B so need design a kind of circuit, can be exported to 64 gray-scale values the driving circuit of simulation with certain waveform.
Two kinds of gray modulation methods are generally arranged at present, PWM and FRC.
PWM, be width modulation (Pulse Width Modulation), be to be divided into several timeslices in the time at single pass, as 64 grades of gray scales, just be divided into 64 timeslices, if show 5/64 gray scale, so this point was had only in time of 5/64 driving voltage is arranged, last equivalent voltage just has only complete black 5/64.
FRC, promptly Frame-rate Control (Frame Rate Control) is that each timeslice has become a subframe, shows 64 grades of gray scales, will use 64 subframes so.At first will distinguish the notion of subframe (subframe), frame frequency is meant the number of times of the full frame data of kind interscan in a second, and in order to realize FRC, a frame is divided into some subframes.Because the visual effect of human eye feels that the brightness that is adding up of all subframes, as shown in Figure 1, the gray scale that shows each point respectively merges effect.
Than higher gray scale, generally adopt the mode of PWM+FRC combination for exponent number.Because gray scale is high more, the frequency that adopts PWM to need is just high more, and power consumption is also just big more, and the bit wide of gradation data has determined grey level, in general, and jPWM+kFRC (j, k=0,1,2 ...) gray scale that can realize is 2
(j+K), j+k is exactly the bit wide of gradation data.If realize 64 grades of gray scales, can adopt (j+k) to be 6.5PWM+1FRC is meant and is divided into two subframes, 32 timeslices arranged, as shown in Figure 2 in each subframe.4PWM+2FRC is meant and is divided into four subframes, 16 timeslices arranged, as shown in Figure 3 in each subframe.From the display effect analysis, if only realize 64 grades of gray scales with FRC, because be to be divided into 64 subframes, refreshing frequency is very high, and power consumption is the highest, but display effect is the most stable, claims that this modulating mode is 6FRC, as shown in Figure 4.
The FRC gray modulation mode circuit of prior art is comparatively complicated.
Summary of the invention
The purpose of this invention is to provide a kind of circuit with frame rate control method realization liquid crystal greyscale, realize the gray modulation pattern of FRC, it realizes that circuit is simple.
Technical scheme of the present invention is as follows:
A kind of circuit with frame rate control method realization liquid crystal greyscale wherein, comprises that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit;
Described pulse generation unit is used to produce periodic pulse waveform, as the input of gray modulation unit, generates line synchronizing signal simultaneously; Described pulse generation unit comprises a sub-frame count device, with clock signal and line synchronizing signal input back its not coordination produce the pulse waveform of distinct pulse widths;
Described gradation data reads control module and is used for carrying out address selection according to described line synchronizing signal, reads the input of gradation data as described gray modulation unit from memory device;
Described data-carrier store is used to store gradation data, and reads the address of control module input and read to apply for signal, the gradation data that output is corresponding according to gradation data;
Described frame synchronization generating unit is used to receive described line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal;
Described gray modulation unit is used for input pulse and gradation data, realizes that the pulse of each section gradation data merges back output.
Described circuit, wherein, the high or low level waveform of described gray modulation unit output is represented different gray scales according to its height duration difference.
Described circuit, wherein, described pulse generation unit is exported described line synchronizing signal by the timeslice counter, described line synchronizing signal also be simultaneously data-carrier store read to apply for signal.
Described circuit, wherein, described gray modulation unit comprises a plurality of unit that cascade is provided with, each unit comprises two selector switchs, the benchmark gradation data through a phase inverter after, with two inputs of basic pulse as rejection gate, T0 is as one of input of the second selector of first module in its output; To the i unit, gradation data Qi is as the selection signal of this unit first selector, and two input is respectively the anti-phase of pulse Pi and Pi; Ti is again as the selection signal of this unit second selector in this output, and it is input as the output of a described gradation data Qi and a last unit, and wherein i is natural sequence number.
A kind of circuit with frame rate control method realization liquid crystal greyscale provided by the present invention compared with prior art, has adopted simple circuit, and has realized the gray modulation of FRC mode.
Description of drawings
Fig. 1 is the effect synoptic diagram of the gray modulation of prior art at human eye;
Shown in Fig. 2 is the 5PWM+1FRC pattern diagram of prior art;
Shown in Fig. 3 is the 4PWM+2FRC pattern diagram of prior art;
Shown in Fig. 4 is the 6FRC pattern diagram of prior art;
Fig. 5 is that liquid crystal greyscale of the present invention is realized circuit structure diagram;
Fig. 6 is the graph of a relation of frame synchronizing signal of the present invention and line synchronizing signal;
Fig. 7 is a gray modulation of the present invention unit schematic diagram;
Fig. 8 is a pulse generation unit schematic diagram of the present invention;
Pulse waveform that Fig. 9 need import for 6FRC of the present invention and line synchronizing signal waveform synoptic diagram;
Figure 10 is the corresponding relation synoptic diagram of row, column signal of the present invention and LCD screen.
Embodiment
Below in conjunction with accompanying drawing, will the concrete enforcement of technical solution of the present invention be described in further detail:
Circuit arrangement of the present invention is mainly used in circuit area, display effect is required to be mainly used to the gray modulation of LCD Controller chip for driving than higher electronic product field.
A kind of circuit with frame rate control method realization liquid crystal greyscale of the present invention, structure comprises that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit as shown in Figure 5.
Described pulse generation unit is used to produce periodic pulse waveform, as the input of gray modulation unit, generates line synchronizing signal simultaneously.Described gradation data reads control module according to described line synchronizing signal, carries out address selection, reads the input of gradation data as described gray modulation unit from described data-carrier store.Described data-carrier store is used to store gradation data, reads the address of control module input and reads to apply for signal, output gray level data according to gradation data.Described frame synchronization generating unit receives line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal.Described gray modulation unit, input pulse and gradation data realize that the pulse of each section gradation data merges back output.The waveform of output is high and low two kinds of level, represents different gray scales according to height duration difference.
Described pulse generation unit is exported a line synchronizing signal by the timeslice counter.Described line synchronizing signal represents that the data of LCD panel lastrow have shown and finishes that linage-counter just adds up after receiving this signal, if the value that adds up reaches total line number of LCD panel, then exports a sub-frame sync signal.This signal is the end of a subframe of indication.After described pulse generation unit receives this sub-frame sync signal, add up, and produce reference pulse waveform, if the value that adds up reaches 64, the zero clearing that then resets, as shown in Figure 6.Because the redirect that each clock all will be gone, so line synchronizing signal is effective all the time, each clock of address (just capable number) all changes.Described line synchronizing signal also be simultaneously described data-carrier store read to apply for signal.
Described pulse generation unit produces the pulse waveform with gradation data bit wide equal number, export to the gray modulation unit with gradation data, generation comprises the waveform of gray value information, and this waveform is high and low two kinds of expressions, and represents different gray scales according to height duration difference.
Can't change owing to show the gradation data of any color, so the circuit design of pulse generation unit of the present invention and gray modulation unit has directly had influence on the waveform of exporting.
The circuit of described gray modulation of the present invention unit is seen shown in Figure 7, and the circuit of pulse generation unit is seen shown in Figure 8.
The circuit of described gray modulation unit is made of a plurality of unit of cascade as shown in Figure 7, and wherein P is the pulse that the pulse generation unit generates, and Q is gradation data.Benchmark gradation data Q0 through a phase inverter after, with two inputs of basic pulse P0 as rejection gate.According to the principle of rejection gate, as long as there is one to be input as 1, then exporting R0 is 0, and therefore as long as Q0 is 0, then R0 is 0, and Q0 is 1, then exports by P0 to determine.Q1 is as the selection signal of this unit first selector 1, and two inputs of first selector 1 are respectively the anti-phase of P1 and P1.Q1 is 1, then selects P1, and Q1 is the anti-phase of 0 selection P1.And this output T1 is as the selection signal of second selector 2, second selector 2 be input as Q1 and R0, T1 1 selects Q1, T1 0 to select R0, second selector 2 is output as R1.
Described gradation data can think that one is selected signal, exports behind the strobe pulse.The Q0 correspondence P0, and the Q1 correspondence P1, and the Qn correspondence Pn.Described gray modulation unit is handled successively, and as shown in Figure 7, each element circuit of cascade comprises two selector switchs in each element circuit, and Qi is as the selection signal of first selector 1, and two inputs of first selector 1 are respectively the anti-phase of Pi and Pi.Qi is 1, then selects Pi, and Qi is the anti-phase of 0 selection Pi.And this output Ti is as the selection signal of second selector 2, second selector 2 be input as Qi and Ri-1, Ri-1 is the output of a last unit, Ti is 1 selection Qi, and Ti is 0 selection Ri-1, and second selector 2 is output as Ri, wherein i is natural sequence number, and value is between 0≤i≤n
Pulse generation unit described in the circuit of the present invention is actually a sub-frame counter, as shown in Figure 8, produces frame synchronizing signal by clock signal and line synchronizing signal input, is input in the sub-frame count device.Because each of counter all is to be the recurrent pulses of 2 multiple a duration, just in time the scale-of-two with gradation data is corresponding one by one.The 0th cnt[0 of counter] corresponding P0, the 1st cnt[1] corresponding P1, the 2nd cnt[2] corresponding P2, n position cnt[n] corresponding Pn.In 6FRC, if be unit 1 with P0, then P0 is to be 1 pulse in the cycle, and P1 is to be 2 pulse in the cycle, and P2 is to be 4 pulse in the cycle, and P3 is to be 8 pulse in the cycle, and P4 is to be 16 pulse in the cycle, and P5 is to be 32 pulse in the cycle.Because the P0 and the Q0 of gray modulation unit are more special, so cnt[0] through being only P0 behind the phase inverter, low level behind the pulse elder generation high level.
Circuit of the present invention adopts the mode of pulse gate, can generate a group length different periodicity pulsewidth P0, P1, P2 in advance ... Pn is with P0, P1, P2 ... Pn is the unit gating.For 64 grades of gray scales, n=6 promptly is called the 6FRC modulation.
The 6FRC modulation algorithm has 64 subframes, with 6 periodic pulses, carry out the periodicity height according to the figure place variation of sub-frame count device and transform, the corresponding cnt[0 of P0], the corresponding cnt[1 of P1], the corresponding cnt[2 of P2], the corresponding cnt[3 of P3], the corresponding cnt[4 of P4], the corresponding cnt[5 of P5], therefore its width ratio pass is 1: 2: 4: 8: 16: 32, see shown in Figure 9.The corresponding positions of the corresponding gradation data of each recurrent pulses, data have 6.
If the LCD screen has 160 row, 160 clocks of then every mistake produce a sub-frame sync signal, and the sub-frame count device adds 1.The sub-frame count device is up to 64, counts again afterwards.
With the capable example that is shown as of N:
P0: high-low level all is the recurrent pulses of 1*N, corresponding Q0;
P1: high-low level all is the recurrent pulses of 2*N, corresponding Q1;
P2: high-low level all is the recurrent pulses of 4*N, corresponding Q2;
P3: high-low level all is the recurrent pulses of 8*N, corresponding Q3;
P4: high-low level all is the recurrent pulses of 16*N, corresponding Q4;
P5: high-low level all is the recurrent pulses of 32*N, corresponding Q5.
Because a clock is exactly a subframe, so line synchronizing signal must remain effectively, each clock of data reading circuit is all at request for data, and only the address is changing always, and the data of each application belong to different rows, see shown in Figure 10.
As 42=6 ' b101010, its data are in the 64th to the 22nd subframe totally 42 sub-image durations, are high level between the departure date of correspondence, have realized 42 gray scale output.
In sum, the designed liquid crystal display drive circuit of the present invention has been realized the gray modulation of FRC helping saving area with fairly simple circuit, improves display effect.
Should be understood that above-mentioned description at specific embodiment is comparatively detailed, but can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1, a kind of circuit with frame rate control method realization liquid crystal greyscale is characterized in that, comprises that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit;
Described pulse generation unit is used to produce periodic pulse waveform, as the input of gray modulation unit, generates line synchronizing signal simultaneously; Described pulse generation unit comprises a sub-frame count device, with clock signal and line synchronizing signal input back its not coordination produce the pulse waveform of distinct pulse widths;
Described gradation data reads control module and is used for carrying out address selection according to described line synchronizing signal, reads the input of gradation data as described gray modulation unit from memory device;
Described data-carrier store is used to store gradation data, and reads the address of control module input and read to apply for signal, the gradation data that output is corresponding according to gradation data;
Described frame synchronization generating unit is used to receive described line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal;
Described gray modulation unit is used for input pulse and gradation data, realizes that the pulse of each section gradation data merges back output.
2, circuit according to claim 1 is characterized in that, the high or low level waveform of described gray modulation unit output is represented different gray scales according to its height duration difference.
3, circuit according to claim 1 is characterized in that, described pulse generation unit is exported described line synchronizing signal by the timeslice counter, described line synchronizing signal also be simultaneously data-carrier store read to apply for signal.
4, circuit according to claim 1, it is characterized in that, described gray modulation unit comprises a plurality of unit that cascade is provided with, each unit comprises two selector switchs, the benchmark gradation data through a phase inverter after, with two inputs of basic pulse as rejection gate, T0 is as one of input of the second selector of first module in its output; To the i unit, gradation data Qi is as the selection signal of this unit first selector, and two input is respectively the anti-phase of pulse Pi and Pi; Ti is again as the selection signal of this unit second selector in this output, and it is input as the output of a described gradation data Qi and a last unit, and wherein i is natural sequence number.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102244959A (en) * | 2011-04-13 | 2011-11-16 | 天利半导体（深圳）有限公司 | Pulse width modulation unit, circuit and method for driving LED |
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| CN1107301C (en) * | 1994-08-23 | 2003-04-30 | 旭硝子株式会社 | Driving method for a liquid crystal display device |
| JPH1124637A (en) * | 1997-07-04 | 1999-01-29 | Optrex Corp | Drive method for simple matrix liquid crystal display |
| TW544650B (en) * | 2000-12-27 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Matrix-type display device and driving method thereof |
| EP1636784A1 (en) * | 2003-06-12 | 2006-03-22 | Koninklijke Philips Electronics N.V. | Energy saving passive matrix display device and method for driving |
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| CN102244959A (en) * | 2011-04-13 | 2011-11-16 | 天利半导体（深圳）有限公司 | Pulse width modulation unit, circuit and method for driving LED |
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Application publication date: 20070321 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2015440020319 Denomination of invention: Circuit for realizing liquid crystal greyscale by frame rate control method Granted publication date: 20081217 License type: Common License Record date: 20151123 |
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