CN1928824A - Method and system for loading FPGA target program - Google Patents
Method and system for loading FPGA target program Download PDFInfo
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- CN1928824A CN1928824A CNA2006101529253A CN200610152925A CN1928824A CN 1928824 A CN1928824 A CN 1928824A CN A2006101529253 A CNA2006101529253 A CN A2006101529253A CN 200610152925 A CN200610152925 A CN 200610152925A CN 1928824 A CN1928824 A CN 1928824A
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Abstract
The provided method for loading FPGA object program comprises: externally hanging flash memory on single-board EPLC to store the FPGA object program; configuring single-board interface; electrical resetting, loading the program into FPGA. This invention implements automatic loading to save startup time, and can on-line update for maintenance.
Description
Technical field
The present invention relates to data communication field, particularly a kind of method and system of loading FPGA target program.
Background technology
Present service processing board more and more adopts FPGA (Field Programmable Gate Array, field programmable gate array) chip is realized service processing function, and the logic scale is also increasing, and the load time to fpga logic when single board starting requires also more and more faster.Existing several load mode since to increase CPU or the load time oversize, all can not satisfy design requirement well.
It is the present veneer a kind of load modes that adopt that CPU loads more, and this mode is that the target program with FPGA is included in the middle of the host software, and after the system start-up, the CPU executive routine is loaded into target program among the FPGA.
The weak point of this method is: 1) load time long, generally want tens seconds time, and the target program scale is big more, the time that load to need is just long more.2) increase of CPU makes cost up, and does not have the veneer of CPU can't realize loading.
Also having a kind of mode is when not having CPU, and veneer is HDLC (the High-level Data Link Control by master control often
High-Level Data Link Control) passage is for the business processing subcard loads.This load mode needs the HDLC passage of business processing subcard and master control borad normal, and after subcard is plugged, the type of reading this subcard that the master control borad energy is correct is loaded into target program corresponding in the main control software in the fpga chip of this subcard by the HDLC passage then.
But this mode has following weak point: 1) load time long, need time of a few minutes at least, and the target program scale is big more, it is just long more to load the time that needs.2) during system upgrade, can cause the professional chief time to interrupt.
In addition, the veneer that has adopts principal and subordinate's load mode, increases a slice ROM (Read Only Memory exactly, ROM (read-only memory)), the FPGA target program is burnt earlier among the ROM, single board starting adopts the master slave mode of FPGA, initiatively initiate by FPGA, target program is loaded among the FPGA from ROM.Under this mode, program is in burned ROM, and is just fixing, can't realize the FPGA upgrading, makes and safeguards inconvenience.
Summary of the invention
The present invention provides a kind of method and system of loading FPGA target program in order to solve long and problem that can not online upgrading of load time in the prior art.Described technical scheme is as follows:
The invention provides a kind of method of loading FPGA target program, plug-in flash memory on the erasable programmable logical device of veneer, and carry out following steps:
Steps A: the target program of FPGA is stored on the described flash memory, and the interface to veneer is configured then;
Step B: Board Power up resets, and described target program is loaded on the FPGA from flash memory.
Described method also comprises:
Step C: the target program that stores in the flash memory is carried out online upgrading by advanced data link control channel.
Described method also comprises:
Step D: after the upgrading of target program in the flash memory, with the target program heavy duty after the upgrading to FPGA.
Described step B specifically comprises:
Step B1: Board Power up resets, and the stress state machine is migrated to the loading standby condition from idle condition, removes the FPGA internal storage;
Step B2: described removing finishes, and chooses the FPGA that needs loading, and described FPGA is read and write to the target program that is stored in the flash memory;
Step B3: loaded, it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
Described step C specifically comprises:
Step C1: the Access status machine of master control borad flash memory is moved to standby condition with the Access status machine by idle condition after being set to effectively;
Step C2: master control borad carries out read operation by advanced data link control channel to flash memory, and the program of reading in the flash memory judges whether this program is latest edition, if finish online upgrading; Otherwise, the target program in the erasing flash memory, wipe finish after, in flash memory, write the target program of latest edition.
Also comprise behind the described step C2:
Step C3: read the target program that newly writes from FLASH, whether the target program that checking writes is correct.
Described step D specifically comprises:
Step D1: behind the target program online upgrading in the flash memory, the erasable programmable logical device of veneer enters heavily loaded standby condition, removes the FPGA internal storage;
Step D2: after described removing finishes, choose described FPGA, the target program in the flash memory is read and write on the described FPGA;
Step D3: heavy duty finishes, and it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
The present invention also provides a kind of system of loading FPGA target program, and described system comprises:
Flash memory, described flash memory hang over outward on the erasable programmable logical device of veneer;
Memory module is used for storing the target program of FPGA into described flash memory;
Configuration module is used for the interface of veneer is configured;
Load-on module is used for Board Power up and resets, and described target program is loaded on the FPGA from flash memory.
Described system also comprises:
The online upgrading module is used for by advanced data link control channel the target program of flash memory being carried out online upgrading.
Described system also comprises:
Update module, be used for the target program upgrading of flash memory after, with the target program heavy duty after the upgrading to FPGA.
Described load-on module specifically comprises:
Load preparatory unit, be used for Board Power up and reset, the stress state machine is an idle condition, enters the loading standby condition, removes the FPGA internal storage;
Loading unit is used for described removing and finishes, and chooses the FPGA that needs loading, and the target program in the flash memory is read and write on the described FPGA; Loaded, it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
Described online upgrading module specifically comprises:
The Access status machine is provided with the unit, and the Access status machine that is used for the master control borad flash memory is moved to standby condition with the Access status machine by idle condition after being set to effectively;
The online upgrading unit is used for master control borad and by advanced data link control channel flash memory is carried out read operation, and the program of reading in the flash memory judges whether this program is latest edition, if finish online upgrading; Otherwise, the target program in the erasing flash memory, wipe finish after, in flash memory, write the target program of latest edition.
Described online upgrading module also comprises:
Authentication unit is used for reading the target program that newly writes from flash memory, and whether the target program that checking writes is correct.
Described update module specifically comprises:
The heavy duty preparatory unit, be used for the target program online upgrading of flash memory after, the erasable programmable logical device of veneer enters heavily loaded standby condition, removes the FPGA internal storage;
Described FPGA after being used for described removing and finishing, is chosen in the heavy duty unit, and the target program in the flash memory is read and write on the described FPGA; Heavy duty finishes, and it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
The beneficial effect that technical scheme of the present invention is brought is:
By at the EPLD of veneer (Erasable Programmable Logic Debice, the erasable programmable logical device) goes up plug-in one or more pieces FLASH (flash memory) and store the FPGA target program, realized loading automatically behind the Board Power up, saved the start-up time of veneer; Master control borad has realized that by advanced data link control channel it is more convenient that system maintenance is got up to the online upgrading of the FPGA target program among the FLASH.
Description of drawings
Fig. 1 is that the FPGA target program in the embodiment of the invention 1 loads block diagram;
Fig. 2 is the method flow diagram of the loading FPGA target program in the embodiment of the invention 1;
Fig. 3 is that the FPGA target program in the embodiment of the invention 1 loads sequential chart;
Fig. 4 is the address synoptic diagram of HDLC visit provided by the invention;
Fig. 5 is the online upgrading method flow diagram in the embodiment of the invention 2;
Fig. 6 is the loading update method process flow diagram in the embodiment of the invention 3;
Fig. 7 is the system schematic of the loading FPGA target program in the embodiment of the invention 4.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The present invention plug-in one or more pieces FLASH on the EPLD of veneer store the target program of fpga logic, and FPGA adopts from load mode also, behind each Board Power up, by EPLD control the program among the FLASH is loaded among the FPGA, the interface conversion by HDLC passage and EPLD realizes the online upgrading to target program among the FLASH.
Embodiment 1
Referring to Fig. 1, plug-in a slice FLASH on the EPLD of veneer connects two fpga chips by bus simultaneously on EPLD, and these two fpga chips connect in parallel mode.In the present embodiment, two fpga chips are arranged on the service processing board, realize the extensive business processing logic of veneer, require when Board Power up starts, to realize quick loading, and will realize system's online upgrading two FPGA.
Here be that 2.11MB is that example describes with FPGA target program size, then the FLASH of the plug-in a slice 4MB of single board design EPLD stores the target program of FPGA, because the logic function of two FPGA of veneer is identical, thus EPLD adopt from also, the mode of bus loads FPGA.
Referring to Fig. 2, the invention provides a kind of method of loading FPGA target program, may further comprise the steps:
Step 101: according to JTAG (Joint Test Action Group; Combined testing action group) the international standard test protocol stores the target program of FPGA among the FLASH into, and the interface on the veneer is defined, and is each interface configuration corresponding information.The present embodiment concrete configuration is as shown in table 1.
| Port name | The I/O type | Bit wide (bit) | Function declaration |
| Rst_Powerup | I | 1 | Electrification reset, reseting logic stress state machine, high level is effective |
| Reload | I | 1 | Logic is reloaded indication, and high level is effective |
| Flash_addr[21:0] | O | 22 | The Flash address |
| Flash_data[7:0] | I/ |
8 | The Flash data |
| Flash_ce_n | O | 1 | The choosing of Flash sheet, low level is effective |
| Flash_oe_n | O | 1 | The Flash output enable, low level is effective |
| Flash_we_n | O | 1 | Flash writes and enables, and low level is effective |
| Fpga_cs_n[1:0] | O | 2 | Fpga loads chip selection signal, and low level is effective |
| Fpga_prog_n | O | 1 | Fpga disposes beginning, and low level is effective |
| Fpga_init_n | I/O | 1 | For output, be used to empty Fpga internal configurations storer before the sampling of Fpga configuration mode; The sampling back is used for indicating layoutprocedure crc error to occur for input; Low level is effective |
| Fpga_done | I | 1 | Indication is finished in the Fpga configuration, and high level is effective |
| Fpga_data[7:0] | |
8 | Fpga disposes parallel data |
| Fpga_cclk | O | 1 | Fpga configuration clock |
Table 1
Step 102: Board Power up resets, the stress state machine is IDLE (idle condition), judge the DONE signal, if the DONE signal is " 0 ", then enter PROG_START (load and prepare) state, put the INIT signal empties FPGA for " 0 " internal storage by CLR_MEM (removing internal memory) state simultaneously.If the DONE signal is " 1 ", then explanation loads termination routine.
Step 103: enter CLR_WAIT (remove and wait for) state, at the mid-PROG signal of CLR_WAIT state procedure is " 1 ", is drawn high by FPGA up to the INIT signal, begins to enter PROGRAM (loading) state, CS (sheet choosing) signal of putting FPGA simultaneously is " 0 ", promptly chooses this FPGA;
Step 104: under the PROGRAM state, the EPLD logic generates the FLASH address automatically and adds 1 certainly by the clock cycle, and FPGA is read and write to target program from FLASH.
Step 105: loaded, FPGA draws high the DONE signal, and withdraw from the PROGRAM state and enter PROG_OVER (loading is finished) state, be " 1 " at PROG_OVER state underlying CS signal, enter the IDLE state then.
The loading sequential chart of the selected FPGA of above-mentioned veneer is referring to accompanying drawing 3.
Two factors are considered in the selection that FPGA is loaded clock (CCLK) frequency, deposit the outside FLASH access visit time tACC of fpga logic code and tSMDCC Time Created of loaded in parallel data-signal.The tACC of the selected FLASH of veneer is 110ns, and the tSMDCC minimum of selected FPGA is 2ns.Draw f
CCLK≤ 1/ (110ns+2ns), i.e. FPGA loading clock CCLK frequency should be less than 8.9MHz, and after its frequency of single board design was chosen as 25MHz input clock 4 frequency divisions, promptly 6.25MHz offered the FPGA load-on module.The loading sequential is as follows:
Board Power up resets, and PROG_B is low level " 0 ", puts the INIT_B signal simultaneously and is " 0 ".Enter CLR_WAIT (remove and wait for) state then, after removing finishes, the INIT_B signal drawn high be " 1 ", the CS_B signal of putting FPGA is " 0 ", the reset of RDWR_B signal, load, the EPLD logic generates the FLASH address automatically and adds 1 certainly by the clock cycle, and FPGA is read and write to target program from FLASH.Loaded, FPGA draws high the DONE signal, puts the CS_B signal and is " 1 ".
Embodiment 2
Master control borad is by the target program among the interface online upgrading FLASH of HDLC commentaries on classics Local Bus (local bus) and FLASH, after online upgrading is finished, when the target program of fpga logic need upgrade, master control borad issues the reload order, EPLD can start FPGA stress state machine, and the logic of FPGA is upgraded loading.If the target program of fpga logic does not temporarily need to upgrade, can not reload.
Master control is by the online programming of the short frame paging mode realization of HDLC to FLASH, and EPLD realizes that HDLC changes the conversion of Local Bus and FLASH interface.Short frame paging loads, and refers to every page of capacity 128B.The address of FLASH is divided into Flash_addr[21:15], Flash_addr[14:7] and Flash_addr[6:0] three sections, in EPLD inside HDLC is set and writes register, when HDLC carries out write operation to Flash, address high position with FLASH writes register Flash_addr[14:7 earlier] and Flash_addr[21:15] in, and low order address Flash_addr[6:0] overturn with clock, in EPLD inside with Flash_addr[21:15] and Flash_addr[14:7] be mapped on the address wire high position of FLASH, write 128 bytes after HDLC refresh Flash_addr[21:15 again] and Flash_addr[14:7] in the high address.
Veneer EPLD logic loads priority by design, when the EPLD execution loads FPGA automatically, does not allow master control that FLASH is carried out read and write access.
The register of veneer tabulation in the present embodiment:
Referring to table 2, the status register of FLASH: FLASH_STS
Address: 0x1E
| Bit | Title | R/W | Describe | Default value |
| 7:1 | Keep | RO | Keep | 0000000 |
| 0 | FLASH_STS | RO | The indication of FLASH state | X |
Table 2
Default configuration is a level signal when FLASH resets, " 1 " expression READY, " 0 " expression BUSY.
When this signal of configuration when being pulse mode, indicate respectively to wipe according to the difference of configuration order and finish or programme and finish.
Referring to table 3, the erasing-programming of FLASH/piece latch enable signal: FLASH_VPEN
Address: 0x1F
| Bit | Title | R/W | Describe | Default value |
| 7:1 | Keep | RO | Keep | 0000000 |
| 0 | FLASH_VPEN | RO | FLASH wipes and enables | 0 |
Table 3
When needing the upgrading FLASH program, the software one writing.
Referring to table 4, FLASH in-system programming enable register: FLASH_ISP_EN
Address: 0x21
| Bit | Title | R/W | Describe | Default value |
| 7:1 | Keep | RO | Keep | 0000000 |
| 0 | FLASH_ISP_EN | R/W | FLASH in-system programming enable | 0 |
Table 4
During the FPGA program of need upgrading, software is put FLASH_ISP_EN changes Local Bus and FLASH interface renewal FLASH for " 1 " by HDLC, and written in software RELOAD is " 1 " then, begins reloading of FPGA target program.
Referring to table 5, FLASH address register 1:FLASH_ADDR1
Address: 0x25
| Bit | Title | R/W | Describe | Default value |
| 7:0 | FLASH_ADDR[14:7] | R/W | FLASH[14:7] address signal | X |
Table 5
Referring to table 6, FLASH address register 2:FLASH_ADDR2
Address: 0x26
| Bit | Title | R/W | Describe | Default value |
| 7:0 | FLASH_ADDR[21:15] | R/W | FLASH[21:15] address signal | X |
Table 6
Referring to Fig. 4, the address space that HDLC can visit comprises EPLD internal register addresses space and FLASH memory address space.Use lb_addr[6:0] as the address field transport address, lb addr[7] be used for the chip select address space, as lb_addr[7] when being " 0 ", sheet selects the EPLD address space; As lb_addr[7] when being " 1 ", sheet selects the FLASH memory address space, carries out the read-write operation to FLASH.
Referring to Fig. 5, present embodiment is as follows by the process of using above-mentioned register tabulation carrying out online upgrading:
Step 201: start FLASH Access status machine, FLASH Access status machine is in original state IDLE, and flash_isp_en and reload initial value are " 0 ", and the fpga_load_over initial value of FPGA_LOAD_OVER register is " 1 ".
Step 202: during operate as normal, master control borad is as upgrading the FPGA program among the FLASH, when the fpga_load_over position is " 1 ", the flash_isp_en position of writing the inner FLASH_ISP_EN control register of EPLD earlier is " 1 ", and this moment, FLASH Access status machine was moved to the FLASH_START state by original state IDLE;
Step 203: enter read operation, the nOE signal of FLASH is chosen in set under READ, READ_DATA and READ_OVER state, and the data of assignment FLASH are given lb_din[7:0 under READ, READ_DATA and READ_OVER state].
Step 204: after master control borad is read target program among the FLASH, judge whether the target program of reading is latest edition, if stop upgrading, execution in step 207; Otherwise execution in step 205.
Step 205: wipe the original program among the FLASH earlier, the program with latest edition writes among the FLASH then.
The specific implementation process is: at first enable the FLASH_VPEN position and be " 1 ", could initiate the erase/program operations to FLASH.When carrying out erase operation, software inquiry FLASH_STS position is represented to wipe when for " 1 " and is finished, and can initiate the operation of writing a program to FLASH.To FLASH write a program the operation finish after, written in software FLASH_VPEN is " 0 ", to the FLASH write-protect.Choose the nWE signal of FLASH in WRITE, the set of WRITE_DATA state, the nWE signal is drawn high under the WRITE_OVER state, at WRITE, WRITE_DATA, WRITE_OVER state assignment lb_dout[7:0] give the data bus of FLASH.
Step 206: after the upgrading of FLASH internal program was finished, correct in order to ensure the target program that writes among the FLASH, master control borad can be carried out read operation once more, and whether the program that checking writes is correct.Also can no longer carry out read operation, present embodiment no longer carries out read operation.The flash_isp_en position of the inner FLASH_ISP_EN control register of master control borad written in software EPLD is " 0 ", discharges the chip selection signal of FLASH.
Step 207: finish online upgrading.
The FLASH partial code of upgrading:
always@(flash_curr_state or flash_isp_en or lb_rw or lb_en_n or lb_addr[7]orflash_vpen) begin case(flash_curr_state) FLASH_IDLE: if(flash_isp_en==1'b1) flash_next_state=FLASH_START; else flash_next_state=FLASH_IDLE; FLASH_START: if(lb_rw==1'b0&&lb_en_n==1'b0&&lb_addr[7]==1'b1&&flash_vpen) <!-- SIPO <DP n="8"> --> <dp n="d8"/> flash_next_state=WRITE; else if(lb_rw==1'b1&&lb_en_n==1'b0&&lb_addr[7]==1'b1) flash_next_state=READ; else flash_next_state=FLASH_START; WRITE: flash_next_state=WRITE_DATA; WRITE_DATA: flash_next_state=WRITE_OVER; WRITE_OVER: flash_next_state=FLASH_IDLE; READ: flash_next_state=READ_DATA; READ_DATA: flash_next_state=READ_OVER; READ_OVER: flash_next_state=FLASH_IDLE; default: flash_next_state=FLASH_IDLE; endcase end
Embodiment 3
After target program upgrading among the FLASH was finished, when the target program of FPGA need upgrade, master control borad issued the reload order, and EPLD can start FPGA stress state machine, referring to Fig. 6, specifically upgrades loading procedure and may further comprise the steps:
After target program among the step 301:FLASH upgraded and finishes, master control borad set reload (heavy duty) signal was " 1 ", and the EPLD logic enters the PROG_START state after the reload set, zero clearing reload under the PROGSTART state.
Step 302 to step 305 is reloaded FPGA with step 102 to 105, finishes the IDLE state of returning up to loading.Here repeat no more.
When sheet selects two FPGA to load simultaneously, the FPGA code is 2.11MB, clock period is 1/6.25MHz=160ns, it is 2.11MB * 160ns that parallel input needs the time, other states need about 5 cycles, about 5 cycles of the STARTUP process need of FPGA, like this: (2.11MB+5+5) * 160ns ~=354ms, realized quick loading to FPGA.
FPGA stress state machine partial code:
always@(load_curr_state or fpga_done or fpga_reload or fpga_init_b) begin case(load_curr_state) LOAD_IDLE: if((fpga_done==1'b0)||((fpga_done==1'b1)&&(fpga_reload==1'b1))) load_next_state=PROG_START; else load_next_state=LOAD_IDLE; PROG_START: load_next_state=CLR_MEM; CLR_MEM: load_next_state=CLR_WAIT; CLR_WAIT: if(fpga_init_b==1'b1) load_next_state=PROGRAM; else load_next_state=CLR_WAIT; PROGRAM: if(fpga_done==1'b1) load_next_state=PROG_OVER; else if(fpga_init_b==1'b0) load_next_state=PROG_START; else load_next_state=PROGRAM; PROG_OVER: load_next_state=LOAD_IDLE; <!-- SIPO <DP n="10"> --> <dp n="d10"/> default: load_next_state=LOAD_IDLE; endcaseend
Automatic loading section code:
//FLASH address read/write＜br/〉always@ (posedge clk25m or posedge rst)＜br/〉begin if (rst==1'b1) begin addr_flash_1d＜=FLASH_OFFSET_ADDR; End else if (load_curr_state[PROGRAM_POS]==1'b1) //FPGA loads begin addr_flash_1d[21:0 automatically]＜=addr_flash_1d[21:0]+1'b1; End else begin addr_flash_1d＜=FLASH_OFFSET_ADDR; Endendassign addr_flash=((| flash_curr_state[7:2])==1'b1) flash_addr2[6:0], flash_addr1, lb_addr[6:0]: addr_flash_ld; //FLASH data read/writeassign dq_flash=((| flash_curr_state[4:2])==1'b1) 8'h00, lb_din[7:0] }: 16'hzzzz; Assign flash_read_data=dq_flash[7:0];
Embodiment 4
Referring to Fig. 7, a kind of system of loading FPGA target program, this system comprises:
Flash memory, this flash memory hang over outward on the erasable programmable logical device of veneer;
Memory module is used for storing the target program of FPGA into flash memory;
Configuration module is used for the interface of veneer is configured;
Load-on module is used for Board Power up and resets, and target program is loaded on the FPGA from flash memory.
In order to realize the online upgrading of flash memory, system also comprises:
The online upgrading module is used for by advanced data link control channel the target program of flash memory being carried out online upgrading.
Update module, be used for the target program upgrading of flash memory after, with the target program heavy duty after the upgrading to FPGA.
Wherein, load-on module specifically comprises:
Load preparatory unit, be used for Board Power up and reset, the stress state machine is an idle condition, enters the loading standby condition, removes the FPGA internal storage;
Loading unit is used for removing and finishes, and chooses the FPGA that needs loading, reads and write the target program in the flash memory on the FPGA; Loaded, it is invalid that the FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
The online upgrading module specifically comprises:
The Access status machine is provided with the unit, and the Access status machine that is used for the master control borad flash memory is moved to standby condition with the Access status machine by idle condition after being set to effectively;
The online upgrading unit is used for master control borad and by advanced data link control channel flash memory is carried out read operation, and the program of reading in the flash memory judges whether this program is latest edition, if finish online upgrading; Otherwise, the target program in the erasing flash memory, wipe finish after, in flash memory, write the target program of latest edition.
The online upgrading module also comprises:
Authentication unit is used for reading the target program that newly writes from flash memory, and whether the target program that checking writes is correct.
Update module specifically comprises:
The heavy duty preparatory unit, be used for the target program online upgrading of flash memory after, the erasable programmable logical device of veneer enters heavily loaded standby condition, removes the FPGA internal storage;
The heavy duty unit, be used for removing finish after, choose FPGA, read and write the target program in the flash memory on the FPGA; Heavy duty finishes, and it is invalid that the FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
Above-described embodiment, the present invention embodiment a kind of more preferably just, the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacing all should be included in protection scope of the present invention.
Claims (14)
1. the method for a loading FPGA target program is characterized in that, plug-in flash memory on the erasable programmable logical device of veneer, and carry out following steps:
Steps A: the target program of FPGA is stored on the described flash memory, and the interface to veneer is configured then;
Step B: Board Power up resets, and described target program is loaded on the FPGA from flash memory.
2. the method for loading FPGA target program as claimed in claim 1 is characterized in that, described method also comprises:
Step C: the target program that stores in the flash memory is carried out online upgrading by advanced data link control channel.
3. the method for loading FPGA target program as claimed in claim 2 is characterized in that, described method also comprises:
Step D: after the upgrading of target program in the flash memory, with the target program heavy duty after the upgrading to FPGA.
4. the method for loading FPGA target program as claimed in claim 1 is characterized in that, described step B specifically comprises:
Step B1: Board Power up resets, and the stress state machine is migrated to the loading standby condition from idle condition, removes the FPGA internal storage;
Step B2: described removing finishes, and chooses the FPGA that needs loading, and described FPGA is read and write to the target program that is stored in the flash memory;
Step B3: loaded, it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
5. the method for loading FPGA target program as claimed in claim 2 is characterized in that, described step C specifically comprises:
Step C1: the Access status machine of master control borad flash memory is moved to standby condition with the Access status machine by idle condition after being set to effectively;
Step C2: master control borad carries out read operation by advanced data link control channel to flash memory, and the program of reading in the flash memory judges whether this program is latest edition, if finish online upgrading; Otherwise, the target program in the erasing flash memory, wipe finish after, in flash memory, write the target program of latest edition.
6. the method for loading FPGA target program as claimed in claim 5 is characterized in that, also comprises behind the described step C2:
Step C3: read the target program that newly writes from FLASH, whether the target program that checking writes is correct.
7. as the method for the described loading FPGA target program of arbitrary claim in the claim 3 to 6, it is characterized in that described step D specifically comprises:
Step D1: behind the target program online upgrading in the flash memory, the erasable programmable logical device of veneer enters heavily loaded standby condition, removes the FPGA internal storage;
Step D2: after described removing finishes, choose described FPGA, the target program in the flash memory is read and write on the described FPGA;
Step D3: heavy duty finishes, and it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
8. the system of a loading FPGA target program is characterized in that, described system comprises:
Flash memory, described flash memory hang over outward on the erasable programmable logical device of veneer;
Memory module is used for storing the target program of FPGA into described flash memory;
Configuration module is used for the interface of veneer is configured;
Load-on module is used for Board Power up and resets, and described target program is loaded on the FPGA from flash memory.
9. the system of loading FPGA target program as claimed in claim 8 is characterized in that, described system also comprises:
The online upgrading module is used for by advanced data link control channel the target program of flash memory being carried out online upgrading.
10. the system of loading FPGA target program as claimed in claim 9 is characterized in that, described system also comprises:
Update module, be used for the target program upgrading of flash memory after, with the target program heavy duty after the upgrading to FPGA.
11. the system of loading FPGA target program as claimed in claim 8 is characterized in that, described load-on module specifically comprises:
Load preparatory unit, be used for Board Power up and reset, the stress state machine is an idle condition, enters the loading standby condition, removes the FPGA internal storage;
Loading unit is used for described removing and finishes, and chooses the FPGA that needs loading, and the target program in the flash memory is read and write on the described FPGA; Loaded, it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
12. the system of loading FPGA target program as claimed in claim 9 is characterized in that, described online upgrading module specifically comprises:
The Access status machine is provided with the unit, and the Access status machine that is used for the master control borad flash memory is moved to standby condition with the Access status machine by idle condition after being set to effectively;
The online upgrading unit is used for master control borad and by advanced data link control channel flash memory is carried out read operation, and the program of reading in the flash memory judges whether this program is latest edition, if finish online upgrading; Otherwise, the target program in the erasing flash memory, wipe finish after, in flash memory, write the target program of latest edition.
13. the system of loading FPGA target program as claimed in claim 12 is characterized in that, described online upgrading module also comprises:
Authentication unit is used for reading the target program that newly writes from flash memory, and whether the target program that checking writes is correct.
14. the system as the described loading FPGA target program of the arbitrary claim of claim 10 to 13 is characterized in that, described update module specifically comprises:
The heavy duty preparatory unit, be used for the target program online upgrading of flash memory after, the erasable programmable logical device of veneer enters heavily loaded standby condition, removes the FPGA internal storage;
Described FPGA after being used for described removing and finishing, is chosen in the heavy duty unit, and the target program in the flash memory is read and write on the described FPGA; Heavy duty finishes, and it is invalid that described FPGA chip selection signal is set to, and the stress state machine enters idle condition simultaneously.
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