CN1925135A

CN1925135A - Method for making powered matrix organic luminescent diode panel

Info

Publication number: CN1925135A
Application number: CN 200510099607
Authority: CN
Inventors: 陈振铭
Original assignee: Chunghwa Picture Tubes Ltd
Current assignee: Chunghwa Picture Tubes Ltd
Priority date: 2005-08-30
Filing date: 2005-08-30
Publication date: 2007-03-07

Abstract

This invention provides one active matrix organic light diode panel process method, which comprises the following steps: providing baseboard to form signal line and leakage metal onto baseboard to form buffer insulator layer and active layer onto buffer insulator layer; depositing grating insulation layer on active layer and buffer insulation layer to form grating metal on grating insulation surface for ion injection source electrode and leakage electrode for form path to form transparent electrode and grating insulation layer to form pixel electrode insulation layer on transparent electrode to form light diode on transparent electrode.

Description

A kind of manufacture method of active matrix organic LED panel

Technical field

The present invention relates to a kind of manufacture method of thin-film transistor display panel, relate in particular to a kind of organic light emitting diode display that is applied to, have the manufacture method of the organic LED panel of low-temperature polysilicon film transistor.

Background technology

General low-temperature polysilicon film transistor (the low temperature polycrystalline siliconthin film transistor that makes, LTPS TFT) step of array need use nearly that six to nine road masks carry out photoetching process (photo-etching-process, PEP), five road masks far beyond general amorphous silicon film transistor (hydrogenated amorphous silicon thin film transistor, α-Si:H TFT) are complicated and consuming time.In addition, at active matrix organic LED panel (active matrix organiclight-emitting diode, AMOLED) in the application, because complicated pixel circuit design framework, so must utilize low-temperature polysilicon film transistor to drive array makes, right its again because the insulating barrier of many one deck definition pixel electrode light-emitting zones (pixel define layer PDL), more makes required mask number increase to seven to ten roads.

See also Fig. 1, Fig. 1 is the structural representation of the thin-film transistor (TFT) that is applied in traditional organic LED panel.Prior art is when making organic LED panel 100, a glass substrate 102 is provided earlier, deposit a buffer insulation layer 104 and one deck amorphous silicon membrane (not shown) more in regular turn on glass substrate 102, and via quasi-molecule laser annealing (excimer laser annealing, ELA) etc. technology makes this amorphous silicon membrane crystallization again (recrystallize) become polysilicon membrane.Then utilize one first mask to carry out first photoetching process (PEP), to etch required active layer (activelayer) pattern in polysilicon membrane, deposit a gate insulator (gate insulator) 108 afterwards again and be covered in active layer and buffering insulating barrier 104 surfaces.

And then use second photoetching (PEP) of second mask to etch gate metal 110 by a metal deposition process and.Can utilize gate metal 110 as autoregistration (self-alignment) shielding subsequently, active layer 106 is carried out boron ion plasma injection technology, to form source electrode (source) 103 and drain electrode (drain) 105.Wherein, prior art is the needs of visual circuit design in addition, form polysilicon bottom electrode 107 and electrode of metal 111 in each pixel region, and isolate with gate insulator 108, constitute storage capacitors (storage capacitance, Cst) 113.

Then deposit interbedded insulating layer (inter-layer dielectric, ILD), and cover gate metal 110, electrode of metal 111 and gate insulator 108, utilize the 3rd mask to carry out the 3rd photoetching (PEP) again, in order to remove the part interlayer insulating film 112 and the gate insulator 108 of source electrode 103 and drain electrode 105 tops, to define via hole (via hole) 115.And then carry out another metal deposition process, and and utilize the 4th mask to carry out the 4th photoetching (PEP), etching metal levels 114 such as holding wire, drain metal on via hole 115 surfaces, and be electrically connected source electrode 103 and drain electrode 105 respectively.Passivation layer (the passivation layer) 116 that then deposits a planarization is on metal level 114 and interlayer insulating film 112, and utilize the 5th mask to carry out the 5th photoetching (PEP), to remove the part passivation layer 116 of metal level 114 tops that are electrically connected drain electrode 105.And then formation tin indium oxide (Indium Tin Oxide, ITO) the transparent conductive film (not shown) is on passivation layer 116, and utilize the 6th mask to carry out the 6th photoetching (PEP), with the transparency electrode 118 that defines suitable size, carry out a depositing operation subsequently again and utilize the 7th mask to carry out the 7th photoetching (PEP) to form pixel electrode insulating barrier (PDL) 120.Form the light-emitting diode (not shown) in transparency electrode 118 surfaces more at last, promptly finish organic LED panel 100 in the prior art.

In the prior art, must utilize seven road masks just can finish the making of aforementioned applications in thin film transistor (TFT) array, not only complex steps, complex process, and the expensive and bit errors (misalignment) that caused of many mask numbers also seriously reduce production capacity and rate of finished products.Therefore how to reduce the mask number when making, become one of important topic of organic light emitting diode display exploitation.

Summary of the invention

In view of this invention provides a kind of manufacture method of active matrix organic LED panel, to address the above problem.

Described according to most preferred embodiment of the present invention, a kind of manufacture method of active matrix organic LED panel is provided, wherein comprising provides substrate, form holding wire and drain metal on substrate, on substrate, form buffer insulation layer, form active layer on buffer insulation layer, the deposition gate insulator is covered on active layer and the buffering insulating barrier, gate insulator laminar surface in the active layer top forms gate metal, carry out the source ion implantation utmost point and drain electrode, in gate insulator, form via hole, form transparency electrode in via hole and gate insulator laminar surface, form the pixel electrode insulating barrier in etc. on the transparency electrode, and form light-emitting diode on transparency electrode.

The present invention has changed the positional structure of metal wire in the display panels of general low-temperature polysilicon film transistor array, make gate metal be positioned at the metal level top, and the making of omitting the interlayer insulating film of prior art, more utilize buffer insulation layer and gate insulator as the insulating barrier between metal level and the gate metal, to avoid it to be short-circuited, and the present invention more omits the making of passivation layer, makes mask count be reduced to six roads, to reach the target that reduces cost and simplify technology.

Description of drawings

Fig. 1 is the structural representation of light-emitting-diode panel in the prior art.

Fig. 2 to Fig. 8 is the process schematic representation of light-emitting-diode panel of the present invention.

The primary clustering symbol description

100,800 light-emitting-diode panels

102,202 glass substrates

103,213 source electrodes

104,206 buffer insulation layers

105,215 drain electrodes

106,208 active layers

107 polysilicon bottom electrodes

108,210 gate insulators

110,212 gate metals

111 electrode of metal

112 interlayer insulating films

113 storage capacitors

114,204 metal levels

115 via holes

116 passivation layers

118,214 transparency electrodes

120,216 pixel electrode insulating barriers

217 via holes

218 light-emitting diodes

Embodiment

Fig. 2 to Fig. 8 is the process schematic representation of the active matrix organic LED panel (AMOLED) according to the embodiment of the invention.As shown in Figure 2, at first provide a glass substrate 202 to be used as infrabasal plate, deposit one deck first metallic film (not shown) again on glass substrate 202, then utilize one first mask to come this first metallic film is carried out first photoetching (PEP), to form the metal level 204 of holding wire, drain metal etc.

Subsequently shown in the 3rd figure, in surface deposition one deck buffer insulation layer 206 of glass substrate 202 and cover on the metal level 204.Then on buffer insulation layer 206, deposit one deck amorphous silicon membrane (not shown), and, make this amorphous silicon membrane recrystallize into polysilicon membrane by annealing processs such as excimer laser.Utilize one second mask to come this polysilicon membrane (not shown) is carried out second photoetching (PEP) then, can obtain the pattern of required active layer 208, and active layer 208 is above the buffer insulation layer 206 between the metal level 204 of holding wire, drain metal, as shown in Figure 4.

Then, consult Fig. 5, at active layer 208 and buffering insulating barrier 206 surface depositions one gate insulator 210.Carry out one second deposit metal films technology then, to form one deck second metallic film (not shown) in gate insulator 210 surfaces, and utilize one the 3rd mask to carry out the 3rd photoetching (PEP), obtain gate metal 212 with etching, as shown in Figure 6, can utilize gate metal 212 as the autoregistration shielding subsequently, active layer 208 is carried out boron ion ion implantation technology, in active layer 208, to form source electrode 213 and drain electrode 215.

Note that gate metal 212 is positioned at the top of metal level 204 in last embodiment of the present invention, still, metal level 114 is positioned at the top of gate metal 110 in the prior art.

See also Fig. 7, then utilize one the 4th mask to carry out the 4th photoetching (PEP), etching gate insulator 210 and buffering insulating barrier 206 partly, until source electrode 213, drain electrode 215 and metal level 204 surfaces, to form a plurality of via holes 217 with source electrode 213 tops respectively at metal level 204 and drain electrode 215.For example form a transparent conductive film (not shown) then: tin indium oxide (ITO) or indium zinc oxide (indiumzinc oxide, IZO), and be covered in gate metal 212, metal level 204, source electrode 213, drain electrode 215 and grid 210 tops, utilize one the 5th mask that transparent conductive film is carried out the 5th photoetching (PEP) afterwards again, with the transparency electrode 214 that defines suitable size, and utilize transparency electrode 214 to be electrically connected metal level 204 and source electrode 213, and be electrically connected metal level 204 and the drain electrode 215 of being used as drain metal.

See also Fig. 8 then, utilize spin coating proceeding with one deck spin-coating glass (spin on glass, SOG) material, for example be that silicon dioxide or sensitization insulating material are evenly coated on transparency electrode 214, gate insulator 210 and the gate metal 212, to form the pixel electrode insulating barrier 216 of a planarization, and utilize one the 6th mask to carry out the 6th photoetching (PEP), with the pixel electrode insulating barrier 216 of etching part and expose the transparency electrode 214 that is electrically connected drain electrode 215.Last again in transparency electrode 214 surface formation one Organic Light Emitting Diode 218 that exposes, promptly finish the organic LED panel 800 among the present invention.Wherein, it should be noted that, the coverage of the transparency electrode 214 of present embodiment is greater than the metal level 204 that is electrically connected drain electrode 215, so therefore the light of Organic Light Emitting Diode 218 can form a bottom-emission (bottom emission) diode panel or upper and lower luminous organic LED panel simultaneously by upper and lower two directional divergences.

Than prior art, because the present invention has changed the positional structure of metal wire in the display panels of general low-temperature polysilicon film transistor (LTPSTFT) array, make gate metal be positioned at the metal level top, and the making of omitting the interlayer insulating film of prior art, more utilize buffer insulation layer and gate insulator as the insulating barrier between metal level and the gate metal, be short-circuited to avoid it.Moreover, pixel electrode insulating barrier of the present invention utilization be the spin-coating glass material, for example silicon dioxide is finished with spin coating method, its plat structure more helps subsequent technique, and the present invention more omits the making of passivation layer, make mask count be reduced to six roads, to reach the target that reduces cost and simplify technology.In addition, technology of the present invention can be applicable in the technology of display panels of general low-temperature polysilicon film transistor (LTPS TFT) array, not only only needing six road masks to prepare finishes, and more can utilize the different of the metal level that is electrically connected drain electrode and transparency electrode relative position, and make reflective, transmission-type and semi-transparent semi-reflecting display panels respectively.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. the manufacture method of an active matrix organic LED panel comprises:

One substrate is provided;

Form a metal level on this substrate;

Form a buffer insulation layer on this substrate and cover this metal level;

Form an active layer on this buffer insulation layer;

Deposit a gate insulator and cover this buffer insulation layer of this active layer;

This gate insulator laminar surface in this active layer top forms a gate metal;

Utilize this gate metal to do shielding this active layer is carried out the ion injection, in this active layer, to form an one source pole and a drain electrode;

This gate insulator of etching and this buffer insulation layer are to form a plurality of via holes on this metal level, this drain electrode and this source electrode;

Form a transparency electrode in described a plurality of via holes and this gate insulator laminar surface;

Form a pixel electrode insulating barrier on this transparency electrode, this gate metal and this gate insulator, this pixel electrode insulating barrier of etching part is with this transparency electrode of expose portion; And

On this transparency electrode, form a light-emitting diode.

2. manufacture method as claimed in claim 1, wherein this substrate includes a transparent glass substrate, an intrinsic substrate, a flexible plastic substrate and a metal substrate.

3. manufacture method as claimed in claim 1, the method that wherein forms this metal level also comprises:

Form one first metallic film at this substrate surface; And

This first metallic film of etching is to form the first metal layer.

4. manufacture method as claimed in claim 1, the method that wherein forms this active layer also comprises:

At this buffer insulation layer surface deposition one non-polysilicon membrane;

This non-polysilicon membrane is carried out crystallization processes again and again, is a polysilicon membrane so that this non-polysilicon membrane changes into; And

This polysilicon membrane of etching is to form this active layer.

5. manufacture method as claimed in claim 1, the method that wherein forms this gate metal also comprises:

Form one second metallic film at this gate insulator laminar surface; And

This second metallic film of etching is to form this gate metal.

6. manufacture method as claimed in claim 1, the method that wherein forms this transparency electrode and this pixel electrode insulating barrier also comprises:

Form a transparent conductive film at this gate insulator and this gate metal surface;

This transparent conductive film of etching is to form this transparency electrode; And

Utilize a spin coating proceeding on this transparency electrode, this gate insulator and this gate metal, to form this pixel electrode insulating barrier; And

On this gate insulator, form this transparency electrode.

7. manufacture method as claimed in claim 6, this transparency electrode coverage that wherein is electrically connected this drain electrode is greater than this drain metal, so that this active matrix organic LED panel forms a bottom-emission diode panel or upper and lower luminous organic LED panel.

8. manufacture method as claimed in claim 6, wherein this transparent conductive film be tin indium oxide and indium zinc oxide one of them.

9. manufacture method as claimed in claim 1, wherein this pixel electrode insulating barrier forms by spin coating silicon dioxide.