CN1921095B - 半导体芯片、显示屏板及其制造方法 - Google Patents

半导体芯片、显示屏板及其制造方法 Download PDF

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CN1921095B
CN1921095B CN2006101215580A CN200610121558A CN1921095B CN 1921095 B CN1921095 B CN 1921095B CN 2006101215580 A CN2006101215580 A CN 2006101215580A CN 200610121558 A CN200610121558 A CN 200610121558A CN 1921095 B CN1921095 B CN 1921095B
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insulating barrier
electrode pad
projection
display panel
substrate
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CN2006101215580A
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CN1921095A (zh
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赵源九
姜镐民
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体芯片及其制造方法，所述半导体芯片包括多个连接至集成在半导体基板上的驱动电路的凸块和设置在所述驱动电路上的有机绝缘层。所述有机绝缘层自所述半导体基板的延伸小于所述多个凸块，使得所述多个凸块的下边缘比所述有机绝缘层伸出得更远。所述多个凸块通过包括导电颗粒的各向异性导电膜连接到形成于下基板上的电极焊盘。

Description

半导体芯片、显示屏板及其制造方法
技术领域
本发明涉及一种半导体芯片以及采用所述半导体芯片的显示屏板，更具体而言，涉及一种能够提高各向异性导电颗粒的剩余比的半导体芯片及其制造方法，以及采用所述半导体芯片的显示屏板及其制造方法。
背景技术
作为流行的显示装置，有如下平板显示器：采用液晶的液晶显示器(LCD)、采用惰性气体放电的等离子体显示器(PDP)和采用有机发光二极管的有机电致发光显示器(OLED)。在这些显示器当中，PDP应用于大型电视，而LCD和OLED则以从小型产品到大型产品的各种尺寸应用于很多领域，例如蜂窝电话、笔记本电脑、监视器、电视机等。
这样的平板显示器包括具有用于显示图像的像素矩阵的显示屏板和用于驱动所述显示屏板的屏板驱动电路。将屏板驱动电路集成为半导体芯片形状，之后将其电连接到显示屏板。为了将这样的驱动电路芯片(下文称为驱动芯片)连接至显示屏板，通常采用带式自动接合(TAP)法和玻璃上芯片(COG)法。
TAP法采用各向异性导电膜(ACF)将其上封装了驱动芯片的带载封装(TCP)或膜上芯片(COF)附到显示屏板上。COG法采用ACF将驱动芯片直接封装到显示屏板上，这种方法主要应用于必须实现低成本、小尺寸和薄厚度的显示屏板。
图1示出了通过COG法封装在显示屏板基板上的驱动芯片的端子部分。
参考图1，驱动芯片20通过ACF 15电连接到形成于基板10上的电极焊盘12，并通过ACF 15附着于基板10。
更具体来讲，驱动芯片20包括形成于硅晶片22上的芯片焊盘(pad)24、保护硅晶片22并且具有用于暴露芯片焊盘24的接触孔的保护层26以及通过保护层26的接触孔连接至芯片焊盘24并且起着端子作用的凸块(bump)28。
通过ACF 15将驱动芯片20封装并附着到显示屏板的基板10上。在示范性实施例中，ACF 15可以包括具有导电颗粒16的ACF树脂14。可以将ACF 15涂覆到具有形成于其上的电极焊盘(electrode pad)12的基板10的焊盘区域(pad region)上。对准、加热并按压驱动芯片20，由此在显示屏板的基板10上封装驱动芯片20。ACF 15的导电颗粒16位于驱动芯片20的凸块28和形成于基板10上的电极焊盘12之间，并且将凸块28电连接至电极焊盘12。
凸块28和电极焊盘12之间的导电颗粒16的数量(下文称为“导电颗粒16的剩余比(remaining ratio)”)决定了凸块28和电极焊盘12之间的连接电阻。因此，导电颗粒16的剩余比应当具有足够的数量或水平，以确保驱动信号的可靠性。
由于在当前技术中，凸块和电极焊盘之间的导电颗粒的剩余量相对而言非常小，因此需要一项提高导电颗粒的剩余比的技术。尽管可以考虑提高包含在ACF中的导电颗粒的量来提高凸块下的导电颗粒的剩余比的方法，但是，这种方法提高了ACF的原材料的价格。
发明内容
本发明的示范性实施例提供了一种能够提高ACF的导电颗粒的剩余比的半导体芯片及其制造方法，以及采用所述半导体芯片的显示屏板及其制造方法。
本发明的一个示范性实施例提供了一种半导体芯片，所述半导体芯片包括多个连接至集成在半导体基板上的驱动电路的凸块和设置在所述驱动电路上的有机绝缘层。所述有机绝缘层自所述半导体基板的延伸小于所述多个凸块，使得所述多个凸块比所述有机绝缘层的下边缘伸出得更远。该多个凸块通过包括导电颗粒的各向异性导电膜连接到形成于下基板上的电极焊盘。
另一示范性实施例提供了一种根据本发明的制造半导体芯片的方法，所述方法包括形成多个连接至集成在半导体基板上的驱动电路的凸块和在所述驱动电路上形成有机绝缘层。所述有机绝缘层自所述半导体基板的延伸小于所述多个凸块，使得所述多个凸块比所述有机绝缘层伸出得更远。该多个凸块通过包括导电颗粒的各向异性导电膜连接到形成于下基板上的电极焊盘。
本发明的另一示范性实施例提供了一种在其内通过各向异性导电膜封装了半导体芯片的显示屏板，所述显示屏板包括：形成于基板上的，并通过所述各向异性导电膜中的导电颗粒连接至形成于所述半导体芯片上的凸块的电极焊盘；以及形成于所述基板上的，具有隔离所述电极焊盘的开放孔的第一绝缘层。
另一示范性实施例提供了一种根据本发明在其内封装了半导体芯片的显示屏板的制造方法，所述方法包括：在基板上形成连接至信号线的电极焊盘；在所述基板上形成第一绝缘层，所述第一绝缘层具有隔离位于所述基板上的所述电极焊盘的开放孔；以及通过各向异性导电膜在所述基板上封装所述半导体芯片，从而通过包含在所述各向异性导电膜中的导电颗粒将所述半导体芯片的凸块连接到所述电极焊盘。
本发明的另一示范性实施例提供了一种显示屏板，所述显示屏板包括：包括第一基板和第一绝缘层的半导体芯片；第二基板，其包括连接至形成于第二基板上的信号线的电极焊盘；以及将所述半导体芯片附着到所述第二基板上的各向异性导电膜，其包括将所述半导体芯片的凸块连接至所述电极焊盘的导电颗粒。所述半导体芯片包括多个连接至集成在所述第一基板上的驱动电路的凸块和设置在所述驱动电路上的第一绝缘层。第二绝缘层，设置在所述电极焊盘与相邻电极焊盘之间。
另一示范性实施例提供了一种根据本发明制造显示屏板的方法，所述方法包括：提供半导体芯片；提供包括暴露的电极焊盘的显示屏板；以及通过包括导电颗粒的各向异性导电膜在所述显示屏板内封装所述半导体芯片。形成所述半导体芯片包括形成多个连接至集成在所述第一基板上的驱动电路的凸块和在所述驱动电路上形成第一绝缘层。所述第一绝缘层自所述第一基板的延伸小于所述多个凸块。提供所述显示屏板包括在所述电极焊盘与相邻电极焊盘之间形成第二绝缘层。
本发明的另一示范性实施例提供了一种半导体芯片，其包括：  多个连接至集成在半导体基板上的驱动电路的凸块和形成厚度小于所述多个凸块的有机绝缘层，所述有机绝缘层形成于凸块对之间。所述多个凸块通过包括导电颗粒的各向异性导电膜连接到形成于下基板上的电极焊盘。另一示范性实施例提供了一种根据本发明制造半导体芯片的方法，所述方法包括：形成多个连接至集成在半导体基板上的驱动电路的凸块和形成厚度小于所述多个凸块的有机绝缘层，所述有机绝缘层形成于凸块对之间。所述多个凸块通过包括导电颗粒的各向异性导电膜连接到形成于下基板上的电极焊盘。
本发明的另一示范性实施例提供了一种显示屏板，所述显示屏板包括：半导体芯片，其包括多个连接至集成在第一基板上的驱动电路的凸块和所形成的厚度小于所述多个凸块的第一绝缘层，所述第一绝缘层形成于凸块对之间；包括连接至形成于其上的信号线的电极焊盘的第二基板；以及各向异性导电膜，其将所述半导体芯片附着到所述第二基板上，并且包括将所述半导体芯片的凸块连接到所述电极焊盘的导电颗粒。第二绝缘层，设置在所述电极焊盘与相邻电极焊盘之间。
另一示范性实施例提供了一种根据本发明制造显示屏板的方法，所述方法包括：提供半导体芯片，所述半导体芯片包括多个连接至集成在第一基板上的驱动电路的凸块和形成厚度小于所述多个凸块的第一绝缘层，所述第一绝缘层形成于凸块对之间；提供暴露电极焊盘的显示屏板；以及通过包括导电颗粒的各向异性导电膜在所述显示屏板内封装所述半导体芯片。提供所述显示屏板包括在所述电极焊盘与相邻电极焊盘之间形成第二有机绝缘层。
附图说明
通过下述接合附图的详细说明，本发明的上述和其他特征和优点将变得更加显见，其中：
图1示出了通过COF法封装在常规显示屏板内的驱动芯片；
图2是示出了形成于常规驱动芯片和基板上的多个凸块之间的接触部分的照片；
图3是部分示出了根据本发明在其内封装了COG型驱动芯片的显示屏板的示范性实施例的截面图；
图4是部分示出了图3所示的驱动芯片的下表面的平面图；
图5是示出了根据本发明的驱动芯片的凸块区域的示范性实施例的照片；
图6A到图6D是示出了图3所示的驱动芯片的制造方法的示范性实施例的截面图；
图7是部分示出了根据本发明在其内封装了COG型驱动芯片的显示屏板的另一示范性实施例的截面图；
图8是部分示出了图7所示的显示屏板的焊盘区域的平面图；
图9A到图9D是示出了图7所示的显示屏板的制造方法的示范性实施例的截面图；
图10是部分示出了根据本发明在其上封装了COG型驱动芯片的显示屏板的示范性实施例的截面图；以及
图11示意性地示出了一LCD屏板，其采用的显示屏板中封装了根据本发明的COG型驱动芯片的示范性实施例。
具体实施方式
下文中将参考附图更为充分地描述本发明，附图中展示了本发明的示范性实施例。不过，本发明可以以许多不同的形式实施，不应被视为受限于此处所述的示范性实施例。相反，提供这些实施例是为了使本公开透彻和完全，并将充分地把本发明的范围传达给本领域的技术人员。在附图中，出于清晰起见扩大了层和区域的尺寸以及相对尺寸。
应当理解，当称一元件或层在另一元件或层“上”或“连接至”另一元件或层时，所述元件或层可能直接位于另一元件或层上或直接连接至另一元件或层，或者存在中间元件或层。反之，当称一元件直接位于另一元件或层上，或者直接连接至另一元件或层时，则不存在中间元件或层。始终以类似的数字指示类似的元件。这里所用的术语“和/或”包括一个或多个相关所列项目的任何与全部组合。
应当理解，虽然这里可能使用术语第一、第二、第三等来描述多种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应被视为受限于这些术语。这些术语仅用于将某一元件、部件、区域、层或部分与其他区域、层或部分区分开。这样一来，在不背离本发明的教导的情况下，以下所讨论的第一元件、组件、区域、层或部分可以被称为第二元件、组件、区域、层或部分。
为了便于描述，这里可能使用诸如“下”、“上”等空间相对术语来描述如图所示的一个元件或特征与其他元件或特征的关系。应当理解，空间相对术语意在包括除图示方向之外的在使用中或在工作中的器件的不同方向。例如，如果将图中的器件反转，那么相对于其他元件或特征被描述为“下”的元件将相对于其他元件或特征指向“上”。这样一来，示范性术语“下”可以包括之上和之下两种方向。器件可以采取其他取向(旋转90度或者在其他方向)，并对这里所用的空间关系描述语进行相应的解释。
这里所用的术语仅仅是为了描述特定的实施例，并不意在限制本发明。如这里所用的，单数形式“一”和“该”意在同时包括复数形式，除非上下文另行明确指出。还要理解的是，本说明书中所用的术语“包括”指明所述特征、整数、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整数、步骤、操作、元件、组件和/或其组合的存在或增加。
这里参考截面图描述本发明的实施例，所述截面图为本发明的理想化实施例(以及中间结构)的示意图。照此，可以预见到由于例如制造技术和/或容限会引起图示形状的变化。这样一来，本发明的实施例不应被解释为受限于这里图示的特定的区域形状，而是包括因(例如)制造而产生的形状变化。
例如，图示为矩形的注入区通常具有圆形的或弯曲的功能部件和/或在其边缘处具有注入浓度的梯度，而不是从注入区到非注入区具有二元变化。类似地，通过注入形成的掩埋层可能导致在所述掩埋层和通过其发生注入的表面之间的区域内存在一些注入。这样一来，图示的区域从本质上讲是示意性的，它们的形状不意在展示器件区域的实际形状，且不意在限制本发明的范围。
除非另行定义，这里所用的所有术语(包括技术和科学术语)具有本发明所属技术领域的普通技术人员所通常理解的同样含义。还要理解的是，诸如在通用词典中所定义的那些术语应当被解释为有着与其在相关技术和本公开的上下文中的含义相一致的含义，除非这里明确加以定义，否则不应被解释为理想化的或过度形式的意义。
以下将参考附图详细描述本发明。
在描述本发明的示范性实施例之前，现在，将参考图2描述驱动芯片的凸块和显示屏板的焊盘之间的ACF的导电颗粒的剩余比可能相对较低的原因。
图2是说明形成于常规驱动芯片上的多个凸块和基板之间的接触部分的照片。
参考图2，可以看出凸块4之间的空隙6内ACF导电颗粒8的剩余比高于位于封装在基板2上的驱动芯片的凸块4之下的区域的剩余比。在基板2上涂覆ACF，之后使其对准、对其加热并将其按压到基板2上，这时作用在位于封装在基板2上的驱动芯片的凸块4之下的ACF树脂上的压力大于作用在凸块4之间的空隙6内的压力。由于封装在基板2上的驱动芯片的凸块4之下和凸块4之间的空隙6内两处之间存在压力差，因此，ACF树脂从封装在基板2上的驱动芯片的凸块4之下向凸块4之间的空隙6流动。ACF导电颗粒8朝向或者随着ACF树脂的流动而移动。因此，降低了封装在基板2上的驱动芯片的凸块4之下的导电颗粒8的剩余比。最终汇集在凸块4之间的空隙6内的导电颗粒8变得越来越大。因此，空隙6内的导电颗粒8的聚集可能引起凸块4之间的电短路。可靠性可能由于封装在基板2上的驱动芯片的凸块4之下的导电颗粒8的剩余比的降低而下降。
在根据本发明的示范性实施例中，可以通过在制造过程中，降低封装在基板上的驱动芯片的凸块之下和凸块之间的空隙内两处之间的压力差，即本质上减少ACF导电颗粒的流动，来提高存在于封装在基板上的驱动芯片的凸块之下的导电颗粒的剩余比。
以下将参考附图详细描述本发明。
图3是部分示出了根据本发明在其内封装了驱动芯片60的显示屏板40的示范性实施例的截面图。图4和图5分别是示出了在其上形成了图3所示的驱动芯片60内的凸块54的下表面的示范性实施例的平面图和照片。
参考图3，驱动芯片60通过ACF 45电连接到形成于显示屏板40的基板30上的电极焊盘36上，并且通过ACF 45附着于基板30。
显示屏板40包括形成于下基板30上并连接至图像显示部分的信号线(未示出)的电极焊盘36。
电极焊盘36包括从图像显示部分的信号线延伸出来的下电极焊盘32和通过穿透绝缘层38的接触孔连接至下电极焊盘32的上电极焊盘34。在示范性实施例中，下电极焊盘32可以由不透明金属连同图像显示部分的信号线一同形成。上电极焊盘34可以由透明导电材料形成，用于保护下电极焊盘32。在一个示范性实施例中，由透明导电材料形成的上电极焊盘34可以和用于透射图像显示部分中的子像素单元(未示出)所发出的光的像素电极(未示出)一起被构图。
驱动芯片60包括连接至形成于硅晶片50上的驱动电路的芯片焊盘52、形成于硅晶片50上的保护层56和凸块54。保护层56包括暴露芯片焊盘52的接触孔。凸块54通过保护层56的接触孔连接至芯片焊盘52，凸块54起着端子的作用。驱动芯片60还可以包括围绕凸块54的有机绝缘层58。在示范性实施例中，有机绝缘层58所具有的沿基本垂直于硅晶片50的方向测量的厚度可以小于凸块54的厚度。在另一示范性实施例中，有机绝缘层58的下边缘可以不延伸至凸块的下边缘，其可以位于保护层56的表面和凸块54的下边缘之间。
在示范性实施例中，芯片焊盘52可以包括，但不限于，诸如铝(Al)的金属。凸块54可以包括，但不限于，诸如金(Au)的金属。在其他示范性实施例中，可以在芯片焊盘52和凸块54之间形成用于保护芯片焊盘52的屏障层(barrier layer)53。屏障层53可以包括，但不限于，金属。
保护层56形成于其上形成了芯片焊盘52的硅晶片50上，其保护形成了驱动电路之处的硅晶片50。保护层56包括暴露芯片焊盘52的接触孔。在示范性实施例中，保护层56可以包括，但不限于，诸如SiNx的绝缘材料。
屏障层53和凸块54连接到通过保护层56的接触孔暴露的芯片焊盘52。
在其上形成了凸块54的保护层56上形成有机绝缘层58，以保护包含在驱动芯片60内的驱动电路。在一个示范性实施例中，有机绝缘层58可能包括，但不限于，聚酰亚胺系列(series)。如图4和图5所示，有机绝缘层58延伸至其中形成了凸块54的驱动芯片60的***区域，并且包括暴露凸块54的开放孔(open hole)55。还可以将这一***区域称为“端子区域”。
在示范性实施例中，有机绝缘层58的高度或厚度可以小于凸块54的高度或厚度。在将驱动芯片60封装在基板30上时，降低了驱动芯片60的凸块54之下和凸块54之间的空隙内两处之间的压力差。有利地，可以防止ACF导电颗粒42从驱动芯片60的凸块54之下流到凸块54之间的空隙内。如图4和图5所示，形成于有机绝缘层58上的开放孔55具有比凸块54宽的截面积，从而彻底、充分地暴露凸块54。将开放孔55的边缘与凸块54隔开，形成缝隙，从而充分确保可以用来与ACF导电颗粒42接触的凸块54的截面积。在备选实施例中，开放孔55可以具有基本类似于或基本等于凸块54的截面积，从而使有机绝缘层58可以与凸块54的侧面接触。
再次参考图3，通过ACF 45将驱动芯片60封装到显示屏板40的基板30上。ACF 45可以包括包含导电颗粒45的ACF树脂44。在其上形成了电极焊盘36的基板30的焊盘区域上涂覆ACF 45，并对准驱动芯片60，对其加热并按压，从而将驱动芯片60封装到显示屏板40的基板30上。由于厚度小于凸块54的有机绝缘层58占据了凸块54之间的空隙，因而可以降低驱动芯片60的凸块54之下和凸块之间的空隙内(或者有机绝缘层58之下)两处之间的压力差。与压力差的下降相称的是，导电颗粒42的流动与ACF树脂44的流动一同减少，因而可以减少从驱动芯片60的凸块54之下流到凸块54的空隙内的导电颗粒42的数量。有利地，由于提高了，或实质上增大了凸块54之下的导电颗粒42的剩余比，因而可以降低驱动芯片60的凸块54和显示屏板40的电极焊盘36之间的连接电阻。
在示范性实施例中，如果有机绝缘层58的高度大于等于凸块54的高度，从而使得有机绝缘层58的下边缘与凸块54的下边缘基本位于同一水平面上，那么，降低了凸块54和电极焊盘36之间的导电颗粒42的变动速率(modification rate)，连接电阻可能增大。有机绝缘层58从保护层56或硅晶片50向下延伸。在一个示范性实施例中，优选形成延伸至位于凸块54的下边缘之上的位置的，或者所包括的厚度比凸块54的小的有机绝缘材料58。
图6A到图6D是示出了根据本发明的图3所示的驱动芯片60的制造方法的示范性实施例的截面图。
参考图6A，连同驱动电路的电极(未示出)一起，在硅晶片50上形成芯片焊盘52。在示范性实施例中，可以通过在硅晶片50上淀积诸如Al的金属层，并通过光刻工艺和蚀刻工艺对所述金属层构图，而连同驱动电路的电极一起形成芯片焊盘52。
参考图6B，在其上形成了驱动电路和芯片焊盘52的硅晶片50上形成保护层56，通过穿透保护层56形成暴露芯片焊盘52的接触孔51。在示范性实施例中，可以通过在其上形成了驱动电路和芯片焊盘52的硅晶片上淀积诸如SiNx的无机绝缘材料，并采用光刻工艺和蚀刻工艺对所述无机绝缘材料构图而形成具有接触孔51的保护层56。
参考图6C，形成屏障金属层53和凸块54。凸块54通过芯片焊盘52的部分连接至芯片焊盘52，所述的芯片焊盘52的部分通过保护层56的接触孔51暴露。在示范性实施例中，可以通过在保护层56上淀积诸如Au/Ni/Ti的屏障金属层和诸如Au的凸块金属，并采用光刻工艺和蚀刻工艺对这些金属层构图而形成屏障金属层53和凸块54。
参考图6D，在保护层56上形成用于保护驱动电路并暴露凸块54的有机绝缘层58。在示范性实施例中，，可以通过在其上形成了凸块54的保护层56上形成聚酰亚胺系列的感光有机绝缘层，并通过光刻工艺对所述有机绝缘层进行曝光和显影而形成有机绝缘层58。
在一个示范性实施例中，通过在其上形成了电极焊盘36的基板30上涂覆ACF 45，并在所述ACF 45上对准、加热并按压驱动芯片60来封装通过图6A到图6D的工艺完成的驱动芯片60。ACF 45可以包括ACF树脂44和导电颗粒42。有利地，通过存在于凸块54之间的空隙内的有机绝缘层58减少ACF树脂44和导电颗粒42在驱动芯片60的区域内的流动，由此提高并改善对应于电极焊盘的凸块54之下的导电颗粒42的剩余比。在另一示范性实施例中，有机绝缘层58可以优选包括比凸块54更小的高度或厚度。
图7是部分示出了根据本发明在其内封装了驱动芯片60的显示屏板40的另一示范性实施例的截面图，图8是示出了图7所示的显示屏板40的焊盘区域的平面图。
参考图7，除了在电极焊盘36之间的空隙内，而不是在驱动芯片60的凸块54之间的空隙内，形成有机绝缘层62之外，其内封装了驱动芯片60的显示屏板40具有与图3所示的相同的构造。因此，将省略对重复元件的详细说明。
驱动芯片60包括连接至形成于硅晶片50上的驱动电路(未示出)的芯片焊盘52、形成于硅晶片50上并且具有暴露芯片焊盘52的接触孔的保护层56以及通过保护层56的接触孔连接至芯片焊盘52并且起着端子作用的凸块54。在示范性实施例中，驱动芯片60还可以包括在除了形成凸块54的端子区域以外的驱动电路区域的保护层56上形成的有机绝缘层(未示出)，以保护驱动电路区域。还可以将形成了凸块54的端子区域视为驱动芯片60的“***区域”。在其他示范性实施例中，驱动芯片60还可以包括形成于芯片焊盘52和凸块54之间的屏障金属层53。
在显示屏板40的下基板30上形成电极焊盘36。电极焊盘包括从图像显示部分的信号线(未示出)延伸出来的下电极焊盘32和通过穿透绝缘层38的接触孔连接至下电极焊盘32的上电极焊盘34。显示屏板40包括沿基本垂直于基板30的方向形成的高度或厚度大于电极焊盘36的有机绝缘层62，以隔离电极焊盘36。有机绝缘层62从绝缘层38或基板30向上延伸，并与电极焊盘36和凸块54间隔一定距离设置有机绝缘层62。可以在与凸块54的下边缘基本相同的平面上设置有机绝缘层62的上边缘。
在下基板30的绝缘层38上形成有机绝缘层62。如图8所示，在有机绝缘层62上形成与电极焊盘36隔开的开放孔63，以隔离电极焊盘36。形成这一有机绝缘层62，使之具有比电极焊盘36大的高度。在示范性实施例中，如果通过ACF 45封装驱动芯片60，那么可以形成从硅晶片50向下延伸并且高度小于驱动芯片60的凸块54的有机绝缘层62。有利地，当在包括从基板30向上延伸到大于电极焊盘36的高度的有机绝缘层62的基板30上封装驱动芯片60时，降低了驱动芯片60的凸块54之下和凸块54之间的空隙内两处之间的压力差，防止了ACF导电颗粒42从驱动芯片60的凸块54之下流到凸块54之间的空隙内。
在示范性实施例中，如图8所示，围绕电极焊盘36的开放孔63可以具有比电极焊盘36更宽的截面积。换言之，将开放孔63的边缘与电极焊盘36的边缘隔开，实质上在电极焊盘36和有机绝缘层62之间形成了缝隙，从而充分确保能够与ACF导电颗粒42接触的电极焊盘36和凸块54的足够大尺寸的截面积。在备选实施例中，开放孔63可以具有与电极焊盘36基本类似或实际相同的截面积，使得有机绝缘层62可以与电极焊盘36的侧面接触。
在示范性实施例中，可以通过在基板30的焊盘区域上涂覆ACF 45，并对准、加热和按压驱动芯片60而在显示屏板40的基板30上封装具有这样的构造的驱动芯片60。ACF 45可以包括含有导电颗粒42的ACF树脂44。由于有机绝缘层62设置于凸块54之间，并且包括小于凸块54的高度，因此，降低了凸块54之下和凸块54之间的空隙内两处之间，即凸块54之下和从焊盘30突出的有机绝缘层62之上两处之间的压力差。导电颗粒42连同ACF树脂44的流动降低了，由此减少了从凸块54之下流到凸块54之间的空隙内的导电颗粒42的数量。有利地，增大了凸块54之下的导电颗粒42的剩余比，并且可以降低驱动芯片60的凸块54和显示屏板40的电极焊盘36之间的连接电阻。
图9A到图9D是示出了根据本发明的图7所示的显示屏板40的制造方法的示范性实施例的截面图。
参考图9A，在基板30上连同图像显示部分的信号线(未示出)一起形成下电极焊盘32。在示范性实施例中，可以通过在基板30上淀积Al或Mo系列的金属层，并采用光刻工艺和蚀刻工艺对所述金属层构图，而连同图像显示部分的信号线一起形成下电极焊盘32。
参考图9B，在其上连同图像显示部分的信号线一起形成了下电极焊盘32的基板30上形成绝缘层38。在绝缘层38内形成暴露下电极焊盘32的接触孔61。在示范性实施例中，可以通过在其上形成了信号线和下电极焊盘32的基板30上淀积诸如SiNx的无机绝缘材料，并采用光刻工艺和蚀刻工艺对所述无机绝缘材料构图，而形成具有接触孔61的绝缘层38。
参考图9C，在绝缘层38上形成具有暴露下电极焊盘32的开放孔63的有机绝缘层62。在示范性实施例中，可以通过在绝缘层38上淀积聚酰亚胺系列的感光有机绝缘材料，并通过光刻工艺对所述有机绝缘材料进行曝光和显影而形成有机绝缘层62。
参考图9D，形成上电极焊盘34，其连接至通过有机绝缘层62的开放孔63暴露的下电极焊盘32。在示范性实施例中，通过在有机绝缘层62上淀积透明导电材料，并采用光刻工艺和刻蚀过程对所述透明导电材料构图而形成上电极焊盘34。在其他示范性实施例中，可以连同由图像显示部分中的子像素单元(未示出)形成的像素电极(未示出)一起形成上电极焊盘34。
在一个示范性实施例中，在通过图9A到图9D所示的工艺完成的基板30的焊盘区域上涂覆ACF 45，并通过在ACF 45上对准、加热并按压驱动芯片60封装驱动芯片60。在有机绝缘层62存在于凸块54之间的空隙内的区域中，ACF树脂44和导电颗粒42的流动降低了，其中，有机绝缘层62包括比凸块54低的高度。有利地，提高了凸块54之下的导电颗粒42的剩余比。
图10是部分示出了根据本发明在其内封装了驱动芯片60的显示屏板40的另一示范性实施例的截面图。
其中封装了驱动芯片60的显示屏板40具有与图3所示的相同的元件，除了在电极焊盘36之间的空隙内额外形成了第二有机绝缘层62之外。因此，将省略对重复元件的详细说明。
驱动芯片60包括连接至形成于硅晶片50上的驱动电路(未示出)的芯片焊盘52、形成于硅晶片50上并且具有暴露芯片焊盘52的接触孔的保护层56以及通过保护层56的接触孔连接至芯片焊盘52并且起着端子作用的凸块54。第一有机绝缘层58形成于保护层56上，并围绕凸块54。有机绝缘层58包括比凸块54低的高度。如图4、图5和图10所示，第一有机绝缘层58延伸至形成了凸块54的端子区域，并且包括暴露凸块54的开放孔55，所述端子区域又称为驱动芯片60的***区域。如图4和图5所示，开放孔55形成于第一有机绝缘层58内，并具有比凸块54宽的截面积，从而充分确保能够与ACF导电颗粒42接触的凸块54的截面积。在备选示范性实施例中，开放孔55可以具有基本类似于或基本等于凸块54的截面积，从而使有机绝缘层58与凸块54的侧面接触。在一个示范性实施例中，通过参考图6A到图6D描述的制造方法完成具有这样的构造的驱动芯片60。
在显示屏板40的下基板30上形成电极焊盘36。电极焊盘36包括从图像显示部分的信号线(未示出)延伸出来的下电极焊盘32和通过穿透绝缘层38的接触孔连接至下电极焊盘32的上电极焊盘34。显示屏板40包括形成于基板30上，并且围绕电极焊盘36的第二有机绝缘层62。自绝缘层38延伸的第二有机绝缘层62包括比电极焊盘36大的高度。
在下基板30的绝缘层38上形成有第二机绝缘层62。如图8所示，在第二有机绝缘层62上形成开放孔63，其围绕电极焊盘36，开放孔63的边缘与电极焊盘36通过缝隙隔开。有机绝缘层62自绝缘层38延伸，并且在高度上高于电极焊盘36。在通过ACF 45封装驱动芯片60时，有机绝缘层62延伸至比驱动芯片60的凸块54低的高度。使第二有机绝缘层62与第一有机绝缘层56间隔预定距离或间隔。如图8所示，第二有机绝缘层62的开放孔63具有比电极焊盘36更宽的截面积，从而充分确保接触ACF导电颗粒42的电极焊盘36和凸块54的截面积。在备选示范性实施例中，第二有机绝缘层62的开放孔63可以具有与电极焊盘36基本相同的截面积，使得第二有机绝缘层62可以与电极焊盘36的侧面接触。在一个示范性实施例中，可以通过参考图9A到图9D描述的制造方法完成具有这样的构造的显示屏板。
在示范性实施例中，第一有机绝缘层58和第二有机绝缘层62可以包括分别沿基本平行于硅晶片50和基板30的方向测量的基本相同的宽度。第一有机绝缘层58和第二有机绝缘层62可以基本上分别位于成对的凸块54和成对的电极焊盘36的中央，或者可以靠近一对凸块54和/或一对电极焊盘36中的一个设置。第一有机绝缘层58和第二有机绝缘层62可以处于相互对应的位置，使得它们的宽度基本一致，或者使得它们的宽度相对于彼此偏移(offset)。
在一个示范性实施例中，通过在其上形成了电极焊盘36的基板30的焊盘区域上涂覆ACF 45，并对准、加热并按压驱动芯片60而在显示屏板40的基板30上封装驱动芯片60。由于在凸块54之间的空隙内存在厚度小于凸块54的第一有机绝缘层58，在电极焊盘36之间的空隙内存在与第一有机绝缘层58以规则间隔隔开的第二有机绝缘层62，因此降低了凸块54之下和凸块54之间的空隙内两处之间的压力差。也就是说，可以降低凸块54之下与第一和第二有机绝缘层58和62之间的空隙内两处之间的压力差。导电颗粒42连同ACF树脂44的流动降低了，可以减少从凸块54之下移动到凸块54之间的空隙内的导电颗粒42的数量。有利地，提高或增大了凸块54之下的导电颗粒42的剩余比，因而可以降低驱动芯片60的凸块54和显示屏板40的电极焊盘36之间的连接电阻。
在示范性实施例中，可以将向其内封装了根据本发明的示范性实施例的驱动芯片的显示屏板应用于诸如LCD和OLED的平板显示器。现在，将参考图11描述应用了本发明的示范性实施例的LCD的示范性实施例。
图11示意性地示出了一LCD屏板，其采用的显示屏板中封装了根据本发明的驱动芯片的示范性实施例。
图11所示的LCD屏板包括下基板30和上基板70，二者之间插置有液晶。上基板70使下基板30的***区域暴露出来。也可以将所述***区域视为其上形成了栅极驱动芯片80和数据驱动芯片90的下基板30的电路区域。
下基板30的显示区域包括沿彼此横陈(transverse to each other)的方向彼此相交，以形成大体的矩阵形排列的栅极线GL和数据线DL、连接在栅极线GL和数据线DL的交接处的薄膜晶体管TFT以及连接至薄膜晶体管TFT的子像素单元的像素电极。像素电极可以与形成于上基板70中的公共电极交叠，在其间***液晶，以形成液晶单元(cell)。也可以将所述液晶单元称为液晶电容器Clc。薄膜晶体管TFT响应来自栅极线GL的栅极信号为像素电极提供来自数据线DL的数据信号。依赖提供至像素电极的数据信号和提供至公共电极的公共电压Vcom之间的差值驱动具有介电各向异性的液晶，并控制透光度。
在示范性实施例中，可以通过针对本发明的示范性实施例所述的COG方法在下基板30的***区域上封装用于驱动栅极线GL的栅极驱动芯片80和用于驱动数据线DL的数据驱动芯片90。
在其他示范性实施例中，通过ACF在下基板30上封装栅极驱动芯片80，并将栅极驱动芯片80连接到自栅极线GL延伸的栅极焊盘上。通过ACF在下基板30上封装数据驱动芯片90，并将数据驱动芯片90连接至自数据线DL延伸的数据焊盘上。可以在栅极驱动芯片和数据驱动芯片80和90的凸块之间的空隙内形成第一有机绝缘层。可以在下基板30的栅极焊盘之间的空隙内以及下基板30的数据焊盘之间的空隙内形成第二有机绝缘层。在备选示范性实施例中，在栅极和数据驱动芯片80和90的凸块之间的空隙内形成第一有机绝缘层，在下基板30的栅极焊盘之间的空隙内以及下基板30的数据焊盘之间的空隙内形成第二有机绝缘层。当在下基板30上封装栅极和数据驱动芯片80和90时，减少了导电颗粒连同ACF树脂的流动。可以减少从凸块54之下流到凸块54之间的空隙内的导电颗粒42的数量。有利地，增大了凸块54之下的导电颗粒42的剩余比，并且可以降低驱动芯片60的凸块54和显示屏板40的电极焊盘36之间的连接电阻。
在根据本发明的半导体芯片及其制造方法的示范性实施例中，当在显示屏板内封装半导体芯片时，通过在凸块之间的空隙内提供有机绝缘层减少了ACF的流动，由此提高了存在于凸块和焊盘之间的导电颗粒的剩余比。
在根据本发明的半导体芯片及其制造方法的示范性实施例中，当在显示屏板内封装半导体芯片时，通过在焊盘之间的空隙内提供有机绝缘层减少了ACF的流动，由此提高了存在于凸块和焊盘之间的导电颗粒的剩余比。
根据本发明的在其内封装了半导体芯片的显示屏板及其制造方法的另一示范性实施例包括位于驱动芯片的凸块之间的空隙内的第一有机绝缘层和位于显示屏板的焊盘之间的空隙内的第二有机绝缘层。有利地，当在包括这一构造的显示屏板内封装半导体芯片时，降低了ACF的流动，可以提高存在于凸块和焊盘之间的导电颗粒的剩余比。
在根据本发明的其内封装了半导体芯片的显示屏板及其制造方法的另一示范性实施例中，可以通过提高ACF导电颗粒的剩余比确保半导体芯片和显示屏板之间的连接的可靠性，并且可以通过减少包含在ACF内的导电颗粒的数量有利地降低ACF原材料的价格。
在根据本发明的其内封装了半导体芯片的显示屏板及其制造方法的另一示范性实施例中，通过提高ACF导电颗粒的剩余比，可以降低适于高分辨率的凸块的面积和间距，还降低了成本。
尽管已经参考本发明的优选实施例对本发明进行了图示和描述，但是，本领域技术人员将理解，在不背离权利要求限定的本发明的精神和范围的情况下，可以在其中做出各种形式和细节上的改变。
本申请要求于2005年8月24日提交的韩国专利申请No.2005-0077657的优先权以及所有权益，在此将其全文引入以供参考。

Claims (13)

1.一种显示屏板，包括：
半导体芯片，包括：
多个连接至集成在第一基板上的驱动电路的凸块；以及
设置在所述驱动电路上并位于彼此相邻的两个凸块之间的第一绝缘层，
其中，所述第一绝缘层自所述第一基板的延伸小于所述多个凸块；
第二基板，其包括：
分别连接至形成于所述第二基板上的多个信号线的多个电极焊盘；
各向异性导电膜，其将所述半导体芯片附着到所述第二基板上，并且包括将所述半导体芯片的凸块连接至所述电极焊盘的导电颗粒；以及
第二绝缘层，设置在彼此相邻的两个电极焊盘之间并具有隔离每个电极焊盘的开放孔，
其中所述第一绝缘层和所述第二绝缘层减小相邻凸块之间的空间，从而所述第一绝缘层和所述第二绝缘层防止连接到所述凸块的所述导电颗粒移动到相邻凸块之间的空间。
2.根据权利要求1所述的显示屏板，其中，所述第一绝缘层和所述第二绝缘层为有机绝缘层。
3.根据权利要求1所述的显示屏板，其中，每个所述电极焊盘包括：
连接至形成于所述第二基板上的所述信号线的下电极焊盘；以及
通过形成于所述下电极焊盘上的第三绝缘层的接触孔连接至所述下电极焊盘的上电极焊盘。
4.根据权利要求1所述的显示屏板，其中，形成于所述第二绝缘层上的所述开放孔的截面积大于每个电极焊盘的截面积。
5.根据权利要求1所述的显示屏板，其中，所述第二绝缘层自所述第二基板延伸得比每个电极焊盘远。
6.根据权利要求1所述的显示屏板，其中，当在所述第二基板上封装所述半导体芯片时，所述第一和第二绝缘层以预定间隔相互隔开。
7.一种制造显示屏板的方法，所述方法包括：
提供半导体芯片，制造所述半导体芯片的方法包括：
形成多个连接至集成在第一基板上的驱动电路的凸块；以及
形成第一绝缘层，所述第一绝缘层在所述驱动电路上并位于彼此相邻的两个凸块之间，
其中，所述第一绝缘层自所述第一基板的延伸小于所述多个凸块；
提供包括暴露的多个电极焊盘的所述显示屏板；以及
通过包括导电颗粒的各向异性导电膜封装所述半导体芯片和所述显示屏板，
其中提供所述显示屏板包括形成第二绝缘层，所述第二绝缘层设置在彼此相邻的两个电极焊盘之间并具有隔离每个电极焊盘的开放孔，
其中所述第一绝缘层和所述第二绝缘层减小相邻凸块之间的空间，从而所述第一绝缘层和所述第二绝缘层防止连接到所述凸块的所述导电颗粒移动到相邻凸块之间的空间。
8.根据权利要求7所述的方法，其中，形成每个所述电极焊盘的方法包括：
在所述第二基板上形成连接至所述信号线的下电极焊盘；
形成具有暴露所述下电极焊盘的接触孔的第三绝缘层；以及
形成通过所述接触孔连接至所述下电极焊盘的上电极焊盘。
9.根据权利要求7所述的方法，其中，所述开放孔的截面积大于每个电极焊盘的截面积。
10.根据权利要求7所述的方法，其中，所述第二绝缘层自所述第二基板突出得比每个电极焊盘远。
11.根据权利要求7所述的方法，其中，当在所述基板上封装所述半导体芯片时，所述第一和第二绝缘层以预定距离彼此隔开。
12.一种显示屏板，包括：
半导体芯片，其包括多个连接至集成在第一基板上的驱动电路的凸块和所形成的厚度小于所述多个凸块的第一绝缘层，所述第一绝缘层形成于凸块对之间；
第二基板，其包括分别连接至形成于其上的多个信号线的多个电极焊盘；
各向异性导电膜，其将所述半导体芯片附着到所述第二基板上，并且包括将所述半导体芯片的凸块连接至所述电极焊盘的导电颗粒；以及
第二绝缘层，设置在成对的电极焊盘之间并具有隔离每个电极焊盘的开放孔，
其中所述第一绝缘层和所述第二绝缘层减小相邻凸块之间的空间，从而所述第一绝缘层和所述第二绝缘层防止连接到所述凸块的所述导电颗粒移动到相邻凸块之间的空间。
13.一种制造显示屏板的方法，所述方法包括：
提供半导体芯片，所述半导体芯片包括多个连接至集成在第一基板上的驱动电路的凸块和所形成的厚度小于所述多个凸块的第一有机绝缘层，所述第一有机绝缘层形成于凸块对之间；
提供包括多个暴露的电极焊盘的所述显示屏板；以及
通过包括导电颗粒的各向异性导电膜在所述显示屏板内封装所述半导体芯片，
其中提供所述显示屏板包括形成第二有机绝缘层，所述第二有机绝缘层在成对的电极焊盘之间并具有隔离每个电极焊盘的开放孔，
其中所述第一绝缘层和所述第二绝缘层减小相邻凸块之间的空间，从而所述第一绝缘层和所述第二绝缘层防止连接到所述凸块的所述导电颗粒移动到相邻凸块之间的空间。
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Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2841454B1 (fr) 2002-07-01 2004-10-22 Jean Pierre Delmotte "appareil de cuisson d'aliments de type barbecue avec une plaque de regulation multi-fonctionnelle"
JP2009527121A (ja) * 2006-02-15 2009-07-23 エヌエックスピー ビー ヴィ 半導体パッケージの製造方法、パッケージ基板、および集積回路（ｉｃ）デバイス
JP2008166381A (ja) * 2006-12-27 2008-07-17 Sanyo Electric Co Ltd 半導体装置及びその製造方法
KR100810242B1 (ko) * 2007-02-13 2008-03-06 삼성전자주식회사 반도체 다이 패키지와 그를 이용한 내장형 인쇄회로 기판
JP2009282285A (ja) * 2008-05-22 2009-12-03 Mitsubishi Electric Corp 画像表示装置、およびその実装検査方法
JP2011009363A (ja) * 2009-06-24 2011-01-13 Nec Corp 半導体装置及びその製造方法並びにこれを用いた複合回路装置
TWI412107B (zh) * 2009-10-02 2013-10-11 Ind Tech Res Inst 凸塊結構、晶片封裝結構及該凸塊結構之製備方法
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
CN102044513A (zh) * 2009-10-21 2011-05-04 日月光半导体制造股份有限公司 半导体组件
TW201117336A (en) * 2009-11-05 2011-05-16 Raydium Semiconductor Corp Electronic chip and substrate providing insulation protection between conducting nodes
TW201121006A (en) * 2009-12-03 2011-06-16 Hannstar Display Corp Connection structure for chip-on-glass driver IC and connection method therefor
US8426251B2 (en) * 2010-01-07 2013-04-23 Infineon Technologies Ag Semiconductor device
CN102237329B (zh) * 2010-04-27 2013-08-21 瑞鼎科技股份有限公司 芯片结构及其芯片接合结构与制造方法
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
CN102064135B (zh) * 2010-10-21 2015-07-22 日月光半导体制造股份有限公司 具有金属柱的芯片及具有金属柱的芯片的封装结构
KR101822012B1 (ko) * 2010-12-07 2018-01-26 삼성디스플레이 주식회사 유기전계발광 표시 장치 및 그 제조 방법
TWM408126U (en) * 2010-12-10 2011-07-21 Chunghwa Picture Tubes Ltd Conductive pad structure, chip package structure and active device array substrate
CN103299410B (zh) * 2011-01-26 2016-01-27 株式会社村田制作所 电子元器件模块及电子元器件单元
KR20130013515A (ko) * 2011-07-28 2013-02-06 삼성디스플레이 주식회사 유기 발광 표시 장치
TWI531835B (zh) 2011-11-15 2016-05-01 友達光電股份有限公司 顯示面板
US9368437B2 (en) 2011-12-31 2016-06-14 Intel Corporation High density package interconnects
WO2013101241A1 (en) 2011-12-31 2013-07-04 Intel Corporation Organic thin film passivation of metal interconnections
JP2014053597A (ja) * 2012-08-09 2014-03-20 Hitachi Chemical Co Ltd チップ型電子部品及び接続構造体
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9293438B2 (en) * 2013-07-03 2016-03-22 Harris Corporation Method for making electronic device with cover layer with openings and related devices
CN108321142B (zh) * 2013-07-26 2020-08-28 日月光半导体制造股份有限公司 半导体封装件及其的制造方法
JP6324746B2 (ja) * 2014-02-03 2018-05-16 デクセリアルズ株式会社 接続体、接続体の製造方法、電子機器
CN104900543B (zh) * 2014-03-06 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
US9666814B2 (en) 2014-03-07 2017-05-30 Samsung Display Co., Ltd. Display device and method of manufacturing the same
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
US9698134B2 (en) * 2014-11-27 2017-07-04 Sct Technology, Ltd. Method for manufacturing a light emitted diode display
CN104966676B (zh) * 2015-07-08 2018-04-27 上海新微技术研发中心有限公司 共晶键合方法
TWI675440B (zh) * 2015-09-16 2019-10-21 楊秉榮 玻璃基板封裝及其製造方法
KR102393315B1 (ko) * 2015-09-30 2022-04-29 엘지디스플레이 주식회사 디스플레이 장치
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块
KR102539031B1 (ko) * 2016-04-28 2023-06-02 삼성디스플레이 주식회사 표시 장치
KR102654925B1 (ko) * 2016-06-21 2024-04-05 삼성디스플레이 주식회사 디스플레이 장치 및 이의 제조 방법
KR102666884B1 (ko) * 2016-07-15 2024-05-17 삼성디스플레이 주식회사 표시 장치 및 그의 제조 방법
CN106019663A (zh) * 2016-07-29 2016-10-12 京东方科技集团股份有限公司 集成电路器件及制作方法、电路板、显示面板、显示装置
KR102638304B1 (ko) * 2016-08-02 2024-02-20 삼성디스플레이 주식회사 표시장치
KR102615177B1 (ko) * 2016-10-06 2023-12-20 삼성디스플레이 주식회사 평판표시장치
WO2018159186A1 (ja) * 2017-02-28 2018-09-07 富士フイルム株式会社 半導体デバイス、積層体ならびに半導体デバイスの製造方法および積層体の製造方法
KR102341124B1 (ko) * 2017-09-26 2021-12-22 삼성디스플레이 주식회사 전자패널, 표시장치, 및 그 제조 방법
CN109659304A (zh) * 2017-10-12 2019-04-19 上海和辉光电有限公司 一种阵列基板、显示面板及显示装置
US10283471B1 (en) * 2017-11-06 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Micro-connection structure and manufacturing method thereof
CN109860224B (zh) * 2017-11-30 2021-05-14 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板、显示装置
KR102452462B1 (ko) 2017-12-26 2022-10-06 엘지디스플레이 주식회사 표시장치
KR102633137B1 (ko) 2018-01-23 2024-02-02 삼성전자주식회사 반도체 패키지
JP7160302B2 (ja) 2018-01-31 2022-10-25 三国電子有限会社 接続構造体および接続構造体の作製方法
JP7185252B2 (ja) 2018-01-31 2022-12-07 三国電子有限会社 接続構造体の作製方法
JP7046351B2 (ja) 2018-01-31 2022-04-04 三国電子有限会社 接続構造体の作製方法
KR102512724B1 (ko) * 2018-04-19 2023-03-23 삼성디스플레이 주식회사 표시장치 및 이의 제조방법
KR20200005096A (ko) * 2018-07-05 2020-01-15 엘지전자 주식회사 반도체 발광 소자를 이용한 디스플레이 장치 및 이의 제조방법
CN109188790B (zh) * 2018-09-13 2022-04-15 京东方科技集团股份有限公司 基板及其制作方法、显示装置
CN114097015A (zh) * 2019-07-12 2022-02-25 夏普株式会社 显示装置
KR20210043790A (ko) * 2019-10-11 2021-04-22 삼성디스플레이 주식회사 접착 부재, 이를 포함한 표시장치, 및 표시장치의 제조 방법
KR20210051535A (ko) 2019-10-30 2021-05-10 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20210065580A (ko) * 2019-11-27 2021-06-04 엘지디스플레이 주식회사 플렉서블 표시장치
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
US11991824B2 (en) * 2020-08-28 2024-05-21 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
CN1348481A (zh) * 1999-02-25 2002-05-08 日东电工株式会社 用于半导体封铸的树脂组合物、由所述材料获得的半导体设备以及制造半导体设备的方法
US6518665B1 (en) * 1997-07-11 2003-02-11 Delaware Capital Formation, Inc. Enhanced underfill adhesion
US6744142B2 (en) * 2002-06-19 2004-06-01 National Central University Flip chip interconnection structure and process of making the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH095769A (ja) * 1995-06-21 1997-01-10 Rohm Co Ltd 電子素子の配線接続構造
JPH10144727A (ja) * 1996-11-14 1998-05-29 Matsushita Electric Ind Co Ltd 半導体素子の実装方法および半導体素子を実装した電子装置
US5903056A (en) * 1997-04-21 1999-05-11 Lucent Technologies Inc. Conductive polymer film bonding technique
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
US6451875B1 (en) * 1999-10-12 2002-09-17 Sony Chemicals Corporation Connecting material for anisotropically electroconductive connection
JP2001267370A (ja) * 2000-03-14 2001-09-28 Hitachi Ltd 半導体実装装置および方法
US6677664B2 (en) * 2000-04-25 2004-01-13 Fujitsu Hitachi Plasma Display Limited Display driver integrated circuit and flexible wiring board using a flat panel display metal chassis
JP2001358171A (ja) * 2000-06-12 2001-12-26 Canon Inc 半導体素子実装構造
US6489573B2 (en) * 2000-06-16 2002-12-03 Acer Display Technology Electrode bonding structure for reducing the thermal expansion of the flexible printed circuit board during the bonding process
TW479304B (en) * 2001-02-06 2002-03-11 Acer Display Tech Inc Semiconductor apparatus and its manufacturing method, and liquid crystal display using semiconductor apparatus
KR100456064B1 (ko) 2001-07-06 2004-11-08 한국과학기술원 극미세 피치 ｃｏｇ 기술용 이방성 전도성 필름
JP3810064B2 (ja) * 2002-03-15 2006-08-16 松下電器産業株式会社 液晶表示装置
JP2003332384A (ja) * 2002-05-13 2003-11-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
WO2004051732A1 (en) * 2002-11-29 2004-06-17 Infineon Technologies Ag Attachment of flip-chips to substrates
JP4115832B2 (ja) * 2002-12-27 2008-07-09 東芝松下ディスプレイテクノロジー株式会社 半導体素子及び液晶表示パネル
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP2005109023A (ja) * 2003-09-29 2005-04-21 Optrex Corp 半導体チップ及びそれを実装した液晶表示装置
JP2005109187A (ja) * 2003-09-30 2005-04-21 Tdk Corp フリップチップ実装回路基板およびその製造方法ならびに集積回路装置
US20050104225A1 (en) * 2003-11-19 2005-05-19 Yuan-Chang Huang Conductive bumps with insulating sidewalls and method for fabricating
TWI262347B (en) * 2004-08-02 2006-09-21 Hannstar Display Corp Electrical conducting structure and liquid crystal display device comprising the same
JP2007335607A (ja) * 2006-06-14 2007-12-27 Sharp Corp Ｉｃチップ実装パッケージ、及びこれを用いた画像表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518665B1 (en) * 1997-07-11 2003-02-11 Delaware Capital Formation, Inc. Enhanced underfill adhesion
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
CN1348481A (zh) * 1999-02-25 2002-05-08 日东电工株式会社 用于半导体封铸的树脂组合物、由所述材料获得的半导体设备以及制造半导体设备的方法
US6744142B2 (en) * 2002-06-19 2004-06-01 National Central University Flip chip interconnection structure and process of making the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
同上.

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