CN1913175A - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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CN1913175A
CN1913175A CNA2006100941975A CN200610094197A CN1913175A CN 1913175 A CN1913175 A CN 1913175A CN A2006100941975 A CNA2006100941975 A CN A2006100941975A CN 200610094197 A CN200610094197 A CN 200610094197A CN 1913175 A CN1913175 A CN 1913175A
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substrate
silicon alloy
sidewall
grid
silicon
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王志豪
王大维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件及其形成方法，可减少栅极间隔物下的凹陷。上述的半导体元件包括一栅极结构于基板上、一侧壁间隔物于栅极结构的侧壁、一小于30埃的凹陷区域于侧壁间隔物下、以及至少部分位于基板中且邻接凹陷区域的硅合金区域。硅合金区域的厚度实质上大于30纳米。在移除栅极结构上的硬掩模时保护基板，可减少凹陷区域的深度。上述的半导体元件较佳为p型金属氧化物半导体元件。上述半导体形成方法可减少金属氧化物半导体元件的接面深度，可改善短沟道效应并增加元件驱动电流。

Description

半导体元件及其形成方法
技术领域
本发明涉及金属氧化物半导体元件，更特别地，涉及一种具有高应变沟道区的金属氧化物半导体元件及其形成方法。
背景技术
超大规模集成电路(VLSI)的尺寸持续缩小，当电路越小及越快时，如何改善元件的驱动电流就越来越重要。金属氧化物半导体晶体管的电流受栅极长度、栅极电容、以及沟道区的载流子迁移率影响。栅极长度持续随着电路尺寸不断缩小，而增加栅极电容的方法包括减少栅极介电层的厚度、选择较高介电常数的材料作为栅极介电层、或其它类似的方法。为了改善元件的电流，增加载流子迁移率则是另一个发展中的方向。
应变沟道区可增加载流子迁移率。应变(strain)，有时亦称为应力(stress)，可增加电子及空穴的迁移率。金属氧化物半导体元件的性能可通过应变表面的沟道提升，在栅极长度固定的情况下，不需额外的过程或设计。先前研究显示，拉伸应力有助于nMOS的性能，而压缩应力有助于pMOS的性能。
如图1所示，为具有压缩应变的沟道区的pMOS元件，其栅极堆叠结构位于硅基板1上，包括栅极介电层4及其上的栅极电极6。栅极堆叠结构下为沟道区8，两侧为硅基板1中的SiGe区2。一般SiGe区2的形成方法是在硅基板1形成凹陷后，外延生长SiGe(含适当杂质)于凹陷中。由于SiGe的晶格常数大于硅，SiGe区2将对沟道区8造成压缩应力并形成压缩应变的沟道区8。
图2及图3显示如何形成图1的栅极堆叠结构。于基板1上依序形成栅极介电层、栅极电极层、及硬掩模层。接着图案化上述的堆叠结构以形成栅极介电层4、栅极电极6、及硬掩模10。在形成具有SiGe区的pMOS元件时，硬掩模10的使用相当广泛。上述的图案化过程将使硅基板1产生凹陷12。如图3所示，形成SiGe区2并移除硬掩模10。硬掩模10一般为氮化硅，移除的方法较佳为磷酸，但磷酸将侵蚀硅基板1并形成凹陷12。公知技艺中，若在外延生长SiGe区2后以磷酸移除硬掩模10，凹陷12的深度Dp将大于30，很难比30浅。
当上述掺杂的SiGe区形成于pMOS时，于接续的热处理中更易扩散。扩散的杂质将增加接面深度与抵消口袋区(pocket region)，这将减少接面的陡峭度(abruptness)，对短沟道效应产生不良影响。当侧壁间隔物底部的凹陷越深时，接面深度跟着越深并影响pMOS元件的性能。
综上所述，现在极需一种金属氧化物半导体元件的形成方法，特别是pMOS元件，以减少靠近栅极结构的基板的凹陷深度。
发明内容
本发明的较佳实施例提供了一种金属氧化物半导体元件及其形成方法，其减少侧壁间隔物下的凹陷深度。
本发明提供一种半导体元件，包括基板；栅极结构，位于该基板上；侧壁间隔物，位于栅极结构的侧壁；凹陷区域，位于基板中且深度实质上小于30，其中至少有部分凹陷区域位于侧壁间隔物下；硅合金区域，至少有部分硅合金区域位于基板中且邻接凹陷区域，其中硅合金区域的晶格常数实质上大于基板的晶格常数，且该硅合金的厚度实质上大于30nm。仔细控制形成栅极的蚀刻液种类及过程，可将凹陷的深度控制在10以内。
如上所述的半导体元件，其中该栅极结构包括一栅极介电层位于该基板上以及一栅极电极位于该栅极介电层上，且该半导体元件还包括：一轻掺杂源极/漏极区域，其实质上对准该栅极结构的边缘；一栅极间隔物，位于该栅极结构的侧壁；以及一源极/漏极区域，位于该基板中并包括至少一部分的该硅合金区域。
如上所述的半导体元件，其中该栅极间隔物覆盖部分的硅合金区域。
如上所述的半导体元件，其中该栅极介电层的介电常数大于约3.9。
如上所述的半导体元件，其中该硅合金区域包括p型杂质。
如上所述的半导体元件，其中该硅合金区域包括SiGe。
如上所述的半导体元件，其中该硅合金区域的一部分高于该基板的上表面。
本发明还提供一种半导体结构，包括：基板；第一晶体管的第一栅极结构，位于基板上，且第一晶体管是第一导电型；第一栅极间隔物，位于第一栅极结构的侧壁；第一凹陷区域，位于基板中且具有第一凹陷深度，且位于第一栅极间隔物下的第一凹陷深度实质上小于30；第一源极/漏极区域，位于基板中，且第一源极/漏极区域包括硅合金区域，硅合金区域的晶格常数实质上大于基板的晶格常数；第二晶体管的第二栅极结构，位于基板上，第二晶体管是与第一导电型相反的第二导电型；第二栅极间隔物，位于第二栅极结构的侧壁；以及第二凹陷区域，位于基板中且具有第二凹陷深度，且位于第二栅极间隔物下的第二凹陷深度实质上小于30。
本发明提供一种半导体结构的形成方法，包括：提供硅基板；形成栅极结构于硅基板上；形成硬掩模于该栅极结构上，硬掩模包括氮化硅；形成第一侧壁间隔物于栅极结构的侧壁；形成第二侧壁间隔物于第一侧壁间隔物的侧壁；形成第一凹陷区域于硅基板中，且第一凹陷区域延着第二侧壁间隔物的侧壁；外延生长硅合金区域于第一凹陷区域；移除硬掩模、第一侧壁间隔物、以及第二侧壁间隔物，其中位于第一侧壁间隔物下的硅基板具有第二凹陷区域，且第二凹陷区域的深度实质上小于30。
如上所述的半导体结构的形成方法，其中该第一侧壁间隔物包括氮化物或氧化物；该第二侧壁间隔物包括氮化物或氧化物。
上述缩减凹陷的方法可减少金属氧化物半导体元件的接面深度，可改善短沟道效应并增加元件驱动电流。
附图说明
图1是一般具有SiGe区的pMOS元件剖面图，其中SiGe区用以使沟道区产生压缩应变；
图2与图3是图1所示的pMOS元件的制作过程剖面图；
图4至图16是本发明实施例中，形成半导体结构的过程剖面图；图17是不同的凹陷深度对pMOS元件性能的曲线图。
其中，附图标记说明如下：
1：硅基板    2：SiGe区   4：栅极介电层
6：栅极电极    8：沟道区    10：硬掩模
12：凹陷    Ds：SiGe区的深度  Dp：凹陷的深度
40：基板    42：浅沟槽绝缘区    100：pMOS区
200：nMOS区    104、204：栅极介电层    106、206：栅极电极
108、208：硬掩模    110：第一侧壁间隔物层的下层
112：第一侧壁间隔物层的上层    114、214：第一侧壁间隔物
1141、2141：内衬氧化层  1142、2142：氮化物层
111：掺杂区               209、212：光阻层
116：第二侧壁间隔物层的下层
118：第二侧壁间隔物层的下层
1201：第二侧壁间隔物的内侧部分
1202：第二侧壁间隔物的外侧部分
124：硅合金区域
1241：硅合金区域于基板中的部分
1242：硅合金区域的***部分
H：硅合金区域的***部分的高度
D：硅合金区域于基板中的深度
D1、D2：凹陷区域   130、230：轻掺杂源极/漏极
132、232：侧壁间隔物   234：源极/漏极区
136、138、236、238：金属硅化区域
具体实施方式
如图4所示，于基板40上形成二个栅极堆叠结构，分别位于pMOS区100与nMOS区200，并以一浅沟槽绝缘区(以下简称STI)42隔开。pMOS区100的栅极堆叠结构具有栅极介电层104以及栅极电极106。nMOS区200的栅极结构具有栅极介电层204以及栅极电极206。
基板40可为基体硅，或其它常见的结构如绝缘层上硅(SOI)。pMOS区100较佳为n型阱区，nMOS区200较佳为p型阱区。栅极介电层104、204较佳为高介电常数的材料，其介电常数大于3.9，如Ta、La、Hf、Al、HfOx、HfSiOx、HfSiOxNy、AlOx、LaOx、HfAlOx、ZrO2、Al2O3、TiO2、Ta2O5、La2O3、CeO2、Bi4Si2O12、WO3、Y2O3、LaAlO3、Ba1-xSrxTiO3、PbTiO3、BaTiO3、SrTiO3、PbZrO3、PST、PZN、PZT、PMN、或上述的组合。栅极106、206较佳为金属氮化物如TiN或TaN，亦可为金属如Mo或Ti，或者是金属硅化物如MoSix、TaSixNy或其它类似的金属硅化物。上述的栅极堆叠结构分别具有硬掩模108、208，较佳为氮化硅。在其它的实施例中，硬掩模可为氮氧化硅，氧化硅，或其它类似的材质。
如图5所示，将第一侧壁间隔物层形成于上述结构上。较佳实施例中，第一侧壁间隔物层分为下层110及上层112，两者较佳具有不同的蚀刻选择性。下层110较佳为氧化物，因此可称之为内衬氧化层110。上层112较佳为氮化硅，因此可称之为氮化物层112。在其它实施例中，第一侧壁间隔物层可为单层或多层结构，材质可为氧化层、氮化硅层、氮氧化硅层、且/或其它的介电材料。形成第一侧壁间隔物层的方法可为一般常见的技术，如等离子体增强式化学气相沉积(PECVD)、低压化学气相沉积法(LPCVD)、次大气压化学气相沉积技术(sub-atmosphere CVD，简称SACVD)、或其它合适的方法。
如图6所示，图案化内衬氧化层110及氮化物层112，以形成pMOS区100的第一侧壁间隔物114，及nMOS区200的第一侧壁间隔物124。如同第一侧壁间隔物114具有内衬氧化部分1141及氮化物部分1142，第一侧壁间隔物124亦具有1241及1242。第一侧壁间隔物114及124的厚度T1及T2较佳大于100，更佳介于120-300之间。
如图7所示，形成光阻层209用以屏蔽nMOS区200。pMOS区域随后进行一注入过程以形成掺杂区111，较佳为p型掺杂如硼或BF2。掺杂区111将弥补栅极电极106及随后形成的硅合金区域之间的能差。
如图8所示，移除光阻层209后，将第二侧壁间隔物层形成于上述结构。第二侧壁间隔物一样具有上层118及下层116，较佳具有不同的蚀刻选择性。下层116较佳与内衬氧化层110材料相同，上层118较佳与氮化物层112材料相同。除此之外，上层118较佳与硬掩模108、208的材料相同。
如图9所示，形成光阻层212用以屏蔽nMOS区200。随后图案化pMOS区100的第二侧壁间隔物层，以形成第二侧壁间隔物120，其具有的内侧部分1201及其外侧部分1202。
之后于pMOS区100形成硅合金区域124，较佳的硅合金区域124的晶格常数实质上大于基板40的晶格常数。较佳的形成方法为等向蚀刻基板40以形成凹陷，再外延生长硅合金于上述凹陷中。
硅合金区域124较佳延伸至第二侧壁间隔物120下，更佳延伸至第一侧壁间隔物114与第二侧壁间隔物120的交界处下。为了增加对沟道区的压缩应力，硅合金区域124较佳超出基板40的上表面，如图9所示的***部分1242。***部分1242的高度H较佳低于栅极电极106，更佳介于100-700。然而，硅合金区域124的上表面亦可与基板40的上表面等高，或低于基板40的上表面。硅合金区域124于基板中的1241部分，其深度D较佳大于300，更佳大于350，甚至介于400-900。
较佳实施例中，基板40为硅，硅合金区域124为SiGe。Ge的原子半径大于Si原子，因此SiGe的晶格常数大于硅基板的晶格常数。可藉由调整Ge原子的比例改变SiGe的晶格常数，进而改变沟道区的压缩应变大小。在其它实施例中，硅合金区域除了Si与Ge外，亦可包含其它元素如碳。
如图10所示，移除光阻层212后，接着以适当蚀刻剂蚀刻硬掩模108，但保留pMOS区100的第二侧壁间隔物的内侧部分1201，及nMOS区200的第二侧壁间隔物层的下层116。pMOS区100的第二侧壁间隔物外侧部分1202，及nMOS区200的第二侧壁间隔物的上层118亦被蚀刻移除，且较佳同时被移除。在较佳实施例中，由于硬掩模108、第二侧壁间隔物的外侧部分1202、以及第二侧壁间隔物的上层118较佳为氮化硅，因此可利用磷酸移除。值得注意的是，基板40被第二侧壁间隔物的内侧部分1201，及第二侧壁间隔物层的下层116所保护。
如图11所示，以不会伤害内衬氧化部分1142及2142的蚀刻液，移除第二侧壁间隔物的内侧部分1201，及第二侧壁间隔物层的下层116。较佳实施例中，由于1201及116由氧化物形成，因此可用氢氟酸移除。
如图12所示，移除硬掩模208、内衬氧化部分1142及2142，此步骤较佳使用与移除第二侧壁间隔物的外侧部分1202相同的蚀刻液。由于pMOS区100的基板40已被氮化物部分1141保护，且硅合金区域124同样不受蚀刻液(磷酸)影响，因此几乎不会产生凹陷。在nMOS区200中，氮化物部分2141保护不到的地方将产生凹陷，但nMOS区200的凹陷几乎不影响nMOS元件的性能。此外，硅合金区域124的凹陷也同样不影响元件的性能。
如图13所示，接着移除氮化物部分1141及1241，较佳使用氢氟酸。氢氟酸对硅基板的蚀刻速率非常低。此外，在邻接栅极电极106、206的区域，只有过蚀刻会影响基板40。因此即使有凹陷，其深度也远较公知结构的凹陷小。举例来说，凹陷区域128及228的深度D1、D2均小于30，在小心的控制蚀刻过程并慎选蚀刻液的情况下，D1、D2可轻易的小于10。
在pMOS元件中，邻接栅极电极106，特别是介于沟道区与硅合金区域之间的凹陷越浅，越能降低接面深度并改善短沟道效应，进而改善pMOS元件的性能。
如图14所示，以p型掺杂与n型掺杂分别形成轻掺杂源极/漏极(lightly doped drain，以下简称LDD)130及LDD230于pMOS区100及nMOS区200。LDD130实质上对准栅极电极206的边缘。当进行LDD230掺杂时可利用光阻(未图示)保护pMOS区100。同样的，当进行LDD130掺杂时亦可利用光阻(未图示)保护nMOS区200。必需注意的是，掺杂区111连接LDD130及硅合金区域124。
如图15所示，形成侧壁间隔物132、232、及nMOS区200的源极/漏极234。形成侧壁间隔物132、232的方法较佳为前述形成第一侧壁间隔物及第二侧壁间隔物的方法。形成源极/漏极于nMOS区200的方法为本技术领域的常见手段，在此不赘述。值得注意的是，pMOS的源极/漏极区，亦即掺杂区111及掺杂的硅合金区域124在前面的步骤中已形成。
如图16所述，进行一金属硅化过程以形成金属硅化区136、138、236、及238。如本技术领域所熟知，此步骤为先毯覆性地沉积适当的金属层如Ti、Co、Ni、Pd、Pt、Er、或类似的金属。接着进行退火工艺使金属层与其下的硅反应。接着移除未反应的金属，较佳的方法为选择性蚀刻工艺。值得注意的是，金属硅化区136实质上高于金属硅化区236。
本发明的较佳实施例可显著改善pMOS元件的驱动电流。如图17所示的模拟结果，不同的pMOS元件各自具有以下的凹陷深度：无凹陷、25凹陷、50凹陷、以及100凹陷。图17显示上述不同元件的漏电流Ioff与驱动电流Ion之间的关系。举例来说，同样漏电流100nA/μm，具有25凹陷的pMOS元件142的驱动电流较无凹陷的pMOS元件140的驱动电流衰退3.3％。相同比较下，具有50凹陷的pMOS元件144的驱动电流与具有100凹陷的pMOS元件146的驱动电流则各自衰退5.5％与9.5％。
本发明的较佳实施例与现有的金属氧化物半导体元件过程可完全兼容。
虽然本发明已以多个较佳实施例揭示如上，然其并非用以限定本发明，对本领域的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视后附的权利要求书所界定的范围为准。

Claims (10)

1.一种半导体元件，包括：
一基板；
一栅极结构，位于该基板上；
一侧壁间隔物，位于该栅极结构的侧壁；
一凹陷区域，位于该基板中且深度实质上小于30，其中至少有部分该凹陷区域位于该侧壁间隔物下；
一硅合金区域，至少有部分该硅合金区域位于该基板中且邻接该凹陷区域，其中该硅合金区域的晶格常数实质上大于该基板的晶格常数，且该硅合金的厚度实质上大于30nm。
2.如权利要求1所述的半导体元件，其中该栅极结构包括一栅极介电层位于该基板上以及一栅极电极位于该栅极介电层上，且该半导体元件还包括：
一轻掺杂源极/漏极区域，其实质上对准该栅极结构的边缘；
一栅极间隔物，位于该栅极结构的侧壁；以及
一源极/漏极区域，位于该基板中并包括至少一部分的该硅合金区域。
3.如权利要求2所述的半导体元件，其中该栅极间隔物覆盖部分的硅合金区域。
4.如权利要求2所述的半导体元件，其中该栅极介电层的介电常数大于约3.9。
5.如权利要求1所述的半导体元件，其中该硅合金区域包括p型杂质。
6.如权利要求1所述的半导体元件，其中该硅合金区域包括SiGe。
7.如权利要求1所述的半导体元件，其中该硅合金区域的一部分高于该基板的上表面。
8.一种半导体结构，包括：
一基板；
一第一晶体管的第一栅极结构，位于该基板上，且该第一晶体管是第一导电型；
一第一栅极间隔物，位于该第一栅极结构的侧壁；
一第一凹陷区域，位于该基板中且具有一第一凹陷深度，且位于该第一栅极间隔物下的该第一凹陷深度实质上小于30；
一第一源极/漏极区域，位于该基板中，且该第一源极/漏极区域包括一硅合金区域，该硅合金区域的晶格常数实质上大于该基板的晶格常数；
一第二晶体管的第二栅极结构，位于该基板上，该第二晶体管是与第一导电型相反的第二导电型；
一第二栅极间隔物，位于该第二栅极结构的侧壁；以及
一第二凹陷区域，位于该基板中且具有一第二凹陷深度，且位于该第二栅极间隔物下的该第二凹陷深度实质上小于30。
9.一种半导体结构的形成方法，包括：
提供一硅基板；
形成一栅极结构于该硅基板上；
形成一硬掩模于该栅极结构上，该硬掩模包括氮化硅；
形成一第一侧壁间隔物于该栅极结构的侧壁；
形成一第二侧壁间隔物于该第一侧壁间隔物的侧壁；
形成一第一凹陷区域于该硅基板中，且该第一凹陷区域延着第二侧壁间隔物的侧壁；
外延生长一硅合金区域于该第一凹陷区域；
移除该硬掩模、该第一侧壁间隔物、以及该第二侧壁间隔物，其中位于该第一侧壁间隔物下的该硅基板具有一第二凹陷区域，且该第二凹陷区域的深度实质上小于30。
10.如权利要求9所述的半导体结构的形成方法，其中该第一侧壁间隔物包括氮化物或氧化物；该第二侧壁间隔物包括氮化物或氧化物。
CNA2006100941975A 2005-08-10 2006-06-27 半导体元件及其形成方法 Pending CN1913175A (zh)

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