CN1912860A

CN1912860A - Apparatus and methods for low-power routing in programmable logic devices

Info

Publication number: CN1912860A
Application number: CN 200610103056
Authority: CN
Inventors: V·桑托卡; R·西汝维德户拉
Original assignee: Altera Corp
Current assignee: Altera Corp
Priority date: 2005-07-11
Filing date: 2006-07-11
Publication date: 2007-02-14

Abstract

An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to derive from the input signal a limited swing driver output signal. The receiver circuit is configured to derive from the limited swing driver output signal a limited swing receiver output signal.

Description

Low-power route device and method in the programmable logic device (PLD)

The cross reference of related application

[0001] the application requires rights and interests (agency recognizes reel number ALTR:048PZ1) that on July 11st, 2005 submitted to, that name is called " Apparatus andMethods for Low-Power Routing in Programmable Logic Devices " U.S. Provisional Patent Application sequence number 60/698,225.

Technical field

[0002] principle of the present invention relates generally to routing circuit (routing circuitry) and the correlation technique in the programmable logic device (PLD) (PLD).More specifically, the present invention relates to have the routing circuit and the correlation technique of relatively low energy consumption.

Background technology

[0003] complicacy of modern PLD increases, and can continue to increase.Typical PLD comprises tens million of transistors.On the one hand, the complicacy of the increase of PLD has caused the raising of performance class and the enhancing of dirigibility.On the other hand, the complicacy of PLD and above-mentioned a large amount of transistor have also caused the energy consumption of this device to increase.

[0004] along with device size reduces to 0.1 micron, energy consumption has become a more crucial problem.Along with the increase of PLD complicacy, this trend continues possibly.The energy consumption that increases in PLD can cause the power density level to improve, and this can influence reliability and the practical application of PLD conversely again.Therefore, there is the demand that reduces the PLD energy consumption.

Summary of the invention

[0005] disclosed new principle relates to the apparatus and method that are used for interconnection circuit.People can use these interconnection circuits in PLD, for example so that be coupled to another resource (as Programmable Logic Device etc.) among the PLD

[0006] in one embodiment, an interconnection circuit comprises a drive circuit and an acceptor circuit.Described acceptor circuit is coupled in described drive circuit.Described drive circuit is configured to receive an input signal, and obtains a finite amplitude driver output signal from described input signal.Described acceptor circuit is configured to obtain a finite amplitude receiver output signal from described finite amplitude driver output signal.

[0007] in another embodiment, interconnection circuit resource among the PLD that has been coupled.Described interconnection circuit comprises a drive circuit.Described drive circuit has the transistor that at least one threshold voltage is higher than nominal threshold voltage among the PLD.

[0008] in another embodiment, a kind of in PLD the method for interconnection circuit, it is included in the circuit receiving inputted signal from signal source, produces the finite amplitude output signal, and described output signal is supplied with another circuit (receiving circuit).Described receiving circuit further produces a finite amplitude output signal.

Description of drawings

[0009] accompanying drawing has only illustrated exemplary embodiment of the present invention, therefore should not be considered to or be interpreted as limitation of the scope of the invention.Those those of ordinary skills that benefit from instructions of the present invention it will be appreciated that disclosed inventive principle can be used for other equivalent embodiment equally.In the accompanying drawings, used identical Digital ID is represented identical, similarly or the function, parts or the module that are equal in more than one accompanying drawing.

[0010] Fig. 1 shows the overall block-diagram of the PLD of an illustrative embodiment according to the present invention.

[0011] Fig. 2 has illustrated the plane figure of PLD according to an illustrative embodiment of the invention.

[0012] Fig. 3 has described a kind of circuit arrangement, and it has illustrated the routing function of an interconnection (interconnect).

[0013] Fig. 4 has described a kind of circuit arrangement that is used to analyze the interconnection circuit first order modeling.

[0014] Fig. 5 has illustrated the curve map as the power consumption (P) of voltage (V) function.

[0015] Fig. 6 has described the circuit arrangement according to an illustrative embodiment of interconnection of the present invention.

[0016] Fig. 7 has described the circuit arrangement according to another illustrative embodiment of interconnection of the present invention.

[0017] Fig. 8 and Fig. 1 O-13 have illustrated the circuit arrangement according to each exemplary embodiment of interconnection of the present invention.

[0018] curve map of used signal during Fig. 9 has described and powered up in exemplary embodiment of the present.

Embodiment

[0019] principle of the invention has provided device and the correlation technique that reduces energy consumption in the PLD.Fig. 1 shows the The general frame of the PLD 103 of the illustrative embodiment according to the present invention.PLD 103 comprises configuration circuit 130, config memory (CRAM) 133, control circuit 136, FPGA (Field Programmable Gate Array) 106, programmable interconnect 109 and I/O circuit 112.In addition, as required, PLD 103 can comprise test/debug circuit 115, one or more processor 118, one or more telecommunication circuit 121, one or more storer 124, one or more controller 127.

[0020] FPGA (Field Programmable Gate Array) 106 comprises the configurable or Programmable Logic Device of polylith, for example look-up table (LUT), product term logic, multiplexer (MUX), logic gate, register, storer, or the like.As required, FPGA (Field Programmable Gate Array) 106 and other module and the which couple in programmable interconnect 109 and the PLD 103.As will be described in further detail below, programmable interconnect 109 in FPGA (Field Programmable Gate Array) 106 various modules and PLD 103 in or provide configurable interconnection (coupling mechanism) between outer other circuit.

[0021] the various operations in the control circuit 136 control PLD 103.Under the monitoring of control circuit 136, PLD configuration circuit 130 utilizes configuration data to programme or disposes the function (configuration data is from external source, for example obtains in memory device, the main frame etc.) of PLD 103.Configuration data is used to store the information among the CRAM 133 usually.The content of CRAM 133 has been determined the function of PLD 103 each modules, for example FPGA (Field Programmable Gate Array) 106 and programmable interconnect 109.

[0022] the I/O circuit 112 that it will be understood by those skilled in the art that of benefiting from instructions of the present invention can comprise various I/O equipment or circuit.I/O circuit 112 can be coupled with the various piece of PLD 103, for example FPGA (Field Programmable Gate Array) 106 and programmable interconnect 109.I/O circuit 112 provides a kind of mechanism and circuit for each modules in the PLD 103, with external circuit or devices communicating.

[0023] test/debug circuit 115 helps to test and checks each module and circuit in the PLD 103.Test/debug circuit 115 can comprise multiple module or the circuit that those those of ordinary skills that benefit from instructions of the present invention are known.For example, as required, test/debug circuit 115 can be included in PLD 103 power up or reset after be used to carry out the circuit of test.As required, test/debug circuit 115 also can comprise coding and parity checker.

[0024] PLD 103 can comprise one or more processors 118.Processor 118 can be coupled in other module and the circuit in the PLD 103.As benefit from instructions of the present invention those skilled in the art recognized, processor 118 can receive data and information from PLD 103 inside or circuit external, and come process information in various modes.One or more processors 118 can constitute a digital signal processor (DSP).As required, DSP can realize various signal processing tasks, for example compresses, decompression, Audio Processing, Video processing, Filtering Processing or the like.Benefit from the understood by one of ordinary skill in the art of instructions of the present invention as those, as required, people can utilize the logical resource of PLD 103 to realize the function of DSP, and do not use special-purpose DSP.

[0025] PLD 103 also can comprise one or more telecommunication circuits 121.Telecommunication circuit 121 can help to carry out data and message exchange between the various circuit of PLD 103 inside and PLD 103 circuit external, as benefits from the understood by one of ordinary skill in the art of instructions of the present invention.

[0026] PLD 103 can further comprise one or more storeies 124 and one or more controller 127.Storer 124 allows various data and the information (for example user data, intermediate result, result of calculation etc.) in the storage PLD 103.What as required, storer 124 can be for particle type or piece formula.Controller 127 allows and PLD external circuit interface, and its operation and various function are controlled.For example, as required, controller 127 can constitute a memory controller, itself and outside Synchronous Dynamic Random Access Memory (SDRAM) interface, and Synchronous Dynamic Random Access Memory controlled.

Notice that [0027] Fig. 1 shows the simplified block diagram of PLD 103.Therefore, PLD 103 can comprise other module and circuit, as one of ordinary skill in understanding.The example of sort circuit comprise clock generating and distributor circuit, redundant circuit, or the like.And as required, PLD 103 can comprise mimic channel, other digital circuit and/or hybrid circuit.

[0028] Fig. 2 shows the plane figure of PLD 103 according to an illustrative embodiment of the invention.PLD 103 comprises the FPGA (Field Programmable Gate Array) 106 that is arranged as two-dimensional array.The programmable interconnect 109 that is arranged as horizontal interconnect and perpendicular interconnection is coupled each module of FPGA (Field Programmable Gate Array) 106 mutually.In illustrative embodiment, can have hierarchical structure according to PLD of the present invention.That is to say that each module of FPGA (Field Programmable Gate Array) 106 can comprise littler or more granular programmed logical module or circuit successively.

[0029] programmable interconnect 109 provides a kind of mechanism or the mechanism of intercommunication mutually for the various modules of PLD 103 (see figure 1)s.Generally speaking, the configuration data of PLD 103 (or programming data) has been determined the function that realized by its resource (comprising FPGA (Field Programmable Gate Array) 106 and programmable interconnect 109).Utilize the configurable circuit module, for example multiplexer, transmission gate and transmission transistor (pass transistor), programmable interconnect 109 can the various circuit in PLD 103 in route signal.

[0030] Fig. 3 shows a circuit arrangement 200, and it has illustrated the routing function of an interconnection 109.Interconnection 109 comprises a drive circuit 203, and the acceptor circuit 205 by coupling mechanism 109A communication.As benefiting from it is understood by one of ordinary skill in the art that as required of instructions of the present invention, coupling mechanism 109A can adopt various forms.Many factors are depended in the selection of embodiment, for example Qi Wang application, design and specification etc.For example, coupling mechanism can comprise conductor, lead or the conductive traces on PLD 103, interconnection etc. as required.

[0031] in drive circuit 203 and the acceptor circuit 205 each can be respectively with the PLD103 (see figure 1) in a source module communicate by letter for example FPGA (Field Programmable Gate Array) 106, processor 118, storer 124 etc. with object module.That is to say that drive circuit 203 receives the signal from certain source among the PLD103, and be sent to acceptor circuit 205 by coupling mechanism 109A signal (one or more).Acceptor circuit 205 offers a target the PLD 103 with the described signal that receives from coupling mechanism 109A.

[0032], 109 often comprises a large amount of electronic packages so interconnect, for example mos field effect transistor (MOSFET) because interconnection 109 spreads all over PLD 103 (no matter being in a section or at littler interconnection section).These transistorized operations can cause relatively large power consumption in the PLD 103.More specifically, these transistorized operations can cause quiescent dissipation (normally owing to leak cause) and dynamic power consumption (normally causing owing to transistorized switch), as benefit from instructions of the present invention those of ordinary skills understood.

[0033] Fig. 4 shows a circuit arrangement 208, and it helps to analyze the first order modeling of interconnection 109.Circuit arrangement 208 109A that will interconnect is modeled as a resistor-capacitor circuit network that comprises resistor 210 and capacitor 213.Resistor 210 can comprise the output impedance of drive circuit 203 and the impedance of coupling mechanism 109A.Capacitor 213 can comprise the input capacitance of electric capacity and the acceptor circuit 205 of coupling mechanism 109A.

[0034] supposition resistor 210 have a negligible value (that is, and the relative stronger buffer area in the drive circuit 203, the 109A of low-impedance coupling mechanism, or the like), people just can carry out modeling to the power consumption of drive circuit 203.If the frequency via the signaling switch of coupling mechanism 109A communication is f, then the value of power consumption P is:

P＝CV ²f

Wherein, C and V represent the electric capacity of capacitor 213 and the output voltage of drive circuit 203 respectively.Notice that above-mentioned equation supposition has complementary circuit (being that voltage is swung) at the output of drive circuit 203 between earth potential and V.Acceptor circuit 205 has the circuit that is similar to driving circuit 203 usually, therefore owing to power consumption takes place switching signal.

Notice that [0035] shown in above-mentioned equation, the switch power consumption increases along with the increase of C, V and/or f.The physical property of coupling mechanism 109A (it is often determined by the layout of PLD 103, to finish signal communication and distribution) has been determined the value (deviser attempts minimizing C as much as possible) of capacitor C.Similarly, the value of frequency f depends on that PLD user wants the function that realizes.

[0036] still, people can influence the power consumption of interconnection 109 by the value that reduces V.Notice that power P is along with square increase of voltage V, shown in the curve 250 of energy consumption among Fig. 5 (P)-voltage (V).Therefore, reduce V and power consumption is had more significant effect than same C of reduction or f.

[0037] in traditional interconnection, described signal is at earth potential and supply voltage (V _DD) between the swing.As will be described in further detail below, principle of the present invention partly be to provide with voltage amplitude be reduced on the earth potential, supply voltage (V _DD) under device and correlation technique.In other words, the present invention low-voltage V of applied voltage amplitude that interconnects _LWith high voltage V _HBe respectively:

V _L=V _GND+ Δ ₁With

V _H＝V _DD-Δ2

Wherein, Δ ₁And Δ ₂The value of expression depends on used particular electrical circuit topological structure and design.

[0038] Fig. 6 shows a circuit arrangement 255, and it has described an illustrative embodiment according to a kind of interconnection 109 of the present invention.Drive circuit 203 in circuit arrangement 255 comprises two-stage, predriver circuit or a regulating circuit 260A (first order) and a level converter circuit 263A (second level).Predriver circuit 260A drive level converter circuit 263.Level converter circuit 263A and coupling mechanism 109A coupling, and the signal that will obtain from one or more input signals is supplied with coupling mechanism 109A.The signal of supplying with coupling mechanism 109A has the voltage amplitude of a minimizing.

[0039] coupling mechanism 109A will offer acceptor circuit 205 from the signal that drive circuit 203 receives.Acceptor circuit 205 comprises a predriver circuit or the regulating circuit 260B first order as it.As required, predriver circuit 260B can have and similar circuit arrangement of predriver circuit 260A and topological structure.The signal that predriver circuit 260B receives from coupling mechanism 109A according to it obtains one or more signals.Predriver circuit 260B offers level converter circuit 263B with these signals (one or more).Level converter circuit 263B provides the output signal of a low-amplitude signal as interconnection 109.As required, level converter circuit 263B can have and similar circuit arrangement of level converter circuit 263A and topological structure.

[0040] Fig. 7 shows a circuit arrangement 265, and it has described another illustrative embodiment according to a kind of interconnection 109 of the present invention.Different with the circuit arrangement among Fig. 6 is that circuit arrangement 265 provides standard amplitude or conventional amplitude logical signal (for example, to have rail-to-rail or V _DDSignal to ground connection, voltage amplitude) as its output.

[0041] more specifically, the drive circuit 203 in circuit arrangement 255 comprises two-stage, predriver circuit or a regulating circuit 260A (first order) and a level converter circuit 263A (second level).Predriver circuit 260A drive level converter circuit 263.Level converter circuit 263A and coupling mechanism 109A coupling, and the signal that will obtain from one or more input signals is supplied with coupling mechanism 109A.The signal of supplying with coupling mechanism 109A has the voltage amplitude of a minimizing.

[0042] coupling mechanism 109A offers acceptor circuit 205 to the signal that receives from drive circuit 203.Acceptor circuit 205 comprises a predriver circuit or the regulating circuit 260B first order as it.As required, predriver circuit 260B can have and similar circuit arrangement of predriver circuit 260A and topological structure.The signal that predriver circuit 260B receives from coupling mechanism 109A according to it obtains one or more signals, and provides these signals (one or more) at its output terminal.Predriver circuit 260B and PLD circuit 270 are coupled, and it is driven.PLD circuit 270 is at its input end (one or more) acceptance criteria amplitude logical signal.

[0043] Fig. 8 and Figure 10-Figure 13 provide the circuit arrangement according to the illustrative embodiment of interconnection circuit of the present invention, and this interconnection circuit comprises low energy-consumption driver and interlock circuit.Fig. 9 shows the curve map of some signal that uses in certain embodiments, and this will be described in more detail below.

Notice that [0044] each among Fig. 8 and Figure 10-Figure 13 embodiment includes drive circuit 203 and acceptor circuit 205.Each drive circuit 203 (for example 203A/203B) comprises predriver circuit 260 (for example 260A/260B) and level converter circuit 263 (for example 263A/263B).Level translator 263A among Fig. 8 and Figure 10-Figure 13 and 263B are similarly, and operation is also similar.In addition, the embodiment among Fig. 8 and Figure 10-Figure 13 comprises the transistor 301,304 and 307 of similar layout, and the interlock circuit that drives these transistorized grids, and these interlock circuits are operation in a similar fashion also.

[0045] with reference to the circuit arrangement among the figure 8 280, predriver circuit 260A comprises

transistor

283A, 286A, 289A and 292A.Level translator 263A comprises transistor 295A and

298A.Transistor

286A and 289A form a transverter, as benefit from instructions of the present invention those of ordinary skills understood.Transistor 292A and transistor 289A series coupled (and use identical gate signal, i.e. the input signal of circuit arrangement 280).

[0046] transistor 292A has a relative higher threshold voltage (V _T), be sometimes referred to as high V _T(HVT) transistor.For example, transistor 292A can have a threshold voltage, and it departs from the nominal threshold voltage+80mV that is used for specific fabrication process.

[0047] has the combination of transistor 289A with the transistor 292A of a nominal threshold voltage, allow predriver circuit 260A a non-zero input voltage to be thought the signal of logic low with a relative higher threshold voltage.For example, predriver circuit 260A can have about V to one _TPThe voltage of (the transistorized nominal threshold voltage of PMOS) value is thought the signal of logic low.Under the situation that lacks transistor 292A, transistor 289A is V in the value of input voltage _TP(perhaps approximate V _TP) time possibly can't turn-off.

[0048] in addition, the relative higher threshold voltage of transistor 292A helps to prevent that it from opening or conducting, leaks (that is, it has reduced crow bar electric current (crow-bar current)) thereby prevent to produce the electric current that causes power consumption to increase.In other words, relatively higher threshold voltage helps to reduce the leakage current in the tandem compound of

transistor

289A and 292A, thereby has reduced the leakage current of described transverter.Transistor 283A has served as a drawing device, and utilizes regeneration feedback, recovers the input signal of logic high.

[0049] more specifically, the input of a logic high can have a voltage lower than nominal voltage (for example causing owing to being coupled by MUX or transmission transistor).The regenerative operation of transistor 283A makes this voltage return to the signal (V of a logic high _DD).This transverter and transistor 283A have been combined to form one and half locks (half lock), as benefit from instructions of the present invention those of ordinary skills understood.

[0050] the output drive level converter 263A of transverter.Level translator 263A comprises the transistor 295A and the transistor 298A of series coupled.Level translator 263A and transverter remove and have exchanged outside PMOS and the nmos device (be that the PMOS device occupies down lamination or storehouse (stack), and nmos device being formed superimposed layer), have similar topological structure.Because this topological structure, the output of level translator 263A has a voltage amplitude that has reduced.

[0051] more specifically, the output voltage of level translator 263A has one at (V _GND+ V _TP) and (V _DD-V _TN) between voltage amplitude, V wherein _TPAnd V _TNThe threshold voltage of representing

transistor

298A and 295A respectively.Therefore, level translator 263A has than typical cmos circuit (promptly at V _GNDAnd V _DDBetween) littler voltage amplitude.As mentioned above, the voltage amplitude that reduces helps to reduce power consumption.

[0052] predriver circuit 260B comprises

transistor

283B, 286B, 289B and 292B.Level translator 263 comprises transistor 295B and 298B.Predriver circuit 260B and level translator 263B operate similarly with predriver circuit 260A and level translator 263A respectively.According to simulation result, in one embodiment, circuit arrangement 280 can provide the energy than classic method saving 29%.

[0053] coupling mechanism 109A and

transistor

301 and 304 are coupled to predriver 260B with level translator 263A.Storage unit driving transistors 301 among the

CRAM

133 and 304 grid.Therefore,

transistor

301 and 304 has played the effect of transmission transistor effectively.According to the data in CRAM 133 storage unit,

transistor

301 and 304 can optionally be coupled to predriver 260B with level translator 263A.Notice that people can use the transistor and the storage unit of varying number or layout as required, as benefit from instructions of the present invention those of ordinary skills understood.

[0054] transistor 307 has served as and has pulled up transistor.Under the situation that

transistor

301 and 304 all turn-offs, transistor 307 can be pulled to the input of predriver 260B near supply voltage, and prevents that therefore this input is unsteady or have uncertain value.The grid of signal NFREEZE driving transistors 307.Notice that the embodiment among Figure 10-Figure 13 has used similar circuit arrangement.

[0055] the signal NFREEZE that shows in the 103 initial power-up stages of PLD of Fig. 9 is with respect to the sequential chart of supply voltage.At t=t ₀The place, supply voltage 313 beginnings are to its end value V _DDRise.t ₀Afterwards, at t=t ₁Constantly, signal 310 (NFREEZE) begins to one near V _DDEnd value rise.But, at t=t ₀And t=t ₁The centre, signal 310 has the value of a logic low.As a result, transistor 307 is opened, and the input of predriver 263B is increased near V _DD, the perhaps value of a logic high.Notice that people can utilize many other to be different from sequential shown in Figure 9 and signaling plan as required, as benefit from those of ordinary skills of the present invention and understand.

[0056] Figure 10 shows a circuit arrangement 320 in the illustrative embodiment that is used in interconnection circuit of the present invention, comprises low energy-consumption driver and interlock circuit.Circuit arrangement 320 comprises drive circuit 203 and acceptor circuit 205.Drive circuit 203 comprises predriver circuit 260A and level translator 263A.Acceptor circuit 205 comprises predriver circuit 260B and level translator

263B.Predriver circuit

260A and 260B have similar topological structure, and operation in an identical manner.Equally,

level translator

263A and 263B have similar topological structure and operation similarly.

[0057] predriver circuit 260A comprises transistor 283A, 325A, 330A, 335A and 340A.The circuit that transistor 283A, 325A, 330A and 335A are constituted is similar to the predriver 260A among Fig. 8.Therefore, transistor 335A has a higher relatively V _T(HVT), it causes energy consumption to reduce, as mentioned above.But the predriver 260A among Figure 10 comprises an extra transistor 340A.

[0058] drain electrode end of transistor 340A and V _DDBe coupled.It is (V at a low input transition period that transistor 340A presets node 350A (that is the node between transistor 330A and the hvt transistor 335A) _DD-V _TN) (in some sense, transistor 340A has played the effect of Schmidt trigger).That is to say that (input of this circuit has V when input has a logic low state _TPValue), transistor 340A remains on (V with node 350 _DD-V _TN).Under the situation of logic low input, transistor 340A makes transistor 330A obtain a higher source voltage.High source voltage makes transistor 330A have higher threshold voltage, and therefore has less static energy consumption.

[0059] more specifically, the threshold voltage VT of transistor 340A depends on many factors, for example the voltage between its source electrode and the body (body).Establishing an equation down provides threshold voltage as body-source voltage function:

V_{T} = V_{T (0)} + γ {\sqrt{{2 φ}_{F} - v_{BS}} - \sqrt{{2 φ}_{F}}} - - - (1)

Perhaps, people can be write as equation 1 according to source electrode-bulk voltage:

V_{T} = V_{T (0)} + γ {\sqrt{{2 φ}_{F} + v_{SB}} - \sqrt{{2 φ}_{F}}} - - - (2)

Wherein:

V _{T (0)}=threshold voltage when source electrode-bulk voltage (perhaps body-source voltage) is made as zero.

γ=body the factor, a constant that depends on the bulk doped degree.

φ _F=one constant.

v _BS=total body-source voltage (promptly comprising AC and DC component);

And

v _SB=total source electrode-bulk voltage (promptly comprising AC and DC component).

[0060] notes, as body-source voltage v _BS(perhaps source electrode-bulk voltage v _SB) when equalling zero, threshold voltage V _TEqual V _{T (0)}Shown in equation 2, for a limited body factor gamma, transistorized threshold voltage is along with source electrode-bulk voltage v _SBIncrease and increase.The increase of threshold voltage has reduced leakage current, and has therefore reduced static energy consumption.Therefore, also therefore improve its source electrode-bulk voltage v by the source voltage that improves transistor 330A _SB, transistor 340A has reduced the energy consumption of predriver circuit 260A.According to simulation result, in one embodiment, circuit arrangement 280 can be saved 35% energy than classic method.

[0061] predriver circuit 260B comprises transistor 325B, 330B, 335B and 340B.Level translator 263B comprises transistor 295B and 298B.The operation of predriver circuit 260B and level translator 263B is similar with level translator 263A to predriver 260A respectively.According to simulation result, in one embodiment, circuit arrangement 280 can be saved 35% energy than classic method.

[0062] Figure 11 shows one and is used in according to the circuit arrangement in the illustrative embodiment of interconnection circuit of the present invention 360, and it comprises low energy-consumption driver and interlock circuit.Circuit arrangement 360 comprises drive circuit 203 and acceptor circuit 205.Drive circuit 203 comprises predriver circuit 260A and level translator 263A.Acceptor circuit 205 comprises predriver circuit 260B and level translator 263B.Predriver circuit 260A has similar topological structure with 260B and operates in a kind of identical mode.Equally,

level translator

263A and 263B have similar topological structure and operation similarly.

[0063] predriver circuit 260A comprises transistor 363A-

384A.Transistor

372A and 375A are coupled as the series connection lamination that a complementary signal drives.Different with the predriver circuit of describing among each figure of front, predriver 260A does not comprise half lock.On the contrary, independent circuit utilizes the complement gate signal to come the grid of driving

transistors

372A and 375A.

[0064] more specifically,

transistor

363A, 366A and 369A drive the grid of PMOS transistor 372A.The circuit of driving transistors 372A comprises a series connection lamination of nmos pass transistor (being

transistor

366A and 369A).On the contrary, the grid of

transistor

384A, 378A and 381A driving N MOS transistor 375A.The circuit of driving circuit 375A comprises a series connection lamination of PMOS transistor (being transistor 378A and 381A).This layout of the circuit of described driving

transistors

372A and 375A has reduced the crow bar electric current by predriver circuit 260A.

[0065] operation of predriver circuit 260A is as follows: if input signal has the signal (V of a logic high _DD-V _TN), transistor 363A turn-offs, and

transistor

366A and 369A then are conductings.The input signal of logic high also makes transistor 378A and transistor 381A turn-off, transistor 384A conducting, thus the grid of transistor 375A is pulled to the circuit earth potential.As a result, transistor 375A turn-offs, transistor 372A conducting, thus the signal of a logic high is provided to level translator 263A.

[0066] opposite, if input signal has the signal (V of a logic low _TP), transistor 363A conducting so, and

transistor

366A and 369A turn-off.Thereby described logic low input signal also makes transistor 378A and 381A conducting that the grid of transistor 375A is drawn high, and transistor 384A is turn-offed.As a result, transistor 375B turn-offs, and transistor 375A also turn-offs, thereby the signal of a logic low is provided to level translator 263A.

[0067] predriver circuit 260B comprises transistor 363B-384B, and itself and predriver circuit 260A layout are similar.Level translator 263B comprises transistor 295B and 298B.The operation of predriver circuit 260B and level translator 263B is similar with predriver 260A and level translator 263A respectively.According to simulation result, in one embodiment, circuit arrangement 280 can be saved 35% energy than classic method.

[0068] Figure 12 shows a circuit arrangement 400 that is used in according to the illustrative embodiment of interconnection circuit of the present invention, and it comprises low energy-consumption driver and interlock circuit.Circuit arrangement 400 comprises drive circuit 203 and acceptor circuit 205.Drive circuit 203 comprises predriver circuit 260A and level translator 263A.Acceptor circuit 205 comprises predriver circuit 260B and level translator 263B.Predriver circuit 260A has identical topological structure and operation in the same manner with 260B.Equally,

level translator

263A and 263B have similar topological structure and operation similarly.

[0069] predriver circuit 260A comprises

transistor

403A, 406A, 409A, 412A, 415A and

418A.Transistor

403A and 418A provide a feedback mechanism for drive circuit 203.The PMOS lamination of a series connection is formed in

transistor

406A and 409A coupling.On the contrary,

transistor

412A and 415A are coupled and form a series connection NMOS lamination.Input signal and PMOS lamination (being the grid of

transistor

406A and 409A) and NMOS lamination (being the grid of

transistor

412A and 415A) coupling, and drive them.

[0070] comprise that in drive circuit 203 PMOS and NMOS lamination and

feedback transistor

403A and 418A have reduced the crow bar electric current of predriver 260A, similar to related circuit described in Figure 11.But different with the circuit among Figure 11 is that circuit arrangement 400 is to utilize feedback (by

transistor

403A and 418A) to realize this function.And these PMOS and NMOS lamination reduce or are tending towards reducing static leakage currents.As a result, the energy loss-rate traditional circuit of circuit arrangement 400 is little.

[0071] operation of predriver circuit 260A is as follows: suppose that the output signal (being node 425) of predriver circuit 260A has the value (V of a logic low _TP), and input signal changes the value of a logic low into.As a result,

transistor

406A and 409A conducting, and

transistor

412A and 415A turn-off.Thereby PMOS lamination (

transistor

406A and 409A) is drawn high the voltage (V of node 421 _DD-V _TN).

[0072] owing to there is this ultramagnifier, when input made it be transformed into low signal, transistor 403A almost completely turn-offed.Same owing to have this ultramagnifier, almost completely conducting of transistor 418A.Opposite result will appear for opposite input value, as benefit from instructions of the present invention those of ordinary skills understood.

[0073] predriver circuit 260B comprises

transistor

403B, 406B, 409B, 412B, 415B and 418B.Level translator 263B comprises transistor 295B and 298B.The operation of predriver circuit 260B and level translator 263B is similar with predriver 260A and level translator 263A respectively.According to simulation result, in one embodiment, circuit arrangement 280 can be saved 42% energy than classic method.

[0074] Figure 13 shows one and is used in according to the circuit arrangement in the illustrative embodiment of interconnection circuit of the present invention 430, and it comprises low energy-consumption driver and interlock circuit.Circuit arrangement 430 comprises drive circuit 203 and acceptor circuit 205.Drive circuit 203 comprises predriver circuit 260A and level translator 263A.Acceptor circuit 205 comprises predriver circuit 260B and level translator

263B.Predriver circuit

260A and 260B have similar topological structure and operation in the same manner.Equally,

level translator

263A and 263B have similar topological structure and operation similarly.

[0075] predriver circuit 260A comprises PMOS transistor 433A and nmos pass

transistor 436A.Transistor

433A and 436A are coupled and form a transverter, as known to a person of ordinary skill in the art.But different with common transverter, transistor 433A has relative higher threshold voltage (V with 436A _T), be called as superelevation V sometimes _T(SHVT) transistor.For example,

transistor

433A or 436A can have a threshold voltage that departs from the nominal threshold voltage 80mV of described specific fabrication process.

[0076] utilize

transistor

433A and 436A (it has relative higher threshold voltage) to reduce predriver circuit 260A crow bar electric current.More specifically, suppose that input has the value (V of a logic high _DD-V _TN).Having the common PMOS transistor of nominal threshold voltage may conducting and conduct some electric currents, thereby produces higher relatively crow bar electric current.

[0077] if this input has the value (VTP) of a logic low, the common nmos pass transistor with nominal threshold voltage may conducting, the finite value electric current that causes the crow bar electric current to raise occurs.But, utilize to have higher absolute threshold voltage (for example SHVT)

transistor

433A and 436A, can avoid these situations.In other words, the relative higher threshold voltage of transistor 433A stops its conducting when logic low value is imported.On the contrary, the relative higher threshold voltage of transistor 433B stops its conducting when input signal has the value of logic high.

[0078] level translator 263A comprises transistor 295A and

298A.Transistor

295A and 298A have relatively low threshold voltage, are sometimes referred to as low threshold voltage (LVT).For example,

transistor

295A or 298A can have the threshold voltage of the nominal threshold voltage-80mV that departs from specific fabrication process.The relatively low threshold voltage of

transistor

295A and 298A has guaranteed the reliability of level translator 263 and the operation of enhancing.

[0079] more specifically, have the transistor 295A of relatively low threshold voltage (LVT) and 298A and cause the amplitude output signal that reduces, i.e. V _DD-V _{TN (LVT)}Logic be high level and V _GND+ V _{TP (LVT)}Logic be low level, wherein V _{TN (LVT)}And V _{TP (LVT)}Represent relatively low threshold voltage (LVT).Because predriver electric current 260B utilizes transistor 433B and the 436B with higher absolute threshold voltage (SHVT), the level of used logic high and the level of logic low have been guaranteed the transistor complete " shutoff " among the predriver circuit 260B.

[0080] that is to say, described circuit relies on the poor of transistorized threshold voltage in transistor AND gate acceptor circuit 205 first order in drive circuit 203 second level, guarantees normal running and (perhaps having less relatively) static static leakage currents do not occur.In addition, relatively low threshold voltage causes the current driving ability of

transistor

295A and 298A (and, similarly,

transistor

295B and 298B) to increase, and then causes their operating speed to increase.

[0081] predriver circuit 260B comprises PMOS transistor 433B and nmos pass

transistor 436B.Transistor

433B and 436B have respectively and transistor 433A and the similar characteristic of 436A.Level translator 263B comprises transistor 295B and 298B.Predriver circuit 260B and level translator 263B operate similarly with predriver circuit 260A and level translator

263A respectively.Transistor

295B and 298B have respectively and transistor 295A and the similar characteristic of 298A.According to simulation result, in one embodiment, circuit arrangement 430 can be saved 42% energy than classic method.

[0082] notes, as benefit from the understood by one of ordinary skill in the art of instructions of the present invention, people can be applied to the foregoing invention principle in the various programmable integrated circuits (IC) as required effectively, and wherein said programmable integrated circuit comprises logical circuit able to programme or configurable (they also are called as other titles in the art).For example, this type of circuit has comprised the device that is called as CPLD (CPLD), programmable gate array (PGA), structuring application specific IC (structured ASIC) and field programmable gate array (FPGA).

[0083] with reference to accompanying drawing, those of ordinary skills it should be noted that shown various modules can have been described principle function and signal flow substantially.Actual circuit embodiment can comprise also can not comprise the independence of described various functional modules or the discernible hardware of separation, and can use the particular electrical circuit shown in also can not utilizing.For example, people can be incorporated in the function of various modules in the circuit module as required.And people can utilize several circuit modules to realize the function of individual module as required.Various factors is depended in the selection of circuit embodiment, for example be used for the particular design and the specification of given embodiment, as benefit from instructions of the present invention those of ordinary skills understood.For benefiting from those of ordinary skills of instructions of the present invention, except embodiment as herein described, other modification of the present invention and alternate embodiment are tangible.Therefore, this instructions has been introduced to those skilled in the art and has been implemented mode of the present invention, should be regarded as merely illustrative.

[0084] should be considered to current preferred or illustrative embodiment with described form of the present invention shown in.Under the situation that does not break away from scope of invention described herein, those skilled in the art can make various modifications to its shape, size and each several part layout etc.For example, those skilled in the art can replace element shown and described herein with equivalent element.And the those skilled in the art that benefit from instructions of the present invention can be independent of the use of further feature without departing from the present invention when using some feature of the present invention.

Claims

1. interconnection circuit comprises:

Drive circuit, it is configured to obtain a finite amplitude driver output signal from an input signal; And

Acceptor circuit, it is coupled in described drive circuit, and described acceptor circuit is configured to obtain a finite amplitude receiver output signal from described finite amplitude driver output signal.

2. interconnection circuit according to claim 1, wherein said finite amplitude driver output signal has one first signal condition and a secondary signal state, wherein said first signal condition has the current potential higher than earth potential corresponding to described finite amplitude driver output signal, and described secondary signal state has the current potential lower than supply voltage corresponding to described limited voltage amplitude driver output signal.

3. interconnection circuit according to claim 1, wherein said finite amplitude receiver output signal has one first signal condition and a secondary signal state, wherein said first signal condition has the current potential higher than earth potential corresponding to described finite amplitude receiver output signal, and described secondary signal state has the current potential lower than supply voltage corresponding to described limited voltage amplitude receiver output signal.

4. interconnection circuit according to claim 1, wherein said input signal is provided by first Programmable Logic Device in the programmable logic device (PLD) PLD.

5. interconnection circuit according to claim 1 further comprises:

The predriver circuit; And

Level converter circuit, it is coupled in described predriver circuit.

6. interconnection circuit according to claim 5, wherein said level converter circuit comprise a PMOS transistor, and this PMOS transistor is coupled to a nmos pass transistor.

7. interconnection circuit according to claim 5, wherein said predriver circuit further comprises a plurality of transistors of cascade coupled, the first transistor in wherein said a plurality of transistors has a threshold voltage higher than nominal threshold voltage.

8. interconnection circuit according to claim 7, wherein said predriver circuit further comprises a transistor seconds that is coupled in described the first transistor, and one is coupled in described the first transistor and earthy the 3rd transistor.

9. interconnection circuit according to claim 5, wherein said predriver circuit further comprises a PMOS transistor, this PMOS transistors couple is in a nmos pass transistor, wherein said PMOS transistor is driven by one first signal, and described nmos pass transistor is driven by a secondary signal, and wherein said first and second signals comprise complementary signal.

10. interconnection circuit according to claim 5, wherein said predriver circuit further comprises:

The PMOS transistor, it is driven by a feedback signal that obtains from described driver output signal; With

Nmos pass transistor, it is driven by the described feedback signal that obtains from described driver output signal.

11. interconnection circuit according to claim 5, wherein said predriver circuit further comprises:

The PMOS transistor, it has a threshold voltage higher than nominal threshold voltage; With

Nmos pass transistor, it has a threshold voltage higher than nominal threshold voltage, and is coupled to described PMOS transistor.

12. interconnection circuit, its interior resource of programmable logic device (PLD) PLD that is used to be coupled, described interconnection circuit comprises a drive circuit, and this drive circuit comprises at least one transistor, and this at least one transistor has than a threshold voltage that nominal threshold voltage is higher.

13. interconnection circuit according to claim 12, wherein said drive circuit comprise a predriver circuit, it is coupled in a level converter circuit.

14. interconnection circuit according to claim 12 further comprises an acceptor circuit, it comprises at least one transistor, and this at least one transistor has the threshold voltage higher than described nominal threshold voltage.

15. interconnection circuit according to claim 14, wherein said drive circuit obtain a finite amplitude driver output signal from an input signal.

16. interconnection circuit according to claim 15, wherein said finite amplitude driver output signal has one first signal condition and a secondary signal state, described first signal condition has a voltage higher than earth potential, and described secondary signal state has a voltage lower than supply voltage.

17. interconnection circuit according to claim 14, wherein said acceptor circuit obtain a finite amplitude receiver output signal from described finite amplitude driver output signal.

18. interconnection circuit according to claim 17, wherein said finite amplitude receiver output signal has one first signal condition and a secondary signal state, wherein said first signal condition has a voltage higher than earth potential, and described secondary signal state has a voltage lower than supply voltage.

19. interconnection circuit according to claim 13, wherein said level converter circuit comprise a PMOS transistor, it is coupled in a nmos pass transistor.

20. interconnection circuit according to claim 12, wherein said drive circuit further comprise a plurality of transistors of cascade coupled, the first transistor in wherein said a plurality of transistors has a threshold voltage higher than described nominal threshold voltage.

21. interconnection circuit according to claim 20, wherein said drive circuit further comprise a transistor seconds that is coupled in described the first transistor, and one is coupled in described the first transistor and earthy the 3rd transistor.

22. interconnection circuit according to claim 12, wherein said drive circuit further comprises a PMOS transistor, it is coupled in a nmos pass transistor, wherein said PMOS transistor is driven by one first signal, described nmos pass transistor is driven by a secondary signal, and wherein said first and second signals comprise complementary signal.

23. interconnection circuit according to claim 12, wherein said drive circuit further comprises:

24. interconnection circuit according to claim 12, wherein said drive circuit further comprises:

The PMOS transistor, it has a threshold voltage higher than described nominal threshold voltage; With

Nmos pass transistor, it has a threshold voltage higher than described nominal threshold voltage, and is coupled in described PMOS transistor.

25. interconnection circuit according to claim 14, wherein said drive circuit are coupled in one first Programmable Logic Device in the described PLD, and described acceptor circuit is coupled in one second Programmable Logic Device in the described PLD.

26. the method for the circuit in the interconnection programmable logic device (PLD) (PLD), described method comprises:

In first circuit, receive an input signal from a signal source;

Produce an output signal of described first circuit, the described output signal of wherein said first circuit has a finite amplitude;

The described output signal of described first circuit is supplied with a second circuit; And

Produce an output signal of described second circuit, the output signal of wherein said second circuit has a finite amplitude.

27. method according to claim 26 wherein, receives described input signal and comprises that further a Programmable Logic Device from described PLD receives described input signal.

28. method according to claim 27 further comprises: the output signal of described second circuit is supplied with one second Programmable Logic Device in the described PLD.

29. method according to claim 26, wherein said first circuit comprises at least one transistor, and this at least one transistor has the threshold voltage that is different from a nominal threshold voltage.

30. method according to claim 26, wherein said second circuit comprises at least one transistor, and this at least one transistor has the threshold voltage that is different from a nominal threshold voltage.

31. method according to claim 26, wherein said first circuit comprises drive circuit.

32. method according to claim 31, wherein said second circuit comprises acceptor circuit.

33. method according to claim 26 wherein, is supplied with a second circuit with the described output signal of described first circuit and is further comprised, comes the described output signal of described first circuit of route by a plurality of transistors.

34. method according to claim 26, the described output signal of wherein said first circuit has one first state and one second state, described first state is corresponding to being different from an earthy voltage level, and described second state is corresponding to a voltage level that is different from supply voltage.

35. method according to claim 26, the described output signal of wherein said second circuit has one first state and one second state, described first state is corresponding to being different from an earthy voltage level, and described second state is corresponding to a voltage level that is different from supply voltage.