CN1904773A - Radio wave receiving apparatus, radio wave receiving circuit and radio wave timepiece - Google Patents

Abstract

In the radio-wave receiving apparatus according to the invention, a signal received by a receiving antenna (621) is amplified and the amplified received signal is input into a multi-stage frequency conversion circuit (623) including a plurality of basic circuits (624n) connected in series. The multi-stage frequency conversion circuit (625) converts the frequency of the received signal from the antenna into frequencies based on signals (gn) input from the frequency divider circuit sequentially, thereby to output a signal ''a'' which is obtained by conversions into gradually lower frequencies. Detection is performed by a detection circuit (626) on the basis of the signal. Thereby, a radio-wave receiving apparatus which requires no local oscillating circuit nor a PLL circuit and is also stable in operation and high in accuracy is realized.

Description

Radio wave receiver, radio wave receiving circuit and Wave timepiece

The reference of related application

The application is based on formerly Japanese patent application No.2005-217469 (submission on July 27th, 2005) and No.2005-345640 (submission on November 30th, 2005), and requires their right of priority, and its full content is incorporated into here as a reference.

Technical field

The present invention relates to for example radio wave receiver, radio wave receiving circuit and the Wave timepiece of acceptance criteria electric wave.

Background technology

Now, in various countries (for example Japanese, Germany, Britain, Switzerland etc.), sending adding moment data is the long wave standard wave of timing code (time code).In Japan, the timing code of the form of use long wave standard wave has been carried out the long wave standard wave of amplitude-modulated 40kHz and 60kHz by two transmitting stations transmissions in Fukushima county and Saga county.This timing code is that each divides the frame with 60 seconds one-periods to send in each position of upgrading correct branch.

In recent years, receive such joining day sign indicating number standard wave, and the so-called Wave timepiece (radiowave timepiece) of revising current time thus just be practical.Wave timepiece, by built-in antenna acceptance criteria electric wave, and amplify to received signal, detection etc., understand timing code thus, revise current time.In addition, in Wave timepiece, it is also known for can the different Wave timepiece a plurality of standard waves, so-called multibandization of receive frequency.

Radio wave receiver in the Wave timepiece of multibandization, main flow is that the local oscillation signal of received signal and assigned frequency is transformed to intermediate frequency signal (IF signal) after synthetic and is the superhet mode that detection is carried out on the basis with this intermediate frequency signal, but, under this kind situation, need the frequency local oscillation signal corresponding with the standard electric wave frequency of reception.

As structure for this reason, known have a following structure etc.: (1) is for each frequency of the standard wave that receives, structure with a plurality of local oscillator circuits of the output local oscillation signal corresponding with this frequency, (2) local oscillator circuit is set, switch the structure of the oscillation frequency of this local oscillator circuit by the ON/OFF of receive frequency selector switch, (3) local oscillator circuit is also used as the oscillatory circuit that timing is used, with the frequency dividing ratio corresponding the reference frequency signal of the 32.768kHz of the oscillatory circuit output used from this timing is carried out frequency division, thereby form the structure of local oscillation signal with the standard electric wave frequency that receives.

But, in the radio wave receiver of above-mentioned existing multibandization, have following problems.That is, under the situation that a plurality of oscillatory circuits corresponding with the standard electric wave frequency that receives are set, it is big that the circuit scale of radio wave receiver becomes (1), thereby existence causes cost to increase and the problem of the frequency limited of receivable standard wave.In addition, as (2), have under the situation of local oscillator circuit, this local oscillator circuit for example constitutes by PLL (Phase LockedLoop) circuit with VCO (Voltage Controlled Oscillator), but in the PLL circuit, there is such problem: be closed into from power supply that action is stable to need the time and according to the setting of reference frequency, from the oscillation frequency instability of VCO output.

In addition, the reference frequency signal of timing being used in (3) carries out frequency division with under the situation that forms local oscillation signal, fractional frequency signal with for being the frequency transformation of received signal that the needed frequency of intermediate frequency is not quite identical, exist because the deviation of this frequency and the problem that can not correctly carry out detection.

Summary of the invention

Therefore, the present invention amplifies the received signal that receives by receiving antenna with the RF amplifying circuit, and the received signal after this amplification is input to the multistage frequency-conversion circuit of being made up of a plurality of basic circuits of plural serial stage connection.Multistage frequency-conversion circuit according to the signal from frequency dividing circuit input, transforms to frequency based on this signal to the received signal that is received by antenna in turn, exports thus and transforms to low-frequency signal a gradually, carries out detection based on signal a by detecting circuit.Thus, not needing to realize the high stable and the high-precision radio wave receiver of local oscillator circuit or PLL circuit.

Description of drawings

Fig. 1 is the structural drawing of the Wave timepiece in the embodiments of the present invention.

Fig. 2 is the structural drawing of radio wave receiver of the present invention.

Fig. 3 is the structural drawing of basic circuit of the present invention.

Fig. 4 is the structural drawing of detecting circuit of the present invention.

Fig. 5 A～Fig. 5 D is the figure of appearance of the frequency spectrum of the reception action when representing to be used to illustrate the standard wave that receives 40kHz in the present invention with image mode.

Fig. 6 is the figure of the reception action during the standard wave that receives 40kHz in the present invention when being considered as the BPF of extremely narrow frequency band.

Fig. 7 A～Fig. 7 D is the figure of appearance of the frequency spectrum of the reception action when representing to be used to illustrate the standard wave that receives 77.5kHz in the present invention with image mode.

Fig. 8 A～Fig. 8 B is the figure of appearance of the frequency spectrum of the reception action when representing to be used to illustrate the standard wave that receives 77.5kHz in the present invention with image mode.

Fig. 9 is the figure of the reception action during the standard wave that receives 77.5kHz in the present invention when being considered as the BPF of extremely narrow frequency band.

Figure 10 is the complete list of the signal of fractional frequency signal when receiving the standard wave of each frequency in the present invention and frequency transformation (multiplication is synthetic).

Figure 11 A is the structural drawing of the basic circuit in the first embodiment of the present invention.

Figure 11 B is the structural drawing of other basic circuits in the first embodiment of the present invention.

Figure 12 is the structural drawing of the radio wave receiver in the second embodiment of the present invention.

Figure 13 A is the structural drawing of the basic circuit in the second embodiment of the present invention.

Figure 13 B is the table of relation of the connection status of the use that is illustrated in the basic circuit 624B among Figure 13 A/do not use and switch SW 2, SW3.

Figure 14 A is the structural drawing of the basic circuit in the third embodiment of the present invention.

Figure 14 B is the table of relation of the connection status of the use that is illustrated in the basic circuit 624C among Figure 14 A/do not use and switch SW 5, SW3.

Figure 15 is the structural drawing of the radio wave receiver in the fourth embodiment of the present invention.

Figure 16 is the structural drawing of the radio wave receiver of the variation among the present invention.

Figure 17 A is the key diagram of picture signal.

Figure 17 B is the key diagram of picture signal.

Figure 18 is the structural drawing of the basic circuit in the fifth embodiment of the present invention.

Figure 19 is the structural drawing of the phase-shift circuit in the fifth embodiment of the present invention.

Figure 20 A is the principle key diagram that the picture signal in the fifth embodiment of the present invention is removed.

Figure 20 B is the principle key diagram that the picture signal in the fifth embodiment of the present invention is removed.

Figure 21 is the structural drawing of the radio wave receiver of the variation among the present invention.

Figure 22 is the structural drawing of the multistage frequency-conversion circuit of the variation among the present invention.

Figure 23 A is the concept map of the phase relation of two signals that the frequency transformation by the first order generates in variation of the present invention.

Figure 23 B is the concept map of the frequency relation of two signals that the frequency transformation by the first order generates in variation of the present invention.

Figure 24 A and Figure 24 B are the concept maps of the phase relation of two signals generating by partial frequency transformation in variation of the present invention.

Figure 25 is the concept map of the frequency relation of two signals generating by partial frequency transformation in variation of the present invention.

Figure 26 is the movement content of each adder-subtractor of multistage frequency-conversion circuit shown in Figure 22.

Embodiment

With reference to the accompanying drawings, preferred implementation of the present invention is described.

[Wave timepiece]

Fig. 1 is the block diagram of the structure of the Wave timepiece in the expression present embodiment.As known in the figure, Wave timepiece 1 has CPU (Central Processing Unit) 100, input part 200, display part 300, ROM (Read Only Memory) 400, RAM (Random Access Memory) 500, receives control part 600, timing code generating unit 700, timing circuit portion 800 and oscillatory circuit portion 900.Each one except that oscillatory circuit portion 900 connects by bus B, and oscillatory circuit portion 900 is connected with radio wave receiver 620 and timing circuit portion 800.

In addition, CPU100, ROM400, RAM500, reception control part 600, timing code generating unit 700, timing circuit portion 800 and oscillatory circuit portion 900 can use SIC (semiconductor integrated circuit) to generate.

CPU100 is in predetermined timing or according to the operation signal from input part 200 input, reads out among the ROM400 program stored and launches in RAM500, each one that constitutes Wave timepiece 1 indicated or forwarding of data etc. according to this program.Specifically, for example receive the reception processing of control part 600 operative norm electric waves,, revise current time data by 800 timing of timing circuit portion according to standard time sign indicating number from 700 inputs of timing code generating unit every stipulated time control.

Input part 200 is made of the switch of the various functions that are used to carry out Wave timepiece 1 etc., when these switches are operated, to the corresponding operation signal of CPU100 output.Display part 300, with formations such as small-sized LCD, it shows current time etc. according to the shows signal from the CPU100 input.

ROM400, system program in the store electricity wave table 1 and application program and being used to realizes the program of present embodiment or data etc.RAM500, as using in the operating area of CPU100, program that interim storage is read from ROM400 or data etc.

Receive control part 600 and have radio wave receiver 620.Radio wave receiver 620, the unwanted frequency composition of the long wave standard wave that excision is received by receiving antenna takes out the correspondent frequency signal, is transformed to electric signal to 700 outputs of timing code generating unit.

Timing code generating unit 700 is the converting electrical signal from radio wave receiver 620 input a digital signal, generates the standard time sign indicating number of the data that comprise clock function needs such as etalon time sign indicating number or accumulation sign indicating number, week sign indicating number, and exports to CPU100.

Timing circuit portion 800, to counting from the signal of oscillatory circuit portion 900 input so that current time is carried out timing, and to CPU100 output current time data.Formations such as oscillatory circuit portion 900 usefulness crystal oscillators, the reference frequency signal of output 32.768kHz.

[radio wave receiver]

Fig. 2 is the block diagram of the concept structure of the radio wave receiver 620 in the expression present embodiment.According to this figure, radio wave receiver 620 has receiving antenna 621, RF amplifying circuit 622, multistage frequency-conversion circuit 623, frequency dividing circuit 625, detecting circuit 626, agc circuit 627.

Receiving antenna 621 for example constitutes by flagpole antenna, receives to comprise the standard wave of the assigned frequency of sign indicating number constantly, and the standard wave that receives is transformed to electric signal output.

RF amplifying circuit 622, according to the control signal h from agc circuit 627 inputs, amplification or decay are exported behind the signal of receiving antenna 621 inputs.

Multistage frequency-conversion circuit 623, have a plurality of basic circuit 624[1 that form by the n level that is connected in series], 624[2] ..., 624[n] (following general name " basic circuit 624 "), signal from 622 inputs of RF amplifying circuit, according to from signal g1, the g2 of frequency dividing circuit 625 input ..., gn (following general name " signal g "), be transformed to frequency in turn based on this signal g, thereby transform to low frequency gradually, export as signal a.

Fig. 3 represents the circuit structure of basic circuit 624.Basic circuit 624 is at the synthetic circuit (translation circuit) that carries out frequency transformation from the signal g (fractional frequency signal) of frequency dividing circuit 625 inputs of input signal comultiplication, according to this figure, has frequency mixer 6241, filtering circuit 6242, amplifier 6243.

Frequency mixer 6241 multiplication synthesize to the input signal of basic circuit 624 with behind the signal g of frequency dividing circuit 625 inputs to be exported.

Filtering circuit 6242 passes through the frequency of the low-frequency range of regulation by LPF formations such as (low-pass filters) for the signal from frequency mixer 6241 inputs, blocks extraneous frequency content.Corresponding input signal and the frequency of the signal g frequency band that passes through that determines this filtering circuit 6242 in this basic circuit 624.Specifically, filtering circuit 6242 constitute blocked input signal and signal g's and frequency, and its difference frequency is passed through.

Amplifier 6243, the signal from filtering circuit 6242 inputs, corresponding control signal I from agc circuit 627 inputs amplifies or export the back of decaying.The output of this amplifier 6243 becomes the output signal of this basic circuit 624.

The basic circuit 624 of a plurality of such formations of multistage frequency-conversion circuit 623 plural serial stages forms, and the output signal of the basic circuit 624 of prime is imported into each basic circuit 624 as input signal.Wherein, the output signal from RF amplifying circuit 622 is imported into elementary basic circuit 624[1 as input signal].Then, from the basic circuit 624[n of final level] output signal, become the output signal a of this multistage frequency-conversion circuit 623.

In Fig. 2, frequency dividing circuit 625 carries out frequency division with a plurality of ratios to the reference frequency signal bs from 900 inputs of oscillatory circuit portion or amplifies at double, they separately as signal g1, g2 ..., gn is to basic circuit 624[1], 624[2] ..., 624[n] output, and as signal f to detecting circuit 626 output.

Detecting circuit 626 uses from the signal f of frequency dividing circuit 625 inputs the signal a from multistage frequency-conversion circuit 623 inputs is carried out detection, exports as rectified signal d.This rectified signal d is imported into timing code generating unit 700, is used for the correction of current time.

Agc circuit 627, the power of corresponding signal a from multistage frequency-conversion circuit 623 inputs generates and control signal h and being used to that output is used for controlling the amplification degree of RF amplifying circuit 622 is controlled at the control signal i of amplification degree of the amplifier 6243 of each basic circuit 624.

[detecting circuit]

Fig. 4 represents the circuit structure of detecting circuit 626.According to this figure, detecting circuit 626, with the signal a from multistage frequency-conversion circuit 623 inputs is that detection is carried out on the basis, and this detecting circuit 626 is constituted as to have: 1/2 frequency divider 6261, logic gate 6262, frequency mixer 6263,6264, LPF6265,6266, squaring circuit 6267,6268, totalizer 6269.

6261 couples of signal f from frequency dividing circuit 625 inputs of 1/2 frequency divider carry out 1/2 frequency division, export as signal e1.Here, be the frequency setting of the signal f that gives 6261 inputs of 1/2 frequency divider 2 times of frequency of signal a, therefore, equal the frequency of signal a from the signal e1 of 1/2 frequency divider, 6261 outputs.

Logic gate 6262 computing signal f and XOR (EOR) from the signal e1 of 1/2 frequency divider 6261 input export operation result as signal e2.Therefore, this signal e2 becomes the signal that makes output signal e 1 phase shifts (phase shift) 90 degree.

Frequency mixer 6263, multiplication synthesize from the signal a of multistage frequency-conversion circuit 623 inputs with behind the signal e1 of 1/2 frequency divider, 6261 inputs to be exported.LPF6265 passes through the frequency of the low-frequency range of regulation for the signal from frequency mixer 6263 inputs, blocks extraneous frequency content, exports as signal b.6267 couples of signal b from the LPF6265 input of squaring circuit carry out exporting behind the square operation.

Frequency mixer 6264, multiplication synthesize behind the signal e2 of the signal a of multistage frequency-conversion circuit 623 inputs and logic gate 6262 inputs to be exported.LPF6266 passes through the frequency of the low-frequency range of regulation for the signal from frequency mixer 6264 inputs, blocks extraneous frequency content, exports as signal c.6268 couples of signal c from the LPF6266 input of squaring circuit carry out exporting behind the square operation.

Totalizer 6269 is carried out additive operation to the signal from squaring circuit 6267 inputs with the signal of importing from squaring circuit 6268, exports as rectified signal d.

Detecting circuit 626, by respectively to make figure signal that frequency reduces by multistage frequency-conversion circuit 623 and from the signal f of frequency dividing circuit 625 inputs and the signal after making this signal f phase shift 90 degree carry out multiplying, square operation, addition both sides' signal carries out detection thus.That is, by the I of operation transform signal, the quadratic sum of Q composition, even when the frequency of figure signal and reference signal or phase place produce small deviation, also can realize correct detection.

[receiving action]

The following describes the concrete reception action in the radio wave receiver 620.

When (I) receiving the standard wave (Japan) of 40kHz

When receiving the standard wave of 40kHz, multistage frequency-conversion circuit 623 is by 3 grades of basic circuit 624[1], 624[2], 624[3] constitute.In addition, Fig. 5 A～Fig. 5 D, Fig. 6 is the figure of appearance of frequency spectrum that represents to be used to illustrate the reception action of this situation with image mode.

At first, the elementary basic circuit 624[1 in multistage frequency-conversion circuit 623] in, respectively from the received signal of RF amplifying circuit 622 input 40kHz, from the signal g2 of frequency dividing circuit 625 inputs as the 32.768kHz of reference frequency signal bs.Then, shown in Fig. 5 A, by frequency mixer 6241, the received signal of the synthetic 40kHz of multiplication and the signal g2 of 32.768kHz, generate as both the frequency sum 72.768kHz signal and as the signal of the 7.232kHz of difference.

Here, if basic circuit 624[1] in the blocking frequency of filtering circuit 6242 as about 8kHz about, then in the signal that generates, 72.768kHz signal by 6242 blocking-up of this filtering circuit, 7.232kHz signal by filtering circuit 6242, by amplifier 6243 as this basic circuit 624[1] output signal output.

That is, we can say basic circuit 624[1] be equivalent to the BPF (bandpass filter) that in by frequency band, comprises as the 40kHz of input signal.In addition, the bandwidth of the BPF that this is of equal value, corresponding with the bandwidth of filtering circuit 6242.

Basic circuit 624[2 at next stage] in, import the basic circuit 624[1 of prime respectively] signal of output 7232Hz, by the signal g4 of the 8192Hz of frequency dividing circuit 6254 frequency divisions after as the 32768Hz of reference frequency signal bs.Then, shown in Fig. 5 B, the input signal of the synthetic 7232Hz of multiplication and the signal g4 of 8192Hz, generate as both the frequency sum 15424Hz signal and as the signal of the 960Hz of difference.

Here, if basic circuit 624[2] in the blocking frequency of filtering circuit 6242 as about 1kHz about, then in the signal that generates, the signal of 15424Hz is by these filtering circuit 6242 blocking-up, the signal of 960Hz is by filtering circuit 6242, as this basic circuit 624[2] output signal output.

That is, we can say basic circuit 624[2] be equivalent to the BPF that in by frequency band, comprises as the 7232Hz of input signal.In addition, the BPF that this is of equal value passes through bandwidth, with filtering circuit 6242 to pass through bandwidth corresponding, but because basic circuit 624[2] in filtering circuit 6242 pass through bandwidth ratio basic circuit 624[1] in filtering circuit 6242 pass through narrow bandwidth, so basic circuit 624[2] equivalence BPF pass through bandwidth, than basic circuit 624[1] equivalence BPF pass through narrow bandwidth.

Then, at the basic circuit 624[3 of final level] in, respectively from the basic circuit 624[3 of prime] signal of input 960Hz, from the signal g7 of the 1024Hz of frequency dividing circuit 625 inputs 32 frequency divisions after as the 32768Hz of reference frequency signal bs.Then, shown in Fig. 5 C, the input signal of the synthetic 960Hz of multiplication and the signal g7 of 1024Hz, generate as both the frequency sum 1984Hz signal and as the signal of the 64Hz of difference on the frequency.

Here, if basic circuit 624[3] in the blocking frequency of filtering circuit 6242 as about 70Hz about, then in the signal that generates, the signal of 1984Hz is by these filtering circuit 6242 blocking-up, the signal of 64Hz is by filtering circuit 6242, as this basic circuit 624[3] output signal output.This output signal is imported to detecting circuit 626 as the output signal a of multistage frequency-conversion circuit 623.

That is, we can say basic circuit 624[3] be equivalent to the BPF that in by frequency band, comprises as the 1024Hz of input signal.In addition, the BPF that this is of equal value passes through bandwidth, with filtering circuit 6242 to pass through bandwidth corresponding, but because basic circuit 624[3] in filtering circuit 6242 pass through bandwidth ratio basic circuit 624[2] in filtering circuit 6242 pass through narrow bandwidth, so basic circuit 624[3] equivalence BPF pass through bandwidth ratio basic circuit 624[2] in BPF of equal value pass through narrow bandwidth.

Then, detecting circuit 626, respectively from the signal a of multistage frequency-conversion circuit 623 input 64Hz, from frequency dividing circuit 625 inputs 256 frequency divisions as the signal g11 of the 128Hz of the 32768Hz of reference frequency signal bs as signal f, carry out detection.Promptly, shown in Fig. 5 D, by each of frequency mixer 6263,6264, the signal a of the synthetic 64Hz of multiplication and differ the signal e1 of the 64Hz of 90 degree phase places, each of e2 mutually, generation is as the signal of the 128Hz of both frequency sums with as the signal of the 0Hz of difference on the frequency.

Here, if LPF6265,6266 blocking frequency separately as about 5Hz about, then in the signal that generates, the signal of 128Hz is by LPF6265,6266 blocking-up, the signal of 0Hz is by LPF6265,6266, by 6267,6268 squares of squaring circuits, and then addition, export as rectified signal d.

That is, we can say that detecting circuit 626 is equivalent to the BPF that comprises 64Hz in by frequency band.In addition, the BPF that this is of equal value passes through bandwidth, with filtering circuit 6242 to pass through bandwidth corresponding, but because LPF6265,6266 pass through bandwidth ratio basic circuit 624[3] in filtering circuit 6242 pass through narrow bandwidth, so become than basic circuit 624[3] equivalence BPF pass through narrow bandwidth.

Therefore, be equivalent to 4 grades BPF of series connection, as shown in Figure 6, can think with the receive frequency to be that 40Hz is the BFP of the utmost point narrow-band at center as radio wave receiver 620 integral body.In Fig. 6, when the reception action of expression during the standard wave that receives shown in Fig. 5 A～Fig. 5 D is considered as the BPF of utmost point narrow-band or the figure when regarding comprehensive BPF as.

In addition, in multistage frequency-conversion circuit 623, by in each basic circuit 624 input signal and signal g (g2, g4 from the basic circuit 624 of prime, g7) the synthetic frequency that makes of multiplication reduces, and makes gradually from the frequency reduction of the received signal of RF amplifying circuit 622 inputs.That is, the bandwidth of passing through of the BPF of the equivalence of each basic circuit 624 narrows down gradually, therefore, can think that radio wave receiver 620 is the BPF of the utmost point narrow-band at center for the frequency with received signal all.

But, reception action in radio wave receiver 620 is above-mentioned such, still ideally, in fact not quite identical because of frequency or the phase place of signal a that imports from detecting circuit 626 and signal f, so might in the waveform of rectified signal d, produce fluctuating.But in the present embodiment,, can suppress the fluctuating of the waveform of the rectified signal d that causes by this deviation, realize correct detection by the I of computing signal a in detecting circuit 626, the quadratic sum of Q composition.

Specifically describe.

In Fig. 4, establishing from the signal a of detecting circuit 626 inputs is a=Asin ω t.So, be and the signal of the same frequency of this signal a to establish e1=sin (ω t+ φ (t)) from the signal e1 of 1/2 frequency divider, 6261 outputs.Here, φ (t) is the deviation with the phase place of signal a.Therefore, the output signal of frequency mixer 6263 provides with following formula (1).

[formula 1]

By making this signal block radio-frequency component by LPF6265, the signal b that exports from LPF6265 becomes b=A/2cos φ (t).

In addition, signal e2 is the signal of phase shifts 90 degree of signal e1, establishes e2=cos (ω t+ φ (t)).Therefore, the output signal of frequency mixer 6264 provides with following formula (2).

[formula 2]

By making this signal block radio-frequency component by LPF6266, the signal c that exports from LPF6266 becomes c=-A/2sin φ (t).

Then, signal b, c become from the rectified signal d of detecting circuit 626 outputs by totalizer 6269 added signal by squaring circuit 6267,6268 respectively square, provide with following formula (3).

[formula 3]

$d={\left\{\frac{A}{2}\cos \mathrm{\&phi;}\left(t\right)\right\}}^2+{\{-\frac{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="A20061010787500562.png,A20061010787500601.png"\; state="\{\{state\}\}">A</figure-callout>}}{2}\sin \mathrm{\&phi;}\left(t\right)\}}^2$

$=\frac{A^2}{4}\{{\mathrm{<figure-callout\; id="2"\; label="cos"\; filenames="A20061010787500562.png,A20061010787500601.png"\; state="\{\{state\}\}">cos</figure-callout>}}^2\mathrm{\&phi;}\left(t\right)+{\mathrm{<figure-callout\; id="2"\; label="sin"\; filenames="A20061010787500562.png,A20061010787500601.png"\; state="\{\{state\}\}">sin</figure-callout>}}^2\mathrm{\&phi;}\left(t\right)\}$

$=\frac{A^2}{4}---\left(3\right)$

When (II) receiving the standard wave (Germany) of 77.5kHz

In addition, when receiving the standard wave of 77.5kHz, multistage frequency-conversion circuit 623 is by 5 grades of basic circuit 624[1], 624[2] .., 624[5] constitute.Fig. 7 A～Fig. 7 D, Fig. 8 A～Fig. 8 B, Fig. 9 is the figure of appearance that represents to be used to illustrate the frequency spectrum of the reception action under this situation with image mode.

At first, at elementary basic circuit 624[1] in, respectively from the received signal of RF amplifying circuit 622 input 77.5kHz, from frequency dividing circuit 625 inputs the 32.768kHz as reference frequency signal bs is carried out the signal g1 of the 65.536kHz that 2 times of amplifications obtain.Then, as shown in Figure 7, by frequency mixer 6241, the received signal of the synthetic 77.5kHz of multiplication and the signal g1 of 65.536kHz, as both signal of 11.964kHz of difference of frequency by filtering circuit 6242 as basic circuit 624[1] output signal output.At this moment, basic circuit 624[1] can be considered as in by frequency band, comprising BPF as the 77.5kHz of input signal of equal valuely.

Basic circuit 624[2 in subordinate] in, respectively from the basic circuit 624[1 of prime] signal of input 11964Hz, from the signal g4 of frequency dividing circuit 625 inputs four frequency divisions as the 8192Hz of the 32768Hz of reference frequency signal bs.Then, shown in Fig. 7 B, the signal of the synthetic 11964Hz of multiplication and the signal g4 of 8192Hz, as both signal of 3772Hz of difference of frequency by filtering circuit 6242 as basic circuit 624[2] output signal output.At this moment, basic circuit 624[2] can be considered as in by frequency band, comprising BPF as the 8192Hz of input signal of equal valuely, should become than basic circuit 624[1 by bandwidth] equivalence BPF pass through narrow bandwidth.

Basic circuit 624[3 in its subordinate] in, respectively from the basic circuit 624[2 of prime] signal of input 3772Hz, from the signal g5 of frequency dividing circuit 625 inputs eight frequency divisions as the 4096Hz of the 32768Hz of reference frequency signal.Then, shown in Fig. 7 C, the signal of the synthetic 3372Hz of multiplication and the signal g5 of 4096Hz, as both signal of 324Hz of difference of frequency by filtering circuit 6242 as this basic circuit 624[3] output signal output.At this moment, basic circuit 624[3] can be considered as in by frequency band, comprising BPF as the 3272Hz of input signal of equal valuely, should become than basic circuit 624[2 by bandwidth] equivalence BPF pass through narrow bandwidth.

Basic circuit 624[4 in its subordinate] in, respectively from the basic circuit 624[3 of prime] signal of input 324Hz, from the signal g9 of frequency dividing circuit 625 inputs 128 frequency divisions as the 256Hz of the 32768Hz of reference frequency signal.Then, shown in Fig. 7 D, the signal of the synthetic 324Hz of multiplication and the signal g9 of 256Hz, as both signal of 68Hz of difference of frequency by filtering circuit 6242 backs as basic circuit 624[4] output signal output.At this moment, basic circuit 624[4] can be considered as in by frequency band, comprising BPF as the 324Hz of input signal of equal valuely, should become than basic circuit 624[3 by bandwidth] equivalence BPF pass through narrow bandwidth.

Basic circuit 624[5 in final level] in, respectively from the basic circuit 624[4 of prime] signal of input 68Hz, from the signal g11 of frequency dividing circuit 625 inputs 512 frequency divisions as the 64Hz of the 32768Hz of reference frequency signal.Then, shown in Fig. 8 A, the signal of the synthetic 68Hz of multiplication and the signal g11 of 64Hz, as both signal of 4Hz of difference of frequency by filtering circuit 6242 backs as basic circuit 624[5] output signal output.This output signal becomes the output signal a of multistage frequency-conversion circuit 623.At this moment, basic circuit 624[5] can be considered as in by frequency band, comprising BPF as the 68Hz of input signal of equal valuely, it becomes than basic circuit 624[4 by bandwidth] equivalence BPF pass through narrow bandwidth.

Then, in detecting circuit 626, respectively from the signal a of multistage frequency-conversion circuit 623 input 4Hz, from the signal g15 of the 4Hz of frequency dividing circuit 625 inputs 8182 frequency divisions after as reference frequency signal 32768Hz as signal f and carry out detection.That is, shown in Fig. 8 B, the signal a of the synthetic 4Hz of multiplication and the signal f of 4Hz, generation is as the signal of the 0Hz of the difference of both frequencies.This signal becomes from the rectified signal d of this detecting circuit 626 outputs, at this moment, detecting circuit 626 can be considered as comprising the BPF as the 4Hz of input signal of equal valuely in by frequency band, it becomes than basic circuit 624[5 by bandwidth] equivalence BPF pass through narrow bandwidth.

Therefore, as radio wave receiver 620 all with connect 6 grades BPF equivalence, as shown in Figure 9, can be considered as is being that 77.5kHz is the BPF of the utmost point narrow-band at center as receive frequency.The reception of expression during the acceptance criteria electric wave shown in Fig. 7 A～Fig. 7 D, Fig. 8 A～Fig. 8 B moved in Fig. 9 when being considered as the BPF of utmost point narrow-band or the figure when regarding comprehensive BPF as.

In addition here, because from the basic circuit 624[5 of final level] frequency of the signal a of output is 4Hz, and is extremely low, so also can be by 4 grades of basic circuit 624[1], 624[2] .., 624[4] form multistage frequency-conversion circuit 623.In this case, to detecting circuit 626 respectively from the signal a of multistage frequency-conversion circuit 623 input 68Hz, from the signal f of frequency dividing circuit 625 input 64Hz and carry out detection, output is as the rectified signal d of the 4Hz of both differences, but because by using the amplitude component of 626 detecting signals of detecting circuit, so be that the regeneration of received signal is no problem for detection.

Figure 10 be the expression various countries when the different standard wave of receive frequency, to each basic circuit 624 of multistage frequency-conversion circuit 623 table from the output signal frequency of the frequency of the signal g of frequency dividing circuit 625 inputs and corresponding basic circuit 624.In the figure, China's (68.5kHz) situation separately Switzerland (70kHz), 5 Germany (77.5kHz), 4 Japan (60kHz), 3 expression 1) Japan (40kHz), 2)))).

For example, 2) during Japan (60kHz), multistage frequency-conversion circuit 623 is by 5 grades of basic circuit 624[1], 624[2] .., 624[5] form.So, at elementary basic circuit 624[1] in, the received signal of the synthetic 60kHz of multiplication and the signal g1 of 65.536kHz are transformed to the signal as the 5536Hz of difference frequency.Then, at basic circuit 624[2] in, multiplication synthesizes the signal of this 5536Hz and the signal g4 of 8192Hz, is transformed to the signal of 2656Hz.At secondary basic circuit 624[3] in, multiplication synthesizes the signal of this 2656Hz and the signal g6 of 2048Hz, is transformed to the signal of 608Hz.Then, at basic circuit 624[4] in, multiplication synthesizes the received signal of this 608Hz and the signal g8 of 512Hz, is transformed to the signal of 96Hz.At basic circuit 624[5] in, multiplication synthesizes the received signal of this 96Hz and the signal g10 of 128Hz, is transformed to the signal of 32Hz.Then, as signal f, carry out detection to the signal g12 of the signal of detecting circuit 626 input 32Hz and 32Hz.

Like this, a plurality of basic circuits 624 that the n level by being connected in series that multistage frequency-conversion circuit 623 has is formed make the standard wave that receives from receiving antenna 621 transform to low frequency in turn according to the signal g from frequency dividing circuit 625 inputs.Then, the signal from multistage frequency-conversion circuit 623 outputs passes through detecting circuit 626 detections.

Thus, need be in the radio wave receiver of existing superhet mode needed local oscillator circuit or PLL circuit, can realize stable reception, and lower as all power consumption of device.In addition, be processing by carry out with a plurality of translation circuits according to the frequency of fractional frequency signal the frequency transformation of received signal, can realize high-precision reception.Have again, because can constitute each translation circuit of conversion frequency, so can dwindle chip size according to the LSIization of using CPOS with simple circuit component.

The following describes the specific embodiment of the radio wave receiver 620 in the present embodiment.

[first embodiment]

First embodiment at first is described.

As mentioned above, multistage frequency-conversion circuit 623 constitutes by a plurality of basic circuits 624 that are connected in series, these basic circuits 624, be in which level according to the standard electric wave frequency that receives or this basic circuit 624 in multistage frequency-conversion circuit 623, that sets in filtering circuit 6242 passes through the bandwidth difference.Therefore, in first embodiment, each basic circuit 624 of following formation.

Figure 11 A is the synoptic diagram of the circuit structure of the basic circuit 624A among first embodiment.According to this figure, basic circuit 624A has frequency mixer 6241, filtering circuit 6242A, amplifier 6243.Filtering circuit 6242A has resistor R 1, R2, capacitor C that is connected in series and the switch SW 1 that is connected in parallel with resistor R 2.Switch SW 1 from the bandwidth switching signal SW1-1 of the CPU100 switching of passing through bandwidth input, that indicate this filtering circuit 6242A, is controlled on/off (connecting/disconnect) in accordance with for example.

In this basic circuit 624A, when switch SW 1 is connected, be output by resistor R 1 and switch SW 1 from the signal of frequency mixer 624 to filtering circuit 6242A input, filtering circuit 6242A plays a role as the RC wave filter of being made up of resistor R 1 and capacitor C.On the contrary, when switch SW 1 disconnected, the signal of importing to filtering circuit 6242A was output by resistor R 1, R2, and filtering circuit 6242A plays a role as the RC wave filter of being made up of resistor R 1, R2 and capacitor C.That is,, the time constant of filtering circuit 6242A is changed, promptly switch and pass through bandwidth by using the on/off of the bandwidth switching signal change-over switch SW1 that imports.

Here, filtering circuit 6242A pass through bandwidth also can be set at blocking-up to the input signal of this basic circuit 624 and signal g with frequency and its difference frequency is passed through.Therefore, the a plurality of basic circuit 624A of same structure of being connected in series constitute multistage frequency-conversion circuit 623, for example, can carry out LSIization, realize easy and general radio wave receiver 620 by set the bandwidth of passing through of each basic circuit 624 from the bandwidth switching signal of CPU100 input.

In addition, also can be filtering circuit 6242A as having the structure that two resistor R 1, R2 is not only arranged but also the resistor R more than three or three is arranged.Figure 11 B is the figure of circuit structure one example that expression has the basic circuit 624A-1 of the resistor R more than three or three.According to Figure 11 B, in basic circuit 624A-1, filtering circuit 6242A-1 have resistor R 1, the resistor R 2a that is connected in parallel mutually, R2b, R2c ..., capacitor C, with resistor R 2a, R2b, R2c ... the switch SW 6 that is connected in parallel, with resistor R 2a, R2b, R2c .. each switch SW 6a that is connected in series, SW6b, SW6c ....Each switch SW 6, SW6a, SW6b, SW6c ..., for example by from the switch-over control signal of CPU100 input (SW6-1, SW6a-2, SW6b-3, SW6c-4 ...) the control on/off.Thus, the bandwidth of passing through of ground setting filtering circuit 6242A-1 can switched more than 3 grades or 3 grades.

According to the invention of first embodiment, have the wave filter of each translation circuit that is connected in series, can a plurality ofly pass through bandwidth from what be predetermined by selecting the bandwidth one ground to switch.Therefore, be same structure by making each translation circuit, the frequency of corresponding for example received signal, a plurality of translation circuit that is connected in series is connecting, and which rank of switches by bandwidth, can constitute general apparatus structure.

[second embodiment]

The following describes second embodiment.

Second embodiment is the embodiment when making radio wave receiver 620 can receive the so-called multiband of standard wave of a plurality of different frequencies.

Figure 12 is the block diagram of the structure of the radio wave receiver 620B among expression second embodiment.According to this figure, radio wave receiver 620B has receiving antenna 621, RF amplifying circuit 622, multistage frequency-conversion circuit 623B, frequency dividing circuit 625B, detecting circuit 626 and agc circuit 627.

Here, for becoming and frame, omit its explanation in " function, structure " illustrated in fig. 2 identical " function, structure ".

Multistage frequency-conversion circuit 623B is by the basic circuit 624[1 of a plurality of N levels that are connected in series], 624[2] ..., 624[N] form.And at each basic circuit 624[1], 624[2] ..., 624[N] in, respectively from frequency dividing circuit 625B input signal g1, g2 .., gN, and for example use/do not use switching signal sf from CPU100 input.

Frequency dividing circuit 625B, output respectively with 2,1,1/2,1/4 ..., 1/2 ^(N-2)The frequency dividing ratio frequency division of (N is an integer) from signal g1, the g2 of the reference frequency signal bs of transtation mission circuit portion 900 input ..., gN and signal f.In addition, more accurate theory, in a single day frequency dividing circuit 625B is carrying out carrying out frequency division after 2 times of amplifications to reference frequency signal bs, but simple for explanation, describes as the frequency division basic frequency.

Here, the progression N of multistage frequency-conversion circuit 623B is corresponding with the frequency of reference frequency signal bs.That is, for example when reference frequency signal bs is 32.768kHz, multistage frequency-conversion circuit 623B is by 16 grades that are connected in series basic circuit 624[1], 624[2] ..., 624[16] form.So, from frequency dividing circuit 625, shown in the table of Figure 10, this 32768Hz respectively with 2,1,1/2,1/4 ..., 1/8182,1/16384 frequency dividing ratio frequency division, output 65768,32768,16384,8192 ..., 4, signal g1, the g2 of 2Hz ..., g16, these signals g1, g2 ..., g16 imports basic circuit 624[1 respectively], 624[2] .., 624[16].

In addition, the so-called use/do not use switching signal is to specify basic circuit 624[1], 624[2] ..., 624[16] use/obsolete signal.So-called " use " basic circuit 624[1], 624[2] ..., 624[N], be meant in this basic circuit 624, synthesize from the signal g of frequency dividing circuit 625 inputs at input signal comultiplication from prime, frequency is reduced, promptly carry out frequency transformation, so-called " not using " is meant for input signal and do not carry out frequency transformation output.What constitute multistage frequency-conversion circuit 623B respectively imports basic circuit 624[1], 624[2] ..., 624[N] be " use " or " not using ", by the standard electric wave frequency decision that receives.

For example, (A) when receiving the standard wave of 40kHz, as reference Fig. 5 A～Fig. 5 D, Fig. 6 explanation, import 3 basic circuit 624[1 of total of signal g7 of the 1024Hz of the signal g4 of 8192Hz of signal g2,4 frequency division reference frequency signal bs as the 32768Hz of reference frequency signal bs and 32 frequency division reference frequency signal bs respectively], 624[2], 624[3] by " uses ", this basic circuit 624[4 in addition], 624[5] .., 624[N] become " not using ".

In addition, (B) when receiving the standard wave of 77.5kHz, as reference Fig. 7 A～Fig. 7 D, Fig. 8 A～Fig. 8 B, Fig. 9 explanation, import 2 times of signal g1 that amplify the 65536Hz behind the reference frequency signal bs respectively, carry out the 8192Hz behind 4 frequency divisions signal g4, carry out the signal g5 of the 4096Hz behind 8 frequency divisions, the 64Hz after carrying out the signal g9 of the 256Hz behind 128 frequency divisions and carrying out 512 frequency divisions 5 basic circuits of total 624 of signal g11 by " uses ", this basic circuit 624 in addition " does not use ".

Figure 13 A is the basic circuit 624[1 that expression constitutes the multistage frequency-conversion circuit 623B among second embodiment], 624[2] ..., 624[N] among one the figure of basic circuit 624B of circuit structure.According to Figure 13 A, basic circuit 624B has switch SW 2, SW3, frequency mixer 6241, filtering circuit 6242 and amplifier 6243.

Switch SW 2 is arranged on the prime of frequency mixer 6241, abides by use from the CPU100 input/do not use switch-over control signal sf, among splicing ear a, the b any one.Switch SW 3 is arranged on the back level of amplifier 6243, abides by the use of input/do not use switch-over control signal sf, among splicing ear a, the b any one.

Figure 13 B is the table of the relation of the expression connection status of use/not using switching signal sf and switch SW 2, SW3.According to Figure 13 B, when switching signal is specified " use ", switch SW 2 splicing ear a, switch SW 3 splicing ear a.Therefore, input signal is exported as the output signal of this basic circuit 624B by filtering circuit 6242 and amplifier 6243 by frequency mixer 6241 with from the synthetic back of the signal g multiplication conversion frequency that frequency dividing circuit 625 is imported.That is, this basic circuit 624B becomes the state of " use ".

In addition, when use/not using switching signal sf to specify " not using ", switch SW 2 splicing ear b, switch SW 3 splicing ear b.Therefore, not conversion of frequency input signal, former state is as the output signal output of this basic circuit 624B.That is, this basic circuit 624B becomes the state of " not using ".

Like this,, can constitute multistage frequency-conversion circuit 623B, the use by switching each basic circuit 624B from the use of outside input/do not use switching signal sf/do not use with a plurality of basic circuit 624B of same structure according to second embodiment.Therefore, the frequency setting of the standard wave that receives by correspondence uses/does not use switching signal sf, can realize general radio wave receiver 620, and wherein only use the basic circuit 624B of necessity, and do not use other basic circuit 624B.

[the 3rd embodiment]

The following describes the 3rd embodiment.

The 3rd embodiment, identical with above-mentioned second embodiment, the embodiment when being multiband radio wave receiver 620, the point of basic circuit 624C that the basic circuit 624B of Figure 13 A is replaced into Figure 14 A is different with second embodiment.

Figure 14 A is the figure of the circuit structure of the basic circuit 624C among expression the 3rd embodiment.According to Figure 14 A, basic circuit 624C has frequency mixer 6241, filtering circuit 6242C, amplifier 6243 and switch SW 4.

Switch SW 4 is arranged between frequency mixer 6241 and the frequency dividing circuit 625, abides by use from the CPU100 input/do not use switch-over control signal sf, control on/off.

Filtering circuit 6242C has resistor R 1, R2, capacitor C that is connected in series and the switch SW 5 that is connected in parallel with resistor R 2.Here, switch SW 5 is abideed by the use of input/do not use switching signal control on/off.

Figure 14 B is the figure of relation that the connection status of switching signal sf and switch SW 5 use/is not used in expression.According to Figure 14 B, when use/not using switching signal sf to specify " use ", switch SW 4 is connected, and switch SW 5 disconnects.Therefore, input signal is exported as output signal by frequency mixer 6241 with from the synthetic back of the signal g multiplication conversion frequency that frequency dividing circuit 625 is imported.In addition this moment, filtering circuit 6242C plays a role as having the low-pass filter that passes through bandwidth corresponding with the capability value of each resistance value of resistor R 1, R2 and capacitor C.That is, this basic circuit 624 becomes the state of " use ".

In addition, when use/not using switching signal sf to specify " not using ", switch SW 4 disconnects, and switch SW 5 is connected.Therefore, because the signal g that comes self frequency-dividing circuit 625 input mixer 6241 not, so input signal does not carry out frequency transformation, 6242C exports as output signal by filtering circuit.That is, this basic circuit 624 becomes the state of " not using ".This moment is minimum because of the resistance value of resistor R 1 though filtering circuit 6242C becomes the RC wave filter of being made up of resistor R 1 and capacitor C in addition, so do not play a role as wave filter in fact.

Like this,, can constitute multistage frequency-conversion circuit 623, by switch the use of each basic circuit 624C/do not use from the use of outside input/do not use switching signal with a plurality of basic circuit 624C of same structure according to the 3rd embodiment.Therefore, the frequency setting of the standard wave that receives by correspondence uses/does not use switching signal sf, can realize general radio wave receiver 620, wherein only uses the basic circuit 624C of necessity, and does not use other basic circuit 624C.

[the 4th embodiment]

The following describes the 4th embodiment.

Figure 15 is the block diagram of the schematic configuration of the radio wave receiver 620D among expression the 4th embodiment.According to this figure, radio wave receiver 620D has receiving antenna 621, RF amplifying circuit 622, multistage frequency-conversion circuit 623, frequency dividing circuit 625D, detecting circuit 626, agc circuit 627 and switches set 628.

In addition, about becoming and frame, omit its explanation in " function, structure " illustrated in fig. 2 identical " function, structure ".

Frequency dividing circuit 625D, have output respectively with 2,1,1/2,1/4 ..., 1/2 ^(m-2)The frequency dividing ratio frequency division of (m is an integer) from signal g1, the g2 of the reference frequency signal bs of transtation mission circuit portion 900 input, g3 ..., a plurality of lead-out terminal t1 of gm, t2, t3 ..., tm.

Switches set 628 is by the basic circuit 624[1 at multistage frequency-conversion circuit 623], 624[2] ..., 624[n] each and frequency dividing circuit 625 between be provided with a plurality of switch S 1, S2 ..., Sn and the switch S n+1 that is provided with between detecting circuit 626 and frequency dividing circuit 625 form.These switch S 1, S2 ..., Sn+1 for example abides by respectively from the selection signal st of CPU100 input, connect frequency dividing circuit 625 lead-out terminal t1, t2, t3 ..., among the tm certain.

As mentioned above, when the radio wave receiver 620 of multibandization, import the frequency difference of signal g of each basic circuit 624 of multistage frequency-conversion circuit 623 according to the standard electric wave frequency that receives.Therefore, as the 4th embodiment, the connection of each switch S of the switches set 628 that is provided with between each basic circuit 624 and detecting circuit 626 and frequency dividing circuit 625 is switched by the selection signal st from the outside input, can switch each basic circuit 624[1 of input thus], 624[2] ..., 624[n] the frequency of signal g, can realize the general apparatus structure of the radio wave receiver 620 of multibandization.

In addition, by each translation circuit as identical structure, for example the frequency of corresponding received signal or corresponding translation circuit be in a plurality of translation circuits that are connected in series which the level switch the fractional frequency signal of input, can become general apparatus structure.

[the 5th embodiment]

The following describes the 5th embodiment.

As mentioned above, in each basic circuit 624 of multistage frequency-conversion circuit 623, carry out the frequency transformation (down conversion) of input signal, result from this frequency transformation and produce the problem of picture signal but exist according to fractional frequency signal g.

For example, when the signal of receive frequency ω, if the fractional frequency signal of frequencies omega 1 is carried out frequency transformation as local signal, then shown in Figure 17 A, outside the signal (wishing received signal) of the frequencies omega that this hope receives, also being received on the frequency axis with frequencies omega 1 be the signal (picture signal 1) of the frequency of center and the position of wishing the received signal symmetry.

Then, the fractional frequency signal of frequencies omega 2 further carried out frequency transformation as local signal after, shown in Figure 17 B, carry out frequency transformation for each of wishing received signal and picture signal 1.Promptly according to for the frequency transformation of wishing received signal, also receive with frequencies omega 2 be the center, with the signal (picture signal 2) of wishing the frequency of acknowledge(ment) signal symmetric position.In addition, according to frequency transformation, also accept with frequencies omega 2 to picture signal 1 _iBe the center, with the signal (picture signal 3) of the frequency of picture signal 1 symmetric position.In addition, frequencies omega 2 _iBe to be the frequency of center and frequencies omega 2 symmetric positions with frequencies omega 1.

That is,, receive one and wish that received signal and 3 picture signals 1～3 add up to 4 signals by 2 grades of frequency transformations.Therefore, when carrying out the frequency transformation of n level, wishing outside the received signal, also becoming in addition and will receive (2 ⁿ-1) individual picture signal.

Therefore, in the 5th embodiment, for removing this picture signal, each basic circuit 624 of following formation.Figure 18 is the figure of the circuit structure of the basic circuit 624F among expression the 5th embodiment, according to this figure, basic circuit 624F has phase-shifter 6244, frequency mixer 6245a, 6245b, phase- shift circuit 6246a, 6246b, adder-subtractor 6247 and filtering circuit 6248.

Phase-shifter 6244 makes from the signal g of frequency dividing circuit 625 inputs and carries out 90 degree phase shifts, as signal g _iOutput.Frequency mixer 6245a multiplication synthetic input signal and signal g to basic circuit 624F are as signal f _1IOutput.Frequency mixer 6245b, synthetic input signal of multiplication and the signal g that imports from phase-shifter 6244 _i, as signal f _1QOutput.

Phase-shift circuit 6246a, phase shift is from the signal f of frequency mixer 6245a input _1I, as signal f _2IOutput.Phase-shift circuit 6246b, phase shift is from the signal f of frequency mixer 6245b input _1Q, as signal f _2QOutput.Here, phase- shift circuit 6246a, 6246b are constituted as and make separately phase shift difference of this phase- shift circuit 6246a, 6246b (phase shift angle poor) become 90 degree (pi/2).For example constitute, at phase-shift circuit 6246a phase shift signalling f _1IWhen " α ", phase-shift circuit 6246b phase shift signalling f _1Q" α-pi/2 ".

Figure 19 represents the circuit structure of phase-shift circuit 6246a, 6246b.As shown in the drawing, phase- shift circuit 6246a, 6246b are same structures, and (All Pass Filter: all-pass filter) 6247 form by 2 grades of APF that are connected in series.APF6247 is the wave filter of variation phase only, has operational amplifier OP, resistor R 1, R2, R3, capacitor C1.By the output stage of the value of resistor R 1, R2 decision APF6247, by the phase-shift phase of the value decision APF6247 of resistor R 3 and capacitor C1.Because can move on to 180 degree mutually, so by connecting two-stage APF6247, phase- shift circuit 6246a, 6246b can move on to 360 degree mutually with an APF6247.

In Figure 18, adder-subtractor 6247, for example correspondence is synthesized or is subtracted each other and synthesize the signal f that imports from phase-shift circuit 6246a from the addition with difference switching signal wsk of CPU100 input _2IWith signal f from phase-shift circuit 6246b input _2Q, as signal f ₃Output.

Filtering circuit 6248, be LPF (Low Pass Filter: low-pass filter), for signal f from adder-subtractor 6247 input ₃, the frequency of the low-frequency range of regulation is passed through, the frequency content beyond the blocking-up scope.This filtering circuit 6248 has resistor R 4, R5, capacitor C2 that is connected in series and the switch SW 1 that is connected in parallel with resistor R 4.Switch SW 1 is abideed by the time constant switching signal tk control on/off of for example importing from CPU100.By the on/off of change-over switch SW1, the time constant of filtering circuit 6248 changes, and promptly is switched by bandwidth.Become the output signal of basic circuit 624F from the output signal of this filtering circuit 6248.

In basic circuit 624F, generate I, the Q signal of input signal, the Q signal of generation is for I signal phase shift 90 degree, by the synthetic picture signal of removing.Figure 20 A, Figure 20 B are the figure that is used to illustrate the principle of removing by the picture signal of basic circuit 624F, establish vertically to real axis (I component), direction in oblique are the imaginary axis (Q component), and the notion of the phase shift relation of received signal and picture signal is wished in expression.In addition, solid line represents to wish received signal, dotted line presentation video signal.

Shown in Figure 20 A, wish each of received signal and picture signal, its I, Q signal are mutually orthogonal.In addition, received signal and picture signal, because the frequency that is positioned at fractional frequency signal g (local signal) is centrosymmetric position,, wish that each Q signal of received signal and picture signal is anti-phase so wish each I signal homophase of received signal and picture signal on frequency axis.

So, if 90 degree phase shift Q signals then shown in Figure 20 B, are wished each Q signal phase shift 90 degree of received signal and picture signal, wishing that the I of received signal, Q signal become homophase, the I of picture signal, Q signal become anti-phase.Therefore, by synthetic dephased I, Q signal, the picture signal composition is cancelled, and only takes out and wishes the received signal composition.

Specifically, in basic circuit 624F, by frequency mixer 6245a, 6245b, input signal is by signal (signal g, the g of mutually orthogonal _i) carry out frequency transformation, and generate I, Q signal (signal f _1I, f _1Q).Then, I, Q signal (the signal f that generates by phase- shift circuit 6246a, 6246b phase shift _2I, f _2Q), by adding/subtract, remove picture signal with adder-subtractor 6247, only received signal is wished in output.

Like this, according to the 5th embodiment, each basic circuit 624F is each each signal that carries out after the frequency transformation makes phase shift difference become the such phase shift of 90 degree to the I of input signal, Q signal with signal g, constitute by addition is synthetic, can remove the picture signal composition that generates by frequency transformation thus.

Promptly, the basic circuit 624F that is connected in series, input signal, with the signal multiplication behind the signal g that imports from frequency dividing circuit 625 and 90 this signal of the degree phase shift g, signal after this is multiplied each other makes the phase shift difference of each signal that multiplies each other for this become the such phase shift of 90 degree, exports as figure signal after the added/subtracted.Thus, become the such phase shift of 90 degree,, can remove the picture signal composition that produces by frequency transformation by added/subtracted by each of the I behind the suppressing out-of-band interference, Q signal being made phase shift difference.

[other embodiment]

Have again,, also can make up above-mentioned first～the 4th embodiment as other embodiment.

[effect, effect]

As mentioned above, according to the Wave timepiece 1 of present embodiment, the received signal that receiving antenna 621 receives, in multistage frequency-conversion circuit 623, by each basic circuit 624 that is connected in series, synthetic with signal g multiplication with the frequency dividing ratio frequency division reference frequency signal bs of regulation, reduce frequency gradually.Then, in detecting circuit 626, the signal a that reduces according to this frequency carries out detection, output rectified signal d.Here, as reference frequency signal bs, because the oscillator signal that uses the timing that generates by oscillatory circuit portion 900 to use, so the local oscillator circuit that need in the radio wave receiver of existing superhet (super heterodyne) mode, need not.That is, because do not need the PLL circuit, thus can realize not producing because power supply changes or the reception of the high stable of the frequency variation that power source ON/OFF causes, and, can lower consumption electric power as device integral body.In addition, by received signal and fractional frequency signal multiplication are synthesized the multistage frequency transformation that reduces frequency gradually, can realize high-precision reception.Have again, though because be multi-level pmultistage circuit and circuit scale is increased, because each basic circuit 624 can so can realize large scale integrated circuitization, dwindle chip size with simple circuit component formation.

[variation]

In addition, can use embodiments of the present invention, be not limited to above-mentioned embodiment, in the scope that does not break away from main idea of the present invention, can suitably change.

In the above-described embodiment, detecting circuit 626, carry out detection according to signal a from multistage frequency-conversion circuit 623 outputs, output rectified signal d, but the basic circuit 624 of the final level of multistage frequency-conversion circuit 623 also can be also used as this detecting circuit 626.

Figure 16 is the block diagram of an example of structure of the radio wave receiver 623E of this situation of expression.According to this figure, radio wave receiver 623E has the basic circuit 624[1 by (n+1) that be connected in series level], 624[2] ..., 624[n], 624[n+1] the multistage frequency-conversion circuit 623E that forms, and, do not have detecting circuit 626 this point, different with the structure of radio wave receiver 623 shown in Figure 2.

Basic circuit 624[n+1 in the final level of multistage frequency-conversion circuit 623] in, respectively from the basic circuit 624[n of prime] input signal a, from frequency dividing circuit 625 inputs as with the signal of the frequency dividing ratio frequency division reference frequency signal bs of regulation, with the signal f of signal a same frequency.Then, basic circuit 624[n+1], the signal d of the difference frequency of output signal a and signal f, but because signal a and signal f are same frequencys, so this signal d becomes 0Hz.That is, from the output signal d of multistage frequency-conversion circuit 623, become the rectified signal of rectified signal a, i.e. the signal of regenerative reception signal.

In addition, the structure as comprise detecting circuit 626 in multistage frequency-conversion circuit 623 also can constitute radio wave receiver 620 as shown in figure 21.

Figure 21 is the block diagram of an example of structure of the radio wave receiver 620G of this situation of expression.This radio wave receiver 620G has receiving antenna 621, RF amplifying circuit 622, multistage frequency-conversion circuit 629G, frequency dividing circuit 625G, agc circuit 627 and switches set 628G to remove picture signal with the identical principle of above-mentioned the 5th embodiment.In addition, about becoming and frame, omit its explanation in " function, structure " illustrated in fig. 2 identical " function, structure ".

Frequency dividing circuit 625G, respectively with 2,1,1/2,1/4 ..., the frequency dividing ratio frequency division of 1/2 (m-2) (m is an integer) is from the reference frequency signal bs of transtation mission circuit portion 900 inputs, signal g1, g2 behind the frequency division, g3 ..., gm output to respectively lead-out terminal t1, t2, t3 ..., tm.

Switches set 628G is made up of a plurality of switch S 1～S3 that are provided with between multistage frequency-conversion circuit 629G and frequency dividing circuit 625G.These switch S 1～S3 for example abide by respectively from lead-out terminal t1, the t2 of the selection signal ss of CPU100 input and frequency dividing circuit 625G, t3 ..., some connections among the tm.Then, the signal g to each lead-out terminal t that is connected output with switch S 1～S3 is input to multistage frequency-conversion circuit 629G as signal k1～k3.

Multistage frequency-conversion circuit 629G the input signal from RF amplifying circuit 622, according to being transformed to low frequency by switches set 628G gradually from signal k1～k3 that frequency dividing circuit 625G imports, exports as signal d.

Figure 22 represents the circuit structure of multistage frequency-conversion circuit 629G.According to this figure, multistage frequency-conversion circuit 629G has phase-shifter 6291a～6291c, frequency mixer 6292a～6292l, wave filter 6293a～6293h, adder-subtractor 6294a～6294d and totalizer 6295.

Frequency mixer 6292a, multiplication synthetic input signal and signal k1 to multistage frequency-conversion circuit 629G are as signal f _A1IOutput.Wave filter 6293a is LPF, for the signal f from frequency mixer 6292a input _A1I, the frequency of the low-frequency range of the difference frequency that comprises input signal and signal k1 is passed through, blocking-up is exported after comprising extraneous frequency content with frequency.

Phase-shifter 6291a spends the signal k1 phase shift 90 of input, exports as signal k4.Frequency mixer 6292b, synthetic input signal of multiplication and the signal k4 that imports from phase-shifter 6291a are as signal f _A1QOutput.Wave filter 6293b is LPF, for the signal f from frequency mixer 6292b input _A1Q, the frequency of the low-frequency range of the difference frequency that comprises input signal and signal k1 is passed through, blocking-up is exported after comprising extraneous frequency content with frequency.

Frequency mixer 6292c, multiplication is synthetic by the signal f of wave filter 6293a from frequency mixer 6292a input _A1IWith signal k2, as signal f _B1IOutput.Wave filter 6293c is LPF, for the signal f from frequency mixer 6292c input _A1I, make to comprise signal f _A1IPass through with the frequency of the low-frequency range of the difference frequency of signal k2, blocking-up is exported after comprising extraneous frequency content with frequency.

Phase-shifter 6291b spends the signal k2 phase shift 90 of input, exports as signal k5.Frequency mixer 6292d, multiplication is synthetic by the signal f of wave filter 6293a from frequency mixer 6292a input _A1IWith signal k5, as signal f from phase-shifter 6291b input _B1QOutput.Wave filter 6293d is LPF, for the signal f from frequency mixer 6292d input _B1Q, make to comprise input signal f _A1IPass through with the frequency of the low-frequency range of the difference frequency of signal k2, blocking-up is exported after comprising extraneous frequency content with frequency.

Frequency mixer 6292e, multiplication is synthetic by the signal f of wave filter 6293b from frequency mixer 6292b input _A1QWith signal k2, as signal f _B2IOutput.Wave filter 6293e is LPF, for the signal f from frequency mixer 6292e input _B2I, make to comprise signal f _A1QPass through with the frequency of the low-frequency range of the difference frequency of signal k2, blocking-up is exported after comprising extraneous frequency content with frequency.

Frequency mixer 6292f, multiplication is synthetic by the signal f of wave filter 6293b from frequency mixer 6292b input _A1QWith signal k5, as signal f from phase-shifter 6291b input _B2QOutput.Wave filter 6293f is LPF, for the signal f from frequency mixer 6292f input _B2Q, make to comprise signal f _A1QPass through with the frequency of the low-frequency range of the difference frequency of signal k2, blocking-up is exported after comprising extraneous frequency content with frequency.

Adder-subtractor 6294a abides by the addition of importing with difference switching signal 1 (wsk1) and synthesizes or subtract each other and synthesize the signal f that imports from frequency mixer 6292c by wave filter 6293c _B1I, with by the signal f of wave filter 6293f from frequency mixer 6292f input _B2QBack output.With differing from switching signal 1 (wsk1) is the signal of specifying the movement content (adding/subtract) of adder-subtractor 6294a, for example imports from CPU100.So, adder-subtractor 6294a, by and difference switching signal 1 (wsk1) when specifying " adding ", addition composite signal f _B1IWith signal f _B2Q, as signal f _dOutput; When specifying " subtracting ", subtract each other composite signal f _B1IWith signal f _B2Q, as signal f _cOutput.

Adder-subtractor 6294b abides by the addition of importing with difference switching signal 2 (wsk2) and synthesizes or subtract each other and synthesize the signal f that imports from frequency mixer 6292d by wave filter 6293d _B1Q, with by the signal f of wave filter 6293e from frequency mixer 6292e input _B2IBack output.With differing from switching signal 2 (wsk2) is the signal of specifying the movement content of adder-subtractor 6294b, for example imports from CPU100.Adder-subtractor 6294b, by and difference switching signal 2 (wsk2) when specifying " adding ", addition composite signal f _B1QWith signal f _B2I, as signal f _gOutput; When specifying " subtracting ", subtract each other composite signal f _B1QWith signal f _B2I, as signal f _eOutput.

Frequency mixer 6292g, multiplication synthesize from exporting behind the input signal of adder-subtractor 6294a and the signal k3.At length say, from adder-subtractor 6294a input signal f _cThe time, multiplication synthesizes this signal f _cWith signal k3, as signal f _CI3Output is at input signal f _dThe time, multiplication synthesizes this signal f _dWith signal k3, as signal f _DI3Output.

Phase-shifter 6291c signal k3 phase shift 90 degree of input, exports as signal k6.Frequency mixer 6292h, multiplication synthesize the input signal from adder-subtractor 6294b and export behind the signal k6 of phase-shifter 6291c input.At length say, from adder-subtractor 6294b input signal f _eThe time, multiplication synthesizes this signal f _eWith signal k6, as signal f _EQ3Output; At input signal f _gThe time, multiplication synthesizes this signal f _gWith signal k6, as signal f _GQ3Output.

Frequency mixer 6292i exports behind synthetic input signal that comes from adder-subtractor 6294b of multiplication and the signal k3.At length say, from adder-subtractor 6294b input signal f _eThe time, multiplication synthesizes this signal f _eWith signal k3, as signal f _EI3Output; At input signal f _gThe time, multiplication synthesizes this signal f _gWith signal k3, as signal f _GI3Output.

Frequency mixer 6292j, multiplication synthesize the input signal from adder-subtractor 6294a and export behind the signal k6 of phase-shifter 6291c input.At length say, from adder-subtractor 6294a input signal f _cThe time, multiplication synthesizes this signal f _cWith signal k6, as signal f _CQ3Output; At input signal f _dThe time, multiplication synthesizes this signal f _dWith signal k6, as signal f _DQ3Output.

Adder-subtractor 6294c abides by the addition with difference switching signal 3 (wsk3) of input and synthesizes or subtract each other to synthesize and export behind the signal of frequency mixer 6292g, each input of 6292h.With differing from switching signal 3 (wsk3) is the signal of specifying the movement content of adder-subtractor 6294c, for example imports from CPU100.Adder-subtractor 6294c, by and difference switching signal 3 (wsk3) when specifying " adding ", synthetic signal (the signal f of addition from frequency mixer 6292g input _CI3Perhaps signal f _DI3) and from signal (the signal f of frequency mixer 6292h input _EQ3Perhaps signal f _GQ3), as signal f _hOutput; When specifying " subtracting ", subtract each other synthetic signal (signal f from frequency mixer 6292g input _CI3Perhaps signal f _DI3) and from signal (the signal f of frequency mixer 6292h input _EQ3Perhaps signal f _GQ3), as signal f _hOutput.

Wave filter 6293g is LPF, for the signal f from adder-subtractor 6294c input _h, the frequency that comprises from the low-frequency range of the difference frequency of the signal of frequency mixer 6292g, each output of 6292h is passed through, blocking-up is exported after comprising extraneous frequency content with frequency.

Adder-subtractor 6294d abides by the addition with difference switching signal 4 (wsk4) of input and synthesizes or subtract each other to synthesize and export behind the signal of frequency mixer 6292i, each input of 6292j.With differing from switching signal 4 (wsk4) is the signal of specifying the movement content of adder-subtractor 6294d, for example imports from CPU100.Adder-subtractor 6294d, by and difference switching signal 4 (wsk4) when specifying " adding ", synthetic signal (the signal f of addition from frequency mixer 6292i input _EI3Perhaps signal f _GI3) and from signal (the signal f of frequency mixer 6292j input _CQ3Perhaps signal f _DQ3), as signal f _iOutput; When specifying " subtracting ", subtract each other synthetic signal (signal f from frequency mixer 6292i input _EI3Perhaps signal f _GI3) and from signal (the signal f of frequency mixer 6292j input _CQ3Perhaps signal f _DQ3), as signal f _jOutput.

Wave filter 6293h is LPF, for the signal f from adder-subtractor 6294d input _i, making to comprise and pass through from each the frequency content of low-frequency range of difference frequency of output signal of frequency mixer 6292i, 6292j, blocking-up is exported after comprising extraneous frequency content with frequency.

Frequency mixer 6292k is square by the signal f of wave filter 6293g from adder-subtractor 6294c input _hBack output.Frequency mixer 6292l is square by the signal f of wave filter 6293h from adder-subtractor 6294d input _iBack output.Totalizer 6295 additions are synthetic from exporting behind each the input signal of frequency mixer 6292k, 6292l.From the signal of these totalizer 6295 outputs, become the output signal d of multistage frequency-conversion circuit 629G.

Specify the action of multistage frequency-conversion circuit 629G below.At first, establish to the input signal f of multistage frequency-conversion circuit 629G (ω) and provide with following formula (4a), the signal f ' of 90 these input signals of degree phase shift (ω) provide with following formula (4b).

[formula 4]

f(ω)＝cosωt

＝(e ^jωt+e ^-jωt)/2 …(4a)

f′(ω)＝sinωt

＝(e ^jωt-e ^-jωt)/2j …(4b)

In addition, establish signal k1～k3 and use following formula (5a)～(5c) provide respectively, the signal k4～k6 of 90 this signal of degree phase shift k1～k3 after each is with following formula (6a)～(6c) provide.

[formula 5]

k1＝cosω1t

＝(e ^jω1t+e ^-jω1t)/2 …(5a)

k2＝cosω2t

＝(e ^jω2t+e ^-jω2t)/2 …(5b)

k3＝cosω3t

＝(e ^jω3t+e ^-jω3t)/2 …(5c)

k4＝sinω1t

＝(e ^jω1t-e ^-jω1t)/2j …(6a)

k5＝sinω2t

＝(e ^jω2t-e ^-jω2t)/2j …(6b)

k6＝sinω3t

＝(e ^jω3t-e ^-jω3t)/2j …(6c)

In multistage frequency-conversion circuit 629G, at first,, carry out frequency transformation for the first order of input signal f (ω) by frequency mixer 6292a, 6292b.That is,,, generate signal f with signal k1 frequency transformation input signal f (ω) by frequency mixer 6292a _A1IThis signal f _A1IProvide with following formula (7).

[formula 6]

f _a1I＝(1/4)(e ^jωt+e ^-jωt)(e ^jω1t+e ^-jω1t)

＝(1/4)(e ^j(ω+ω1)t+e ^-j(ω+ω1)t+e ^j(ω-ω1)t+e ^-j(ω-ω1)t)

＝1/2(1/2)·{(e ^j(ω+ω1)t+e ^-j(ω+ω1)t)+(e ^j(ω-ω1)t+e ^-j(ω-ω1)t)}

＝f(ω+ω1)+f(ω-ω1) …(7)

In addition, by frequency mixer 6292b,, generate signal f with signal k4 frequency transformation input signal f (ω) _A1QThis signal f _A1QProvide with following formula (8).

[formula 7]

f _a1Q＝(1/4j)(e ^jωt+e ^-jωt)(e ^jω1t-e ^-jω1t)

＝(1/4j)(e ^j(ω+ω1)t+e ^-j(ω-ω1)t-e ^j(ω-ω1)t-e ^-j(ω+ω1)t)

＝1/2(1/2j)·{(e ^j(ω+ω1)t-e ^-j(ω+ω1)t)-(e ^j(ω-ω1)t-e ^-j(ω-ω1)t)}

＝f(ω+ω1-π/2)-f(ω-ω1-π/2) …(8)

Therefore, according to formula (7), (8), by the frequency transformation of this first order, generated frequency is respectively two signals of " ω+ω 1 ", " ω-ω 1 ".Figure 23 A, Figure 23 B are the figure of expression by the notion of the relation of two signals of this first order frequency transformation generation.Figure 23 A represents phase relation, and Figure 23 B represents frequency relation, and the signal of the frequency of representing with solid line " ω-ω 1 " is to wish received signal, and the signal of the frequency that dots " ω+ω 1 " is a picture signal.

In Figure 23 A, be illustrated in the signal f on the same frequency axis _A1IWith signal f _A1QPhase relation.Shown in Figure 23 A, signal f _A1IWith signal f _A1QQuadrature.In addition, signal f _A1IAs wishing each I signal of received signal and picture signal, both signal homophases.Signal f _A1QAs wishing each Q signal of received signal and picture signal, both signals are anti-phase mutually.In addition, shown in Figure 23 B, wish received signal and picture signal, on frequency axis, the frequencies omega 1 that is positioned at signal k1 is the position of the symmetry at center.

Then, by frequency mixer 6292c～6292f, carry out partial frequency transformation.Promptly, use signal k2 to signal f by frequency mixer 6292c _A1ICarry out frequency transformation, generate signal f _B1IThis signal f _B1IProvide with following formula (9).

[formula 8]

f _b1I＝[1/2(1/2)·{(e ^j(ω+ω1)t+e ^-j(ω+ω1)t)+(e ^j(ω-ω1)t+e ^-j(ω-ω1)t)·(e ^jω2t+e ^-jω2t)/2

＝1/4{(e ^{j(ω+ω1+ω2)t}+e ^{-j(ω+ω1-ω2)t})+(e ^{j(ω-ω1+ω2)t}+e ^{-j(ω-ω1-ω2)t})

+(e ^{j(ω+ω1-ω2)t}+e ^{-j(ω+ω1+ω2)t})+(e ^{j(ω-ω1-ω2)t}+e ^{-j(ω-ω1+ω2)t})}/2

＝(1/4){f((ω+ω1+ω2)+f(ω+ω1-ω2)+f(ω-ω1+ω2)+f(ω-ω1-ω2)}

…(9)

In addition, by frequency mixer 6292d, use signal k5 to signal f _A1ICarry out frequency transformation, generate signal f _B1QThis signal f _B1QProvide with following formula (10).

[formula 9]

f _b1Q＝[1/2(1/2)·{(e ^j(ω+ω1)t+e ^-j(ω+ω1)t)+(e ^j(ω-ω1)t+e ^-j(ω-ω1)t)·(e ^jω2t-e ^-jω2t)/2j

＝(1/4){(e ^{j(ω+ω1+ω2)t}+e ^{-j(ω+ω1-ω2)t})+(e ^{j(ω-ω1+ω2)t}+e ^{-j(ω-ω1-ω2)t})

-(e ^{j(ω+ω1-ω2)t}+e ^{-j(ω+ω1+ω2)t})-(e ^{j(ω-ω1-ω2)t}+e ^{-j(ω-ω1+ω2)t})}/2j

＝(1/4){f′(ω+ω1+ω2)-f′(ω+ω1-ω2)+f′(ω-ω1+ω2)-f′(ω-ω1-ω2)}

…(10)

In addition, by frequency mixer 6292e, use signal k2 to signal f _A1QCarry out frequency transformation, generate signal f _B2IThis signal f _B2IProvide with following formula (11).

[formula 10]

f _b2I＝1/2(1/2j)·{e ^j(ω+ω1)t-e ^-j(ω+ω1)t)-(e ^j(ω-ω1)t-e ^-j(ω-ω1)t)}·(e ^jω2t+e ^-jω2t)/2

＝(1/4){e ^{j(ω+ω1+ω2)t}-e ^{-j(ω+ω1-ω2)t})-(e ^{j(ω-ω1+ω2)t}-e ^{-j(ω-ω1-ω2)t})

+(e ^{j(ω+ω1-ω2)t}-e ^{-j(ω+ω1+ω2)t})-(e ^{j(ω-ω1-ω2)t}-e ^{-j(ω-ω1+ω2)t})}/2j

＝(1/4){f′(ω+ω1+ω2)+f′(ω+ω1-ω2)-f′(ω-ω1+ω2)-f′(ω-ω1-ω2)}

…(11)

In addition, by frequency mixer 6292f, use signal k5 to signal f _A1QCarry out frequency transformation, generate signal f _B2QThis signal f _B2QProvide with following formula (12).

[formula 11]

f _b2Q＝1/2(1/2j)·{e ^j(ω+ω1)t-e ^-j(ω+ω1)t)-(e ^j(ω-ω1)t-e ^-j(ω-ω1)t)}·(e ^jω2t-e ^-jω2t)/2j

＝-(1/4){e ^{j(ω+ω1+ω2)t}-e ^{-j(ω+ω1-ω2)t})-(e ^{j(ω-ω1+ω2)t}-e ^{-j(ω-ω1-ω2)t})

-(e ^{j(ω+ω1-ω2)t}-e ^{-j(ω+ω1+ω2)t})+(e ^{j(ω-ω1-ω2)t}-e ^{-j(ω-ω1+ω2)t})}/2

＝(1/4){-f(ω+ω1+ω2)+f(ω+ω1-ω2)+f(ω-ω1+ω2)-f(ω-ω1-ω2)}

…(12)

Here, according to (9)～(12), by this partial frequency transformation, generated frequency is respectively " ω+ω 1+ ω 2 ", " ω+ω 1-ω 2 ", " ω-ω 1+ ω 2 ", " ω-ω 1-ω 2 " 4 signals.

Figure 24 A～Figure 24 B, the 25th, expression is by the figure of the notion of the relation of the signal of this second level frequency transformation generation.In Figure 24 A～Figure 24 B, 25, the signal of the frequency of representing with solid line " ω-ω 1-ω 2 " is to wish received signal, and the signal of the frequency of other that with dashed lines, a dot-and-dash line, two dot-and-dash lines are represented " ω+ω 1+ ω 2 ", " ω-ω 1+ ω 2 ", " ω+ω 1-ω 2 " is respectively a picture signal 1～3.

Figure 24 A～Figure 24 B represents the phase shift relation of each signal.Figure 24 A is illustrated in the signal f on the same frequency axis _B1IWith signal f _B1QPhase relation, Figure 24 B is illustrated in the signal f on the same frequency axis _B2IWith signal f _B2QPhase relation.Shown in Figure 24 A～Figure 24 B, signal f _B1IWith signal f _B1Q, signal f _B2IWith signal f _B2QThe difference quadrature.

In addition, Figure 25 represents the frequency relation of each signal.As shown in the drawing, the picture signal 1 of frequency " ω+ω 1+ ω 2 ", the frequencies omega 1 that is positioned at signal k1 is center and the position of wishing the received signal symmetry, the picture signal 2 of frequency " ω-ω 1+ ω 2 ", the frequencies omega 2 that is positioned at signal k2 is center and the position of wishing the received signal symmetry, the picture signal 3 of frequency " ω+ω 1-ω 2 " is positioned at frequencies omega 2 _iBe the position of center and picture signal 1 symmetry, and frequencies omega 2 _iBe positioned at frequencies omega 1 is the position of center and frequencies omega 2 symmetries.

Then, according to formula (9)～(12) and Figure 24 A～Figure 24 B, the signal of following each frequency of taking-up.At first, the signal f (ω-ω 1-ω 2) of following taking-up frequency " ω-ω 1-ω 2 ".That is, from signal f _B1ISubtraction signal f _B2QIn addition, signal f _B1QWith signal f _B2IAddition, and then make its phase delay 90 degree.Then, by both signals of addition, cancel the signal content of other frequencies.Therefore, signal f (ω-ω 1-ω 2) represents with following formula (13).

[formula 12]

f(ω-ω1-ω2)＝f _b1I-f _b2Q+P(f _b1Q+f _b2I) …(13)

In addition, in following formula (13), function P (f) is the function that makes phase delay 90 degree of signal f.

In addition, the signal f (ω+ω 1+ ω 2) of following taking-up frequency " ω+ω 1+ ω 2 ".That is, from signal f _B1ISubtraction signal f _B2QIn addition, signal f _B1QWith signal f _B2QAddition, and then make leading 90 degree of its phase place.Then, by both signals of addition, cancel the signal content of other frequencies.Therefore, signal f (ω+ω 1+ ω 2) represents with following formula (14).

[formula 13]

f(ω+ω1+ω2)＝f _b1I-f _b2Q-P(f _b1Q+f _b2I) …(14)

In addition, the signal f (ω-ω 1+ ω 2) of following taking-up frequency " ω-ω 1+ ω 2 ".That is sum signal f, _B1IWith signal f _B2QIn addition, from signal f _B1QMiddle subtraction signal f _B2I, and then make leading 90 degree of its phase place.Then, by both signals of addition, cancel the signal content of other frequencies.Therefore, signal f (ω-ω 1+ ω 2) represents with following formula (15).

[formula 14]

f(ω-ω1+ω2)＝f _b1I+f _b2Q+P(-f _b1Q+f _b2I)

＝f _b1I+f _b2Q-P(f _b1Q-f _b2I) …(15)

In addition, the signal f (ω+ω 1-ω 2) of following taking-up frequency " ω+ω 1-ω 2 ".That is sum signal f, _B1IWith signal f _B2QIn addition, from signal f _B1QMiddle subtraction signal f _B2I, and then make its phase delay 90 degree.Then, by both signals of addition, cancel the signal of other frequencies.Therefore, signal f (ω+ω 1-ω 2) represents with following formula (16).

[formula 15]

f(ω+ω1-ω2)＝f _b1I+f _b2Q+P(f _b1Q-f _b2I) …(16)

From these formula (13)～(16), determine each movement content (adding/subtract) of adder-subtractor 6294a～6294d as Figure 26.Be each the movement contents of preceding half adding/subtract decision adder-subtractor 6294a of through type (13)～(16), by later half the movement content that adds/subtract decision adder-subtractor 6294b.In addition, each the phase shifts (leading/postpone) of 90 degree and adding/subtracting of preceding half and later half of through type (13)～(16), each movement content of decision adder-subtractor 6294c, 6294d.

Then, abide by this table,, generate the synthetic f of addition by adder-subtractor 6294a _B1IWith signal f _B2QSignal f _dOr from f _B1ISubtracted signal f _B2QSynthetic signal f _cThis signal f _dProvide signal f by following formula (17) _cProvide by following formula (18).

[formula 16]

f _d＝f _b1I+f _b2Q

＝((1/2){(e ^{j(ω+ω1-ω2)t}+e ^{-j(ω+ω1-ω2)t})+(e ^{j(ω-ω1+ω2)t}+e ^{-j(ω-ω1+ω2)t})}/2

…(17)

[formula 17]

f _c＝f _b1I-f _b2Q

＝(1/2){(e ^{j(ω+ω1+ω2)t}+e ^{-j(ω+ω1+ω2)t})+(e ^{j(ω-ω1-ω2)t}+e ^{-j(ω-ω1-ω2)t})}/2

…(18)

In addition, by adder-subtractor 6294b, generate the synthetic f of addition _B1QWith signal f _B2ISignal f _g, perhaps, from f _B1QSubtracted signal f _B2ISynthetic signal f _eThis signal f _gProvide signal f by following formula (19) _eProvide by following formula (20).

[formula 18]

f _g＝f _b1Q+f _b2I

＝(1/2){(e ^{j(ω+ω1+ω2)t}-e ^{-j(ω+ω1+ω2)t})-(e ^{j(ω-ω1-ω2)t}-e ^{-j(ω-ω1-ω2)t})}/2j

…(19)

[formula 19]

f _e＝f _b1Q-f _b2I

＝(1/2){(e ^{j(ω+ω1-ω2)t}-e ^{-j(ω+ω1-ω2)t})+(e ^{j(ω-ω1+ω2)t}-e ^{-j(ω-ω1+ω2)t})}/2j

…(20)

Then, by frequency mixer 6292g～6292j, carry out the frequency transformation of the third level.Promptly, generate with signal k3 signal f by frequency mixer 6292g _cCarry out the signal f of frequency transformation _CI3, perhaps, use signal k3 to signal f _dCarry out the signal f of frequency transformation _DI3This signal f _CI3Provide signal f with following formula (21) _DI3Provide with following formula (22).

[formula 20]

f _cI3＝(f _b1I-f _b2Q)·(e ^jω3t+e ^-jω3t)/2

＝{(e ^{j(ω+ω1+ω2+ω3)t}+e ^{-j(ω+ω1+ω2-ω3)t})+(e ^{j(ω-ω1-ω2+ω3)t}+e ^{-j(ω-ω1-ω2-ω3)t})

+(e ^{j(ω+ω1+ω2-ω3)t}+e ^{-j(ω+ω1+ω2+ω3)t})+(e ^{j(ω-ω1-ω2-ω3)t}+e ^{-j(ω-ω1-ω2+ω3)t})/8

＝(1/4){f(ω+ω1+ω2+ω3)+f(ω+ω1+ω2-ω3)

+f(ω-ω1-ω2+ω3)+f(ω-ω1-ω2-ω3)} …(21)

[formula 21]

f _dI3＝(f _b1I+f _b2Q)·(e ^jω3t+e ^-jω3t)/2

＝{(e ^{j(ω+ω1-ω2+ω3)t}+e ^{-j(ω+ω1-ω2-ω3)t})+(e ^{j(ω-ω1+ω2+ω3)t}+e ^{-j(ω-ω1+ω2-ω3)t})

+(e ^{j(ω+ω1-ω2-ω3)t}+e ^{-j(ω+ω1-ω2+ω3)t})+(e ^{j(ω-ω1+ω2-ω3)t}+e ^{-j(ω-ω1+ω2+ω3)t})/8

＝(1/4){f(ω+ω1-ω2+ω3)+f(ω+ω1-ω2-ω3)

+f(ω-ω1+ω2+ω3)+f(ω-ω1+ω2-ω3)} …(22)

In addition, by frequency mixer 6292h, generate with signal k6 signal f _eCarry out the signal f of frequency transformation _EQ3, perhaps, use signal k6 to signal f _gCarry out the signal f of frequency transformation _GQ3This signal f _EQ3Provide signal f with following formula (20) _GQ3Provide with following formula (24).

[formula 22]

f _eQ3＝(f _b1Q-f _b2I)·(e ^jω3t-e ^-jω3t)/2j

＝-{(e ^{j(ω+ω1-ω2+ω3)t}-e ^{-j(ω+ω1-ω2-ω3)t})+(e ^{j(ω-ω1+ω2+ω3)t}-e ^{-j(ω-ω1+ω2-ω3)t})

+(-e ^{j(ω+ω1-ω2-ω3)t}+e ^{-j(ω+ω1-ω2+ω3)t})+(-e ^{j(ω-ω1+ω2-ω3)t}+e ^{-j(ω-ω1+ω2+ω3)t})/8

＝(1/4){-f(ω+ω1-ω2+ω3)+f(ω+ω1-ω2-ω3)

-f(ω-ω1+ω2+ω3)+f(ω-ω1+ω2-ω3)} …(23)

[formula 23]

f _gQ3＝(f _b1Q+f _b2I)·(e ^jω3t-e ^-jω3t)/2j

＝-{(e ^{j(ω+ω1+ω2+ω3)t}-e ^{-j(ω+ω1+ω2-ω3)t})-(e ^{j(ω-ω1-ω2+ω3)t}-e ^{-j(ω-ω1-ω2-ω3)t})

+(-e ^{j(ω+ω1+ω2-ω3)t}+e ^{-j(ω+ω1+ω2+ω3)t})-(-e ^{j(ω-ω1-ω2-ω3)t}+e ^{-j(ω-ω1-ω2+ω3)t})/8

＝(1/4){-f(ω+ω1+ω2+ω3)+f(ω+ω1+ω2-ω3)

+f(ω-ω1-ω2+ω3)-f(ω-ω1-ω2-ω3)} …(24)

In addition, by frequency mixer 6292i, generate with signal k3 signal f _eCarry out the signal f of frequency transformation _EI3, perhaps, use signal k3 to signal f _gCarry out the signal f of frequency transformation _GI3This signal f _EI3Provide signal f with following formula (25) _GI3Provide with following formula (26).

[formula 24]

f _eI3＝(f _b1Q-f _b2I)·(e ^jω3t+e ^-jω3t)/2

＝{(e ^{j(ω+ω1-ω2+ω3)t}-e ^{-j(ω+ω1+ω2-ω3)t})+(e ^{j(ω-ω1+ω2+ω3)t}-e ^{-j(ω-ω1+ω2-ω3)t})

+(e ^{j(ω+ω1-ω2-ω3)t}-e ^{-j(ω+ω1-ω2+ω3)t})+(e ^{j(ω-ω1+ω2-ω3)t}-e ^{-j(ω-ω1+ω2+ω3)t})/8j

＝(1/4){f′(ω+ω1-ω2+ω3)+f′(ω+ω1-ω2-ω3)

+f′(ω-ω1+ω2+ω3)+f′(ω-ω1+ω2-ω3)} …(25)

[formula 25]

f _gI3＝(f _b1Q+f _b2I)·(e ^jω3t+e ^-jω3t)/2

＝{(e ^{j(ω+ω1+ω2+ω3)t}-e ^{-j(ω+ω1+ω2-ω3)t})-(e ^{j(ω-ω1-ω2+ω3)t}-e ^{-j(ω-ω1-ω2-ω3)t})

+(e ^{j(ω+ω1+ω2-ω3)t}-e ^{-j(ω+ω1+ω2+ω3)t})-(e ^{j(ω-ω1-ω2-ω3)t}-e ^{-j(ω-ω1-ω2+ω3)t})/8j

＝(1/4){f′(ω+ω1+ω2+ω3)+f′(ω+ω1+ω2-ω3)

-f′(ω-ω1-ω2+ω3)-f′(ω-ω1-ω2-ω3)} …(26)

In addition, by frequency mixer 6292j, generate with signal k6 signal f _cCarry out the signal f of frequency transformation _CQ3, perhaps, use signal k6 to signal f _dCarry out the signal f of frequency transformation _DQ3This signal f _CQ3Provide signal f with following formula (27) _DQ3Provide with following formula (28).

[formula 26]

f _cQ3＝(f _b1I-f _b2Q)·(e ^jω3t-e ^-jω3t)/2j

＝{(e ^{j(ω+ω1+ω2+ω3)t}+e ^{-j(ω+ω1+ω2-ω3)t})+(e ^{j(ω-ω1-ω2+ω3)t}+e ^{-j(ω-ω1-ω2-ω3)t})

+(-e ^{j(ω+ω1+ω2-ω3)t}-e ^{-j(ω+ω1+ω2+ω3)t})+(-e ^{j(ω-ω1-ω2-ω3)t}-e ^{-j(ω-ω1-ω2+ω3)t})/8j

＝(1/4){f′(ω+ω1+ω2+ω3)-f′(ω+ω1+ω2-ω3)

+f′(ω-ω1-ω2+ω3)-f′(ω-ω1-ω2-ω3)} …(27)

[formula 27]

f _dQ3＝(f _b1I+f _b2Q)·(e ^jω3t-e ^-jω3t)/2j

＝{(e ^{j(ω+ω1-ω2+ω3)t}+e ^{-j(ω+ω1-ω2-ω3)t})+(e ^{j(ω-ω1+ω2+ω3)t}+e ^{-j(ω-ω1+ω2-ω3)t})

+((-e ^{j(ω+ω1-ω2-ω3)t}-e ^{-j(ω+ω1-ω2+ω3)t})+(-e ^{j(ω-ω1+ω2-ω3)t}-e ^{-j(ω-ω1+ω2+ω3)t})/8j

＝(1/4){f′(ω+ω1-ω2+ω3)-f′(ω+ω1-ω2-ω3)

+f′(ω-ω1+ω2+ω3)-f′(ω-ω1+ω2-ω3)} …(28)

Then, by adder-subtractor 6294c, generate the synthetic f of addition _CI3With signal f _GQ3Signal f _H1, perhaps from signal f _CI3Middle subtracted signal f _GQ3Synthetic signal f _H2, perhaps f is synthesized in addition _DI3With signal f _EQ3Signal f _H3, perhaps from signal f _DI3Middle subtracted signal f _EQ3Synthetic signal f _H4This signal f _H1(29a) provides by following formula, signal f _H2(29b) provides by following formula, signal f _H3(29c) provides by following formula, signal f _H4(29d) provides by following formula.

[formula 28]

f _h1＝f _cI3+f _hQ3

＝(1/2){f(ω+ω1+ω2-ω3)+f(ω-ω1-ω2+ω3)} …(29a)

f _h2＝f _cI3-f _hQ3

＝(1/2){f(ω+ω1+ω2+ω3)+f(ω-ω1-ω2-ω3)} …(29b)

f _h3＝f _dI3+f _eQ3

＝(1/2){f(ω+ω1-ω2-ω3)+f(ω-ω1+ω2-ω3)} …(29c)

f _h4＝f _dI3-f _eQ3

＝(1/2){f(ω+ω1-ω2+ω3)+f(ω-ω1+ω2+ω3)} …(29d)

In addition, by adder-subtractor 6294d, generate the synthetic f of addition _CQ3With signal f _GI3Signal f _I1, perhaps from signal f _CQ3Middle subtracted signal f _GI3Synthetic signal f _I2, perhaps f is synthesized in addition _DQ3With signal f _EI3Signal f _I3, perhaps from signal f _DQ3Middle subtracted signal f _EI3Synthetic signal f _I4This signal f _I1(30a) provides by following formula, signal f _I2(30b) provides by following formula, signal f _I3(30c) provides by following formula, signal f _I4(30d) provides by following formula.

[formula 29]

f _i1＝f _cQ3+f _gI3

＝(1/2){f′(ω+ω1+ω2+ω3)-f′(ω-ω1-ω2-ω3)} …(30a)

f _i2＝f _cQ3-f _gI3

＝(1/2){-f′(ω+ω1+ω2-ω3)+f′(ω-ω1-ω2+ω3)} …(30b)

f _i3＝f _dQ3+f _eI3

＝(1/2){f′(ω+ω1-ω2+ω3)+f′(ω-ω1+ω2+ω3)} …(30c)

f _i4＝f _dQ3-f _eI3

＝(1/2){-f′(ω+ω1-ω2-ω3)-f′(ω-ω1+ω2-ω3)} …(30d)

Here, wish received signal for taking-up, subtract each other synthetic adder-subtractor 6294a, 6294d, addition synthetic adder-subtractor 6294b, 6294c after, the signal f that provides with formula (18) from adder-subtractor 6294a output _c, export the signal f that provides with formula (19) from adder-subtractor 6294b _gThen, the signal f that provides with formula (29a) from adder-subtractor 6294c output _H1, export the signal f that provides with formula (30b) from adder-subtractor 6294d _I2

Then, according to this formula (29a), (30b), satisfying following formula (31a) or frequencies omega (31b) becomes receive frequency.Therefore, receive frequency ω becomes following formula (32a) or (32b).

[formula 30]

ω+ω1+ω2-ω3＝O …(31a)

ω-ω1-ω2+ω3＝O …(31b)

[formula 31]

ω＝ω1+ω2-ω3 …(32a)

ω＝-(ω1+ω2-ω3) …(32b)

In addition, the signal d from totalizer 6295 outputs provides with following formula (33).

[formula 32]

d＝(f _cI3+f _gQ3) ²+(f _cQ3-f _gI3) ²

＝{(e ^{j(ω+ω1+ω2-ω3)t}+e ^{-j(ω+ω1+ω2-ω3)t})+(e ^{j(ω-ω1-ω2+ω3)t}+e ^{-j(ω-ω1-ω2+ω3)t})/2} ²

+{(e ^{j(ω+ω1+ω2-ω3)t}-e ^{-j(ω+ω1+ω2-ω3)t})-(e ^{j(ω-ω1-ω2+ω3)t}-e ^{-j(ω-ω1-ω2+ω3)t})/2j} ²

＝{cos(ω+ω1+ω2-ω3)t+cos(ω-ω1-ω2+ω3)t} ²+sin(ω+ω1+ω2-ω3)t

-sin(ω-ω1-ω2+ω3)t} ²

＝2+2cos(ω+ω1+ω2-ω3)t·cos(ω-ω1-ω2+ω3)t

-2sin(ω+ω1+ω2-ω3)t·sin(ω-ω1-ω2+ω3)t

＝2+2cos2ωt …(33)

Then, this signal d blocks radio-frequency component thus by the LPF (not shown) of regulation, and final output signal d becomes d=2, can only take out signal level.

In addition, in the multistage frequency-conversion circuit 629G of Figure 22, suppose that 3 different fractional frequency signal k1～k3 of frequency of utilization carry out 3 grades frequency transformation, but also can carry out the frequency transformation more than 4 grades or 4 grades.In this case, can the corresponding progression of progression of the frequency transformation of carrying out with hope be set, input fractional frequency signal k in each level for the partial circuit 624G that comprises frequency mixer 6292g～6292j and adder-subtractor 6294c, 6294d.

According to the structure of in Figure 21 and Figure 22, representing that in multistage frequency-conversion circuit 623, comprises detecting circuit 626, because not local oscillator circuit that need in the radio wave receiver of existing superhet mode, need or PLL circuit, so can realize stable reception, and can lower as all consumption electric power of device.By carry out frequency transformation to received signal multistagely, can realize that high precision receives in addition according to a plurality of fractional frequency signals.

And then, when carrying out multistage frequency transformation to received signal, can remove the picture signal composition that produces by this frequency transformation according to fractional frequency signal.That is,, each of received signal and first fractional frequency signal and the first frequency division phase shift signalling carry out the frequency transformation of the first order by being multiplied each other.Then, by being multiplied each other, each of first I signal that generates by this first order frequency transformation and first Q signal and second fractional frequency signal and the second frequency division phase shift signalling carry out partial frequency transformation, by addition or subtract each other second I signal of generation and the 3rd Q signal, second Q signal and the 3rd I signal each, remove the picture signal composition that produces by the first order and partial frequency transformation.Then, by that generate by this second frequency conversion, first, second composite signal each and three frequency division signal and three frequency division phase shift signalling each are multiplied each other, carry out the frequency transformation of the third level, by addition or subtract each other the 4th I signal and the 4th Q signal and the 5th I signal and the 5th Q signal of generation, remove the picture signal composition that the frequency transformation by the third level produces.

In the embodiment of narration so far, illustrated and in the Wave timepiece of acceptance criteria electric wave, used situation of the present invention, but also can be suitable equally for the radio wave receiver beyond this.

In addition, in the embodiment of narration so far, establishing reference frequency signal bs is that frequency is the signal of 32.768kHz, even but obviously other frequency can realize too.

Claims (20)

1. a radio wave receiver (620,620B, 620D) is characterized in that having:

Amplify the amplifier unit (622) of the received signal that receives with antenna (621);

The reference frequency output block (900) of the reference frequency signal of output preset frequency;

Frequency division parts (625,625B, 625D), with a plurality of frequency dividing ratios the signal after amplifying at double by the reference frequency signal of this reference frequency output block output or with the frequency of this reference frequency signal is carried out frequency division, and export a plurality of fractional frequency signals behind this frequency division;

Multistage frequency transform part (623,623B), wherein be connected in series with a plurality of translation circuits (624), be provided for elementary described translation circuit by the received signal after the described amplifier unit amplification as input signal, the such signal of described translation circuit output is as figure signal, this signal be with input signal transform to based on from described a plurality of fractional frequency signals of described frequency division parts output each frequency and the signal that obtains; With

Demodulation component (626), by any one fractional frequency signal in a plurality of fractional frequency signals behind the described frequency division parts frequency division as reference signal, be that detection is carried out on the basis with figure signal from the translation circuit output of the final level of described multistage frequency transform part.

2. radio wave receiver according to claim 1 is characterized in that, described demodulation component has:

First multiplying unit (6263) that described figure signal and described reference signal are carried out multiplying;

To carry out first square of parts (6267) of square operation by the signal after this first multiplying unit multiplying;

Described reference signal is carried out the phase shift parts (6262) of 90 degree phase shifts;

With described figure signal and second multiplying unit (6264) that carries out multiplying by the dephased signal of described phase shift parts;

To carry out second square of parts (6268) of square operation by the signal after this second multiplying unit multiplying; With

Will be by signal behind described first square of parts square operation and the adding unit (6269) that carries out additive operation by the signal behind described second square of parts square operation.

3. radio wave receiver according to claim 1 (620E) is characterized in that,

Described demodulation component, as reference signal, the figure signal so that final grade prime of the translation circuit in described multistage frequency transform part is exported carries out detection by final grade translation circuit the fractional frequency signal of exporting from described frequency division parts.

4. radio wave receiver according to claim 1 is characterized in that,

Each translation circuit of described multistage frequency transform part has:

The multiplying unit (6241) that input signal and fractional frequency signal are carried out multiplying; With

From filter part (6242) by the signal of extraction allocated frequency band the signal after this multiplying unit multiplying,

To export as figure signal by the signal that this filter part is extracted out.

5. radio wave receiver according to claim 1 is characterized in that,

Each translation circuit of described multistage frequency transform part has:

The multiplying unit (6241) that input signal and fractional frequency signal are carried out multiplying; With

From the filter part (6242) by the signal of extracting allocated frequency band the signal after this multiplying unit multiplying out, this filter part is constituted as and can a plurality ofly switches by frequency band (SW1, SW6a, SW6b ..) by selecting a ground the frequency band from predetermined,

The signal of being extracted out by this filter part is exported as figure signal.

6. radio wave receiver according to claim 1 is characterized in that,

Each translation circuit of described multistage frequency transform part has:

Not corresponding switching is set conversion frequency and switching output block (SW2, SW3, SW4, SW5) that first input signal is exported as figure signal.

7. radio wave receiver according to claim 1 is characterized in that also having:

Alternative pack (628) is selected the fractional frequency signal to each translation circuit input of described multistage frequency transform part from the fractional frequency signal by described frequency division parts output.

8. radio wave receiver according to claim 1 is characterized in that,

Each translation circuit of described multistage frequency transform part has:

The 3rd multiplying unit (6245a) that input signal and fractional frequency signal are carried out multiplying;

Described fractional frequency signal is carried out the first phase shift parts (6244) of 90 degree phase shifts;

With described input signal and the 4th multiplying unit (6245b) that carries out multiplying by the dephased signal of the described first phase shift parts;

The second phase shift parts (6246a, 6246b), be to by described the 3rd, the 4th multiplying unit two parts that signal carries out phase shift after the multiplying respectively, the described second phase shift parts carry out phase shift at least one side's signal, so that become 90 degree with respect to the phase shift difference of these two signals respectively; With

To carry out the plus-minus method parts (6247) of additive operation or subtraction by dephased two signals of these second phase shift parts,

Exporting as figure signal by the signal behind additive operation of described plus-minus method parts or the subtraction.

9. radio wave receiver according to claim 1 (620G) is characterized in that,

Described multistage frequency transform part (629G) has:

First, second, third phase shift parts (6291a, 6291b, 6291c), respectively first, second, third fractional frequency signal from a plurality of fractional frequency signals of described frequency division parts output is carried out 90 degree phase shifts, and export as first, second, third frequency division phase shift signalling;

Primary treatment parts (6292a, 6292b) by described received signal of having amplified being multiply by described first fractional frequency signal respectively and the described first frequency division phase shift signalling comes this received signal is carried out frequency transformation, generate and export first I signal and first Q signal;

The one IQ Signal Processing Element (6292c, 6292d, 6292e, 6292f), by described first I signal and first Q signal be multiply by described second fractional frequency signal and the described second frequency division phase shift signalling respectively, generate and export following signal thus: second Q signal that described first I signal is carried out second I signal that obtains after the frequency transformation and with the described second frequency division phase shift signalling described first I signal is carried out obtaining after the frequency transformation with described second fractional frequency signal, with the 3rd Q signal that with described second fractional frequency signal described first Q signal is carried out the 3rd I signal that obtains after the frequency transformation and with described second fractional frequency signal described first Q signal is carried out obtaining after the frequency transformation;

First compound component (6294a) carries out additive operation or subtraction to described second I signal and described the 3rd Q signal, and generates and export first composite signal;

Second compound component (6294b) carries out additive operation or subtraction to described second Q signal and described the 3rd I signal, and generates and export second composite signal;

The 2nd IQ Signal Processing Element (6292g, 6292h, 6292i, 6292j), by described first composite signal and second composite signal be multiply by described three frequency division signal and described three frequency division phase shift signalling respectively, generate and export following signal thus: the 4th Q signal that described first composite signal is carried out the 4th I signal that obtains after the frequency transformation and with described three frequency division phase shift signalling described first composite signal is carried out obtaining after the frequency transformation with described three frequency division signal, with the 5th Q signal that with described three frequency division signal described second composite signal is carried out the 5th I signal that obtains after the frequency transformation and with described three frequency division phase shift signalling described second composite signal is carried out obtaining after the frequency transformation;

The 3rd compound component (6294c) carries out additive operation or subtraction to described the 4th I signal and described the 4th Q signal, and generates and export the 3rd composite signal;

The 4th compound component (6294d) carries out additive operation or subtraction to described the 5th I signal and described the 5th Q signal, and generates and export the 4th composite signal; With

Back level processing element (6292k, 6292l, 6295), the quadratic sum and the output of calculating described the 3rd composite signal and described the 4th composite signal.

10. a radio wave receiving circuit (620,620B, 620D) is characterized in that having:

Amplify the amplifying circuit (622) of the received signal that receives with antenna (621);

The reference frequency output circuit (900) of the reference frequency signal of output preset frequency;

Frequency dividing circuit (625,625B, 625D), with a plurality of frequency dividing ratios the signal after amplifying at double by the reference frequency signal of this reference frequency output circuit output or with the frequency of this reference frequency signal is carried out frequency division, and export a plurality of fractional frequency signals behind this frequency division;

Multistage frequency-conversion circuit (623,623B), wherein be connected in series with a plurality of translation circuits (624), be provided for elementary described translation circuit by the received signal after the described amplifying circuit amplification as input signal, the such signal of described translation circuit output is as figure signal, this signal be with input signal transform to based on from described a plurality of fractional frequency signals of described frequency division parts output each frequency and the signal that obtains; With

Detecting circuit (626), by any one fractional frequency signal in a plurality of fractional frequency signals behind the described frequency dividing circuit frequency division as reference signal, be that detection is carried out on the basis with figure signal from the translation circuit output of the final level of described multistage frequency-conversion circuit.

11. radio wave receiving circuit according to claim 10 is characterized in that, described detecting circuit has:

First mlultiplying circuit (6263) that described figure signal and described reference signal are carried out multiplying;

To carry out first squaring circuit (6267) of square operation by the signal after this first mlultiplying circuit multiplying;

Described reference signal is carried out the phase-shift circuit (6262) of 90 degree phase shifts;

With described figure signal and second mlultiplying circuit (6264) that carries out multiplying by the dephased signal of described phase-shift circuit;

To carry out second squaring circuit (6268) of square operation by the signal after this second mlultiplying circuit multiplying; With

Will be by signal behind the described first squaring circuit square operation and the adding circuit (6269) that carries out additive operation by the signal behind the described second squaring circuit square operation.

12. radio wave receiving circuit according to claim 10 (620E) is characterized in that,

Described detecting circuit, as reference signal, the figure signal so that final grade prime of the translation circuit in described multistage frequency-conversion circuit is exported carries out detection by final grade translation circuit the fractional frequency signal of exporting from described frequency dividing circuit.

13. radio wave receiving circuit according to claim 10 is characterized in that,

Each translation circuit of described multistage frequency-conversion circuit has:

The mlultiplying circuit (6241) that input signal and fractional frequency signal are carried out multiplying; With

From filtering circuit (6242) by the signal of extraction allocated frequency band the signal after this mlultiplying circuit multiplying,

To export as figure signal by the signal that this filtering circuit is extracted out.

14. radio wave receiving circuit according to claim 10 is characterized in that,

Each translation circuit of described multistage frequency-conversion circuit has:

The mlultiplying circuit (6241) that input signal and fractional frequency signal are carried out multiplying; With

From the filtering circuit (6242) by the signal of extracting allocated frequency band the signal after this mlultiplying circuit multiplying out, this filtering circuit is constituted as and can a plurality ofly switches by frequency band (SW1, SW6a, SW6b ..) by selecting a ground the frequency band from predetermined,

The signal of being extracted out by this filtering circuit is exported as figure signal.

15. radio wave receiving circuit according to claim 10 is characterized in that,

Each translation circuit of described multistage frequency-conversion circuit has:

Not corresponding switching is set conversion frequency and switching output block (SW2, SW3, SW4, SW5) that first input signal is exported as figure signal.

16. radio wave receiving circuit according to claim 10 is characterized in that, also has:

Select circuit (628), from fractional frequency signal, select fractional frequency signal to each translation circuit input of described multistage frequency-conversion circuit by described frequency dividing circuit output.

17. radio wave receiving circuit according to claim 10 is characterized in that,

Each translation circuit of described multistage frequency-conversion circuit has:

The 3rd mlultiplying circuit (6245a) that input signal and fractional frequency signal are carried out multiplying;

Described fractional frequency signal is carried out first phase-shift circuit (6244) of 90 degree phase shifts;

With described input signal and the 4th mlultiplying circuit (6245b) that carries out multiplying by the dephased signal of described first phase-shift circuit;

Second phase-shift circuit (6246a, 6246b), be to by described the 3rd, the 4th mlultiplying circuit two circuit that signal carries out phase shift after the multiplying respectively, this second phase-shift circuit carries out phase shift at least one side's signal, so that become 90 degree with respect to the phase shift difference of these two signals respectively; With

To carry out the adder and substracter circuit (6247) of additive operation or subtraction by dephased two signals of this second phase-shift circuit,

Exporting as figure signal by the signal behind described adder and substracter circuit additive operation or the subtraction.

18. radio wave receiving circuit according to claim 1 (620G) is characterized in that,

Described multistage frequency-conversion circuit (629G) has:

First, second, third phase-shift circuit (6291a, 6291b, 6291c), respectively first, second, third fractional frequency signal from a plurality of fractional frequency signals of described frequency dividing circuit output is carried out 90 degree phase shifts, and export as first, second, third frequency division phase shift signalling;

Primary treatment circuit (6292a, 6292b) by described received signal of having amplified being multiply by described first fractional frequency signal respectively and the described first frequency division phase shift signalling comes this received signal is carried out frequency transformation, generates and exports first I signal and first Q signal;

The one IQ signal processing circuit (6292c, 6292d, 6292e, 6292f), by described first I signal and first Q signal be multiply by described second fractional frequency signal and the described second frequency division phase shift signalling respectively, generate and export following signal thus: second Q signal that described first I signal is carried out second I signal that obtains after the frequency transformation and with the described second frequency division phase shift signalling described first I signal is carried out obtaining after the frequency transformation with described second fractional frequency signal, with the 3rd Q signal that with described second fractional frequency signal described first Q signal is carried out the 3rd I signal that obtains after the frequency transformation and with described second fractional frequency signal described first Q signal is carried out obtaining after the frequency transformation;

First combiner circuit (6294a) carries out additive operation or subtraction to described second I signal and described the 3rd Q signal, and generates and export first composite signal;

Second combiner circuit (6294b) carries out additive operation or subtraction to described second Q signal and described the 3rd I signal, and generates and export second composite signal;

The 2nd IQ signal processing circuit (6292g, 6292h, 6292i, 6292j), by described first composite signal and second composite signal be multiply by described three frequency division signal and described three frequency division phase shift signalling respectively, generate and export following signal thus: the 4th Q signal that described first composite signal is carried out the 4th I signal that obtains after the frequency transformation and with described three frequency division phase shift signalling described first composite signal is carried out obtaining after the frequency transformation with described three frequency division signal, with the 5th Q signal that with described three frequency division signal described second composite signal is carried out the 5th I signal that obtains after the frequency transformation and with described three frequency division phase shift signalling described second composite signal is carried out obtaining after the frequency transformation;

The 3rd combiner circuit (6294c) carries out additive operation or subtraction to described the 4th I signal and described the 4th Q signal, and generates and export the 3rd composite signal;

The 4th combiner circuit (6294d) carries out additive operation or subtraction to described the 5th I signal and described the 5th Q signal, and generates and export the 4th composite signal; With

Post processing electric circuit (6292k, 6292l, 6295), the quadratic sum and the output of calculating described the 3rd composite signal and described the 4th composite signal.

19. a Wave timepiece is characterized in that having:

Amplifier unit (622) amplifies containing the received signal that obtains behind the standard wave of time information with antenna (621) reception;

The reference frequency output block (900) of the reference frequency signal of output preset frequency;

Frequency division parts (625,625B, 625D), with a plurality of frequency dividing ratios the signal after amplifying at double by the reference frequency signal of this reference frequency output block output or with the frequency of this reference frequency signal is carried out frequency division, and export a plurality of fractional frequency signals behind this frequency division;

Multistage frequency transform part (623,623B), wherein be connected in series with a plurality of translation circuits (624), be provided for elementary described translation circuit by the received signal after the described amplifier unit amplification as input signal, the such signal of described translation circuit output is as figure signal, this signal be with input signal transform to based on from described a plurality of fractional frequency signals of described frequency division parts output each frequency and the signal that obtains;

Demodulation component (626), by any one fractional frequency signal in a plurality of fractional frequency signals behind the described frequency division parts frequency division as reference signal, be that detection is carried out on the basis with figure signal from the translation circuit output of the final level of described multistage frequency transform part;

The timing code that generates time information according to the rectified signal from this demodulation component output generates parts (700);

Timing piece (800), the reference frequency signal based on from described reference frequency output block output carries out timing to current time; With

Moment correcting part (100) is according to generating the time information that parts generated by described timing code, to just being revised at the current time of timing by described timing piece.

20. Wave timepiece according to claim 19 is characterized in that,

As reference signal, the figure signal so that final grade prime of the translation circuit in described multistage frequency transform part is exported carries out detection by final grade translation circuit to described demodulation component the fractional frequency signal of being exported from described frequency division parts.

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