CN1889551A - Discrete multi-audio frequency modulating system optimal power distributing comprehensive bit position loading method - Google Patents

Abstract

A resource distribution technique of discrete multiaudio modulation system includes carrying out maximum bit-loading for system and ending bit-loading course if maximum bit rate is not over object bit rate or otherwise deriving out loading parameter value, utilizing greedy bit erasure method to finalize bit distribution if parameter value is zero, applying parallel bit erasure method to speed up bit distribution rate and updating system bit rate and loading parameter if loading parameter value is not zero, using addition method to converge it to be object bit rate if system current bit rate is lower than object bit rate then using bit fine regulation to realize minimum power bit distribution.

Description

The comprehensive bit position loading method of discrete multi-audio frequency modulating system optimal power division

Technical field

The comprehensive bit position loading method that is used for DMT and is the discrete multi-audio frequency modulating system optimal power division belongs to the resource allocation techniques of Discrete multi-tone modulation communication system.

Background technology

Along with Internet development and user increase for multimedia broad band digital service demand, require wide-band communication system of future generation not only can carry out high speed data transfers reliably, and distributing system resource neatly, to satisfy the different demands of different service types.

Discrete multi-tone modulation (DMT) is a kind of special shape of multi-carrier modulation technology.DMT is divided into abundant narrowband subchannels with communication channel, each subcarrier all carries out independently QAM modulation, utilize IDFT and DFT that signal is carried out modulation and demodulation, have and realize simply, availability of frequency spectrum height, characteristics such as anti-impulsive noise ability is strong, be particularly suitable at serious channel circumstance of intersymbol interference (ISI) such as twisted pair telephone and exist in the wireless channel of multipath fading carrying out high speed data transfers, therefore elected as the modulation standard that multiple Digital Subscriber Line (xDSL) comprises ADSL (Asymmetric Digital Subscriber Line) (ADSL) and Very-high-speed Digital Subscriber Line (VDSL) by the standardization body of US and European and International Telecommunications Union and (see B.Nowrouzian, L.Wang, and W.Agha, " An overview of discrete multitone modulation/demodulation systems in xDSLapplications ", Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol.1, pp.31-35, Nov., 2001.).A key issue in the DMT system design is exactly how under the various restrictive conditions of system itself, carries out resource allocation according to attenuation characteristic and noise, the interference profile situation of each subchannel, with the optimization system performance.Under the situation that one of them typical optimization problem is certain at system's total mean power and target bit rate is certain, how to adjust the transmitted power and the bit number of each subcarrier, the signal to noise ratio (snr) allowance that makes system is the difference maximization of system's total mean power and actual total transmitted power of using, be equivalent to total transmitted power of the actual use of system is minimized, this problem is also referred to as allowance self adaptation (MA) problem.

The most basic MA problem is retrained by system's gross bit rate, and corresponding optimum loading method is a water-filling algorithm.Because the optimal solution non-integer of water-filling algorithm, require the constellation degree of quantization can be infinitely small, in real system, make to be difficult to realize.Therefore having increased each subcarrier bit number again is the constraints of integer, corresponding two kinds of loading methods are that the optimum loading method that Hughes-Hartog proposes (is seen Hughes-Hartog, " Ensemble modem structure for imperfect transmission media ", USPatent, Patent Number:4833706,1989.) and the suboptimum loading method that proposes of Chow (see P.S.Chow, " Bandwidth optimized digital transmission techniques for spectrally shaped channelswith impulse noise ", Stanford University, 1993-05.).The Hughes-Hartog method is a kind of greedy algorithm, and the subcarrier of the most suitable current next bit of transmission is selected on this algorithm bit-by-bit ground, up to gross bit rate or till always transmitted power satisfies the system design index.Because the target bit rate that actual DMT system such as ADSL require is very high, adopt the greedy algorithm operand too big, and impracticable.The Chow method is that the pairing approximation water filling is separated to round up and carried out Bit Allocation in Discrete, because the required operand of Chow method almost separates with water filling that operand equates even is bigger, so also impracticable.J.Campello and H.Levin are at the shortcoming of greedy algorithm, set up a cover complete and on mathematics the feasible discrete distribution method of optimum, be called the LC algorithm, performance improves a lot and (sees J.M.Cioffi, " Advanced Digital Communication ", EE379C CourseTextbook, Stanford University, 2002. and J.Campello, " Optimal discrete bit loadingfor multicarrier modulation systems ", International Symposium on Information Theory, p.193, August 16-12,1998.).The LC algorithm selects a kind of initial discrete bits to distribute at first arbitrarily, use validation (EF) algorithm to make bits of original distribute effectively then---Bit Allocation in Discrete validity is defined as: when a subcarrier was transferred to another subcarrier and all no longer can be reduced system's transmitted power, then this Bit Allocation in Discrete was effective with arbitrary information bit; Last bit-by-bit distributes, up to satisfying the target bit rate requirement.But because the selection that bits of original distributes has blindness, select when improper, the required operand of validation is bigger, and, when initial bit rate when the target bit rate difference is big, the operand that bit-by-bit distributes is also very big.

After this research considers that various DSL are professional as the spectral compatibility problem between Integrated Service Digital Network, high-bit-rate digital subscriber line (HDSL) etc. and the ADSL, need to increase the restrictive condition of various DSL circuit transmit power spectral density (PSD) (is seen John A.C.Bingham, " ADSL; VDSL; and Multicarrier Modulation ", John Wiley ﹠amp; Sons, 2000.), in addition, consider that timing error or interchannel noise, disturbance regime worsen the influence to systematic function, need reserve certain allowance to system, the restriction that also should be taken into account maximum qam constellation size (is seen R.V.Sonalkar andR.R.Shively, " An efficient bit-loading algorithm for DMT applications ", IEEE GlobalTelecommunications Conference, vol.5, pp.2683-2688, Nov., 1998.).At these constraints, Fasano proposes zero-based greedy bit increase method and (sees A.Fasano from the greedy bit delet method that system's Maximum Bit Rate begins from matroid opinion angle, G.D.Blasio, E.Baccarelli and M.Biagi, " Optimal discrete bitloading for DMT based constrained multicarrier sytems ", ISIT 2002, Lausanne, Switzerland, June 30-July 5,2002), and propose under the restriction of maximum PSD of system and maximum qam constellation size, greedy bit delet method than greedy bit increase method more practicability and effectiveness (see A.Fasano, " On the optimaldiscrete bit loading for multicarrier systems with constraints ", V57th IEEESemiannual ehicular Technology Conference, vol.2, pp.915-919, April, 2003.).Sonalkar and Shively further limit the bit number of the minimum distribution of each subcarrier, proposition (is seen R.V.Sonalkar and R.R.Shively based on the optimum loading method of greedy bit deletion, " An efficient bit-loadingalgorithm for DMT applications ", IEEE Communications Letters, vol.4, no.3, pp.80-82,2000.).Still there be the problem same with the LC algorithm in above-mentioned greedy loading method, and when promptly original upload speed and target bit rate differed big, operand was very big.People such as Papandreou and Antonakopoulos proposes to adopt many bit loading methods acceleration target bit rate rates of convergence (to see N.Papandreou and T.Antonakopoulos at this problem, " A newcomputationally efficient discrete bit-loading algorithm for DMT application ", IEEETransactions on Communications, vol.53, no.5, pp.785-789,2005.).This method utilizes the difference of each subchannel gains noise ratio (CNR) to provide a kind of effective Bit Allocation in Discrete earlier, obtain initial bit rate and bits of original distribution by significant bit distribution and system's maximum rate bit distribution, approach optimal solution according to the difference of initial bit rate and target bit rate with many bit loading methods then, utilize greedy bit increase or delet method at last again to obtain target bit rate.This loading method is applicable to that target bit rate does not require very high system, and its operand obviously increases when high target bit rate, and operation efficiency descends.For the DMT system that high target bit rate requirement is arranged, still there is not optimal power allocation bit loading method efficiently at present.Because the user increases day by day to the demand of multimedia services such as figure, image, requires the future communications system to have very high message transmission rate, promptly high target bit rate, bit loading method is supported efficiently accordingly.

The present invention is a kind of comprehensive optimum discrete bits loading method that combines based on the multiple bit loading method of parallel bit deletion of high target bit rate DMT system's proposition.By introducing loading parameters, this method can be according to the difference of target bit rate, the loading method that adopts greedy bit deletion or parallel bit deletion, greedy bit additions and deletions and bit fine setting to combine respectively carries out bit and power division, to guarantee the high operation efficiency under the various high target bit rates.The main feature of this method is, starting stage does not need to calculate significant bit and distributes, under high target bit rate situation, usually only need to carry out a parallel bit deletion and can rapidly converge to target bit rate, make the required transmitted power minimum of final Bit Allocation in Discrete by the bit fine setting again.Its advantage is that flexibility is big, and algorithm is simple, is easy to realize.In most cases, Bit Allocation in Discrete when reaching target bit rate has been the minimum power Bit Allocation in Discrete, even bit distribution does not satisfy the validity requirement under the individual cases, only need minority bit fine setting several times just can realize optimum allocation, need not pay the initial significant bit distribution of big computing overhead computational.In target bit rate was the 60%-99% scope of loop Maximum Bit Rate, the operation efficiency of this method was particularly useful for carrying out the DMT system of high data rate transfer apparently higher than existing optimum discrete bits loading method.

Summary of the invention

The purpose of this invention is to provide a kind of comprehensive bit position loading method that is used for the discrete multi-audio frequency modulating system optimal power division, in target bit rate is the high target bit rate scope of 60%-90% of system's Maximum Bit Rate, realize high operation efficiency optimal power Bit Allocation in Discrete.

The method of the invention is characterised in that:

(1) at first system is carried out Maximum Bit Rate and load, according to signal to noise ratio difference Γ, subcarrier n place subchannel gains noise ratio CNR _n, the maximum power spectral densities Φ of system and subchannel bandwidth F, be calculated as follows number of bits b by each subcarrier n of Φ decision _n, n=1,2 ..., M,

Described CNR _n, Φ and F be set point, Γ is by the aiming symbol error probability P that sets _e, signal to noise ratio allowance γ _mWith coding gain γ _cCommon definite, provide by following formula:

$\mathrm{\Γ}=10{\log }_{10}\left(\frac{{\left[Q^{-1}(P_e/2)\right]}^2}{3}\right)+{\mathrm{\γ}}_m-{\mathrm{\γ}}_c---\left(2\right)$

Wherein, Q ^-1(x) inverse function of expression Q (x), function Q (x) is provided by following formula:

$Q\left(x\right)=\frac{1}{\sqrt{2\mathrm{\&pi;}}}{\&Integral;}_x^{\&infin;}{e}^{-{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="A20061008963000191.png,A20061008963000211.png"\; state="\{\{state\}\}">t</figure-callout>}}^2/2}\mathrm{dt},x=P_e/2;---\left(3\right)$

Then, be calculated as follows the number of bits b of each subcarrier _nM altogether, n=1,2 ..., M,

b _n＝min(b _max， b _n)， (4)

Wherein, b _MaxNumber of bits for the maximum qam constellation size decision set.Determine systematic bits rate B by following formula:

$B=\underset{n=1}{\overset{M}{\mathrm{\&Sigma;}}}{b}_n,---\left(5\right)$

This moment, B was system's Maximum Bit Rate.If B≤B _T, then bit loads and finishes; Otherwise, be calculated as follows the difference Bdiff of Maximum Bit Rate and target bit rate:

Bdiff＝B-B _T. (6)

(2) according to Bdiff and b _nWith b _MaxBetween relation ask loading parameters u, n=1,2 ..., M utilizes parallel bit deletion to quicken Bit Allocation in Discrete speed.At first, according to each subcarrier number of bits b of Maximum Bit Rate allocated phase _nWhether surpass b _Max, the subcarrier sequence number is divided into two classes, be placed on set respectively

With

In, wherein, $\tilde{N}=\{n:{\stackrel{\&OverBar;}{b}}_n>b_{\max },n=\mathrm{1,2},...,M\}$ Be subcarrier number of bits b _nSurpass b _MaxThe set of subcarrier sequence number, $\underset{~}{N}=\{n:0<{\stackrel{\&OverBar;}{b}}_n{\&le;b}_{\max },n=\mathrm{1,2},...,M\}$ Be subcarrier number of bits b _nBe no more than b _MaxThe set of subcarrier sequence number, set

With

The number of middle element promptly

With

Radix be respectively

With

Ask the value of loading parameters u by the following method:

If $\tilde{L}=0,$ U is determined by following formula:

If $\tilde{L}\&NotEqual;0,$ U is determined by following formula:

Wherein, $v=\underset{n\&Element;N}{\max }({\stackrel{\&OverBar;}{b}}_n-b_{\max })$ Be b _nWith b _MaxThe maximum of difference, $n\&Element;\tilde{N}.$

According to the size of u, carry out the parallel bit deletion by the following method:

Earlier sequence number is set

The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _nIf u＞1 also needs sequence number is set ${\tilde{N}}_{\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="A20061008963000191.png,A20061008963000211.png"\; state="\{\{state\}\}">s</figure-callout>}1}=\{n:b_{\max }<{\stackrel{\&OverBar;}{b}}_n<b_{\max }+u,n\&Element;\tilde{N}\}$ The number of bits deletion u-(b of each subcarrier of middle element _n-b _Max) bit, promptly sequence number is

The subcarrier bit number of middle element is reduced to b _n-u obtains new number of bits b _nThe parallel bit deletion may make some subcarrier bit number for negative, with b _nThe number of bits zero setting of the subcarrier n of＜0 correspondence obtains new number of bits b _n, the bit rate B that the system that is calculated as follows then is new:

$B=\underset{n=1}{\overset{M}{\mathrm{\&Sigma;}}}{b}_n,---\left(9\right)$

And by the new Bdiff of (6) formula calculating.If Bdiff=0, then the bit loading procedure finishes; If Bdiff＜0, then carrying out greedy bit increases; If Bdiff＞0, the initial value with loading parameters u leaves in the Δ earlier, i.e. Δ=u calculates the new value of loading parameters u then by the following method:

If parallel bit deletion back number of bits b _nFor the set of positive subcarrier sequence number is ${\underset{~}{N}}_s^{+}=\{n:0<b_n,n\&Element;\underset{~}{N}\},$

Radix be

Be calculated as follows the new value of u:

If u=0 then carries out greedy bit deletion; Otherwise, carry out the parallel bit deletion by the following method:

Earlier sequence number is set ${\underset{~}{N}}_s^{+}\&cup;{\tilde{N}}_{s1}$ The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _nIf $\tilde{L}-{\tilde{L}}_{a1}\&NotEqual;0,$ Be set Radix, then also need sequence number is set ${\tilde{N}}_{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061008963000191.png,A20061008963000211.png"\; state="\{\{state\}\}">s</figure-callout>}2}=\{n:{\stackrel{\&OverBar;}{b}}_n=b_{\max }+\mathrm{\&Delta;},n\&Element;\tilde{N}\}$ The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _nFurther, if $\tilde{L}-{\tilde{L}}_{s1}-{\tilde{L}}_{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061008963000191.png,A20061008963000211.png"\; state="\{\{state\}\}">s</figure-callout>}2}\&NotEqual;0,$

Be set

Radix, then also need sequence number is set ${\tilde{N}}_{\mathrm{<figure-callout\; id="3"\; label="s"\; filenames="A20061008963000221.png"\; state="\{\{state\}\}">s</figure-callout>}3}=\{n:b_{\max }+\mathrm{\&Delta;}<{\stackrel{\&OverBar;}{b}}_n<b_{\max }+\mathrm{\&Delta;}+u,n\&Element;\tilde{N}\}$ Each subcarrier number of bits of middle element is reduced to b _n-Δ-u, u are new value, obtain new number of bits b _n

With b _nThe bit position zero of each subcarrier n of＜0 correspondence obtains new number of bits b _n, successively calculate new B and new Bdiff according to (9) formula and (6) formula.If Bdiff=0, then bit loads and finishes; If Bdiff＜0 or u=0 then increase by greedy bit respectively or the deletion of greedy bit converges to B _T, realize the optimal power Bit Allocation in Discrete by the bit fine setting at last.In fact, after the execution parallel bit deletion for the second time, Bdiff is enough little, can directly enter greedy bit deletion and bit fine setting stage by Bdiff＞0, need not to calculate u again.

Greedy bit increase is set from sequence number at every turn ${\tilde{N}}_p=\{n:0\&le;b_n<b_{\max },n=\mathrm{1,2},...,M\}$ Seeking in each subcarrier of middle element increases the required transmitted power increment Delta of 1 bit P _n ⁺(b _n) minimum subcarrier address n ⁺, $n\&Element;{\tilde{N}}_p,$ Promptly $n^{+}=\arg \left\{\underset{n\&Element;{\tilde{N}}_p}{\min }\right[{\mathrm{\&Delta;P}}_n^{+}\left(b_n\right)\left]\right\},$ Calculate transmitted power increment Delta P according to (1) formula for the first time _n ⁺(b _n), with subcarrier n ⁺Number of bits increase by 1, promptly $b_{n^{+}}=b_{n^{+}}+1;$ If $b_{n^{+}}<b_{\max },$ Then with Δ P _N+ ⁺(b _N+) be updated to 2 times of initial value, otherwise, with Δ P _N+ ⁺(b _N+) value be changed to infinity; Repeat said process, up to Bdiff=0.

Greedy bit deletion is set from sequence number at every turn ${\underset{~}{N}}_p=\{n:0<b_n{\&le;b}_{\max },n=\mathrm{1,2},...,M\}$ Seek in each subcarrier of middle element and reduce the required transmitted power decrement of 1 bit Δ P _n ^-(b _n) maximum subcarrier address n ^-, $n\&Element;{\underset{~}{N}}_p,$ Promptly $n^{-}=\arg .\left\{\underset{n\&Element;{\underset{~}{N}}_p}{\max }\right[{\mathrm{\&Delta;P}}_n^{-}\left(b_n\right)\left]\right\},$ Be calculated as follows for the first time transmitted power decrement Δ P _n ^-(b _n):

${\mathrm{\&Delta;P}}_n^{-}\left(b_n\right)=2^{(b_n-1)}\frac{\mathrm{\&Gamma;}}{{\mathrm{CNR}}_n},0<b_n{\&le;b}_{\max };---\left(11\right)$

With subcarrier n ^-Number of bits reduce 1, promptly $b_{n^{-}}=b_{n^{-}}-1;$ If $0<b_{n^{-}},$ Then with Δ P _N- ^-(b _N-) be updated to 1/2 of initial value; Otherwise, with Δ P _N+ ⁺(b _N+) value be changed to zero; Repeat said process, up to Bdiff=0.

During the bit fine setting, determine that earlier sequence number is set ${\tilde{N}}_p=\{n:0\&le;b_n<b_{\max },n=\mathrm{1,2},...,M\}$ The number of bits of each subcarrier of middle element increases the required transmitted power increment Delta of 1 bit P respectively _n ⁺(b _n), 1≤n≤M, minimum subcarrier address n ⁺, promptly $n^{+}=\arg \left\{\underset{n\&Element;{\tilde{N}}_p}{\min }\right[{\mathrm{\&Delta;P}}_n^{+}\left(b_n\right)\left]\right\},$ And sequence number is set ${\underset{~}{N}}_p=\{n:0<b_n{\&le;b}_{\max },n=\mathrm{1,2},...,M\}$ The number of bits of each subcarrier of middle element reduces the required transmitted power decrement of 1 bit Δ P respectively _n ^-(b _n), 1≤n≤M, maximum subcarrier address n ^-, promptly $n^{-}=\arg \left\{\underset{n\&Element;{\underset{~}{N}}_p}{\max }\right[{\mathrm{\&Delta;P}}_n^{-}\left(b_n\right)\left]\right\},$ If ${\mathrm{\&Delta;P}}_{n^{+}}^{+}\left(b_{n^{+}}\right)\&GreaterEqual;{\mathrm{\&Delta;P}}_{n^{-}}^{-}\left(b_{n^{-}}\right),$ Then Bit Allocation in Discrete finishes; Otherwise, with subcarrier n ⁺Number of bits increase by 1, promptly $b_{n^{+}}=b_{n^{+}}+1,$ With subcarrier n ^-Number of bits reduce 1, promptly $b_{n^{-}}=b_{n^{-}}-1.$ If $b_{n^{+}}<b_{\max },$ Then with Δ P _N+ ⁺(b _N+) be updated to 2 times of initial value, otherwise, with Δ P _N+ ⁺(b _N+) value be changed to infinity; If $0<b_{n^{-}},$ Then with Δ P _N- ^-(b _N-) be updated to 1/2 of initial value; Otherwise, with Δ P _N+ ⁺(b _N+) value be changed to zero.Repeat said process then, up to ${\mathrm{\&Delta;P}}_{n^{+}}^{+}\left(b_{n^{+}}\right)\&GreaterEqual;{\mathrm{\&Delta;P}}_{n^{-}}^{-}\left(b_{n^{-}}\right).$

Effect analysis:

Do not consider that the maximum rate bit loads (all needing in the various optimum loading methods), in existing optimal bit loading method, the expense of multicarrier loading method is except that fundamental types such as addition and subtraction, division, comparison, assignment and logical operation, also comprise the more complicated logarithm operation of asking, and the required expense of this loading method is basic operation, therefore, this method is easier to realize than manying bit loading method.In most cases, this method has just realized optimal power allocation after finishing greedy bit additions and deletions, need not calculate significant bit when original upload distributes, not only having saved the complicated logarithm of asking operates, the dynamic range problems of too that has occurred when also having avoided differing greatly because of each subcarrier place subchannel gains noise ratio (CNR) of circuit in many bit loading methods has greater flexibility.

With 5 kinds of dissimilar ADSL system standard test loops comprising 220 subcarriers is example, when loop is operated in high target bit rate situation following time (target bit rate is the 60%-99% of loop maximum bit rate), the main operand of greedy bit deletion, many bit loading methods and this method is contrasted.The operand of greedy bit delet method is directly proportional with the difference of target bit rate and loop Maximum Bit Rate, when target bit rate during near the loop maximum bit rate (as maximum bit rate 99%), greedy bit delet method is identical with the required main operand of this method, but under other high target bit rate situations, the operand of greedy bit delet method is then apparently higher than the operand of this method, especially when the difference of target bit rate and loop Maximum Bit Rate was big, the operation efficiency of greedy bit delet method obviously descended.Many bit loading methods are higher than greedy bit delet method at 90% operation efficiency when following that target bit rate is about the loop Maximum Bit Rate, but are lower than greedy bit delet method at the 90% above operation efficiency that is about Maximum Bit Rate at target bit rate.And this method (target bit rate is the loop mid-CSA of Maximum Bit Rate 70%) except that the few cases, required main operand all significantly is lower than the operand of many bit loading methods under various high target bit rate situations.Therefore, total operation efficiency (comprising operand and robustness) in the whole high target bit rate scope, this method is that operation efficiency is the highest in three kinds of optimum loading methods, is more suitable in the DMT system that has high speed data transfers to require than existing optimum loading method.

Description of drawings

Fig. 1 is that the DMT system sends and receive theory diagram.

Fig. 2 is a DMT system transmitting terminal high-level schematic functional block diagram.

Fig. 3 is a DMT system optimal power division comprehensive bit position loading method schematic diagram.

Fig. 4-Fig. 8 is the comprehensive bit position loading method implementing procedure figure of DMT system optimal power division.

Embodiment:

The comprehensive bit position loading method of DMT system optimal power division is to realize on the digital integrated circuit chip of DMT system transmitting terminal as the Bit Allocation in Discrete circuit.Accompanying drawing 1 sends and receives theory diagram for the DMT system.Accompanying drawing 2 is a DMT system transmitting terminal high-level schematic functional block diagram.Behind transmitting terminal incoming bit stream process buffering and the serial to parallel conversion, the characteristic of channel parameter information that utilizes the low-speed reverse channel to pass back, finish the subcarrier Bit Allocation in Discrete, after encoded then mapping, convolution and the IFFT conversion, add Cyclic Prefix (CP), the bit stream behind the parallel serial conversion is delivered in the circuit after digital-to-analogue conversion.The receiving terminal inverse process restore data bit rate of transmitting terminal.Characteristic of channel parameter can obtain by the initialization training.In the ADSL of standard test environment, characteristic of channel parameter is known, and the present invention has utilized ADSL standard testing loop when realizing.The comprehensive bit position loading method schematic diagram of DMT system optimal power division is seen accompanying drawing 3.The comprehensive bit position loading method implementing procedure figure of DMT system optimal power division sees accompanying drawing 4-accompanying drawing 8.Provide a concrete application example below.Consideration ADSL standard testing loop T1.601#9 ring (sees that dragon rises, Cioffi J.M. and Liu Feng, xDSL technology and application, the Electronic Industry Press, 2002.) down link (155kHz～1.1MHz frequency range), the DMT symbol lengths is 250us, and subchannel bandwidth is 4.3125kHz, and sample rate is 2.208MHz.Down link actual loaded sub-carrier number is M=220.Loop is operated under the environment of 10 HDSL and 10 ADSL cross-talk, and the PSD of background additive white Gaussian noise (AWGN) is-140dBm/Hz.System adopts the Frequency Division Duplexing (FDD) technology, and gross power is 100mW, and the maximum PSD that allows of each subchannel is-40dBm/Hz, and the SNR allowance is 6dB, and coding gain is 2dB, target bits error rate BER=10 ^-7Pairing SNR difference is about Γ=9.5-2+6=13.5 (dB), b _Max=8.Test loop Maximum Bit Rate B is 1584 bit/symbol, target bit rate B _TBe chosen as 95%, 80% and 60% of Maximum Bit Rate respectively, i.e. 1505,1267 and 950 (units: bit/symbol, summary).

4 Maximum Bit Rate load at first with reference to the accompanying drawings, computing system Maximum Bit Rate B and B and B _TDifference Biff.Determine loading parameters u then.According to ${\stackrel{\&OverBar;}{b}}_n(n\&Element;\tilde{N})$ With b _MaxRelation can try to achieve set

Length be $\tilde{L}=67,$ Set

Length be $\underset{~}{L}=153,$ ${\stackrel{\&OverBar;}{b}}_n(n\&Element;\tilde{N})$ With b _MaxThe maximum of difference be v=3.Work as B _T=1505 o'clock, Bdiff=79, therefore loading parameters u=0 can carry out greedy bit deletion according to accompanying drawing 7, need carry out 79 transmitted power incremental raios and subtraction.Work as B _T=1267 o'clock, u=2 carried out the parallel bit deletion according to accompanying drawing 4 and accompanying drawing 5, deletes 184 bits altogether, upgrade B then, try to achieve Bdiff=-20,6 finish remaining Bit Allocation in Discrete with reference to the accompanying drawings, carry out the bit fine setting according to accompanying drawing 8 then, it is 0 that bit is adjusted number of times, shows to reach B _TThe time Bit Allocation in Discrete be the minimum power Bit Allocation in Discrete.Work as B _TGot 950 o'clock, loading parameters u=v=3, carry out the parallel bit deletion according to accompanying drawing 4 and accompanying drawing 5, delete 208 bits altogether, remaining bits is counted Bdiff=89,7 finishes remaining Bit Allocation in Discrete with reference to the accompanying drawings, carries out the bit fine setting according to accompanying drawing 8 then, it is 0 all also that bit is adjusted number of times, shows and realizes the optimal power Bit Allocation in Discrete.

Emulation experiment is at 5 kinds of ADSL standard testing loop T1.601#9, T1.601#13, CSA#7, CSA#8 and mid-CSA, adopting greedy bit deletion, the loading of many bits and this method to carry out the optimal power bit respectively loads, the bit distribution that the whole bag of tricks obtains is identical, and have identical transmitted power, but operand is different.All data that provide in the simulation result are all represented the computing magnitude after the M normalization.

Table 1 get respectively for target bit rate the loop Maximum Bit Rate 99%, 90%, 80%, 70% and 60% o'clock 3 kind of optimum loading method main operand relatively, and provided many bit loading methods and be used for the operand of additions and deletions of many bits and greedy bit additions and deletions and the operand that this method is used for parallel bit deletion and greedy bit additions and deletions.Because the used logarithm operation of asking is not the basic operation type in many bit loading methods, will load expense about the main operand of many bit loading methods and this method in the table 1 and count interior.If consider the loading expense, then this method action required type is simpler, is easier to realize.As can be seen from Table 1, the additions and deletions of many bits are deleted required operand with parallel bit and are compared and can ignore with greedy bit additions and deletions, are not counted in when loading expense, and main operand is the required operands of greedy bit additions and deletions.As shown in Table 1, except that the few cases (target bit rate is the loop mid-CSA of Maximum Bit Rate 70%), this method required main operand under various high target bit rate situations significantly is lower than the operand of many bit loading methods; At target bit rate during near loop Maximum Bit Rate (Maximum Bit Rate 99%), its main operand is identical with greedy bit delet method, and when target bit rate was the 60%-90% of Maximum Bit Rate, its main operand was well below greedy bit delet method.Near the loop Maximum Bit Rate when (being about more than 90% of Maximum Bit Rate), main operand is higher than greedy bit delet method to many bit loading methods at target bit rate; And when the difference of target bit rate and loop Maximum Bit Rate increased, the operand of greedy bit delet method increased rapidly.In sum, this loading method operation efficiency of (60%-99% of loop Maximum Bit Rate) under high target bit rate situation obviously is better than existing optimal bit loading method.Because actual DMT system requires high speed data transfers mostly, therefore, this method is a kind of very practical DMT system optimal power Bit distribution method.

Test loop	Target bit rate	Many bits load		This method		Main operand relatively
									The additions and deletions of many bits	Greedy bit additions and deletions	The parallel bit deletion	Greedy bit additions and deletions	Many bits load	This method	Greedy bit deletion
		T1.601 #9	1568	1	172	0	16	172								16	16
1426	1								219	0.7	5	219	5	158
			1267	1	60	0.84	20	60							20	317
1109	1								121	0.95	70	121	70	475
			950	1	182	0.95	89	182							89	634
T1.601 #13	1544								1	154	0	16	154	16			16
		1404	1	200	0.7	3	200	3							156
	1248								1	44	0.83	24	44	24		312
		1092	1	107	0.95	78	107	78							468
	936								1	171	0.95	78	171	78		624
		CSA #7	1633	1	190	0	16	124							16		16
1484	1								224	0.63	27	224	27	165
			1319	1	59	0.79	19	59							19	330
1154	1								99	0.9	13	99	13	495
			989	1	153	0.97	62	153							62	660
CSA #8	1625								1	181	0	16	181	16			16
		1477	1	216	0.64	23	216	23							164
	1313								1	52	0.79	13	52	13		328
		1149	1	93	0.9	21	93	21							492
	985								1	148	0.98	72	148	72		656
		Mid -CSA	1717	1	120	0	17	120							17		17
1561	1								118	0.42	80	118	80	173
			1387	1	127	0.79	61	127							61	347
1214	1								159	0.98	301	159	301	520
			1040	1	204	0.98	127	204							127	694

The main operand that table 1 target bit rate is got 99%, 90%, 80%, 70% and 60% o'clock this method of loop Maximum Bit Rate and many bit loading methods and greedy bit delet method respectively relatively

Claims (1)

1. the comprehensive bit position loading method of discrete multi-audio frequency modulating system optimal power division, at target bit rate is the discrete multi-audio frequency modulating system of the 60%-90% of system's Maximum Bit Rate, it is characterized in that: described method is to realize on the digital integrated circuit chip of this system's transmitting terminal as the Bit Allocation in Discrete circuit, comprises following steps successively:

Step (1), Maximum Bit Rate loads, and contains following steps successively:

Step (11) is according to signal to noise ratio difference Γ, subcarrier n place subchannel gains noise ratio CNR _n, the maximum power spectral densities Φ of system and subchannel bandwidth F, be calculated as follows each subcarrier, the number of bits b of n by the Φ decision _n, n=1,2 ..., M,

Described CNR _n, Φ and F be set point, Γ is by the aiming symbol error probability P that sets _e, signal to noise ratio allowance γ _mWith coding gain γ _cCommon definite, provide by following formula:

$\mathrm{\&Gamma;}={10\log }_{10}\left(\frac{{\left[Q^{-1}(P_e/2)\right]}^2}{3}\right)+{\mathrm{\&gamma;}}_m-{\mathrm{\&gamma;}}_c;Q\left(x\right)=\frac{1}{\sqrt{2\mathrm{\&pi;}}}{\&Integral;}_x^{\&infin;}{e}^{{-t}^2/2}\mathrm{dt}$ , Q ^-1(x) be the inverse function of Q (x), x=P _e/ 2;

Step (12) is calculated as follows the number of bits b of each subcarrier n _n, M altogether, n=1,2 ..., M,

b _n=min (b _Max, b _n); b _MaxNumber of bits for the maximum qam constellation size decision set;

Step (13), the computing system bit rate $B=\underset{n=1}{\overset{M}{\mathrm{\&Sigma;}}}{b}_n$ , this moment, B was system's Maximum Bit Rate: if B≤B _T, then bit loads and finishes; Otherwise, the difference Bdiff=B-B of calculating Maximum Bit Rate and target bit rate _T, execution in step (2) again;

Step (2), Bit Allocation in Discrete is quickened, and described bit rate accelerating ated test process contains following steps successively:

Step (21) is according to each subcarrier number of bits b of maximum rate bit load phase _nWhether surpass b _Max, the sequence number of subcarrier is divided into two classes, be placed on set respectively

With In, ask set With

The number of middle element, i.e. set

With

Radix, wherein:

$\tilde{N}=\{n:{\stackrel{\&OverBar;}{b}}_n>b_{\max },n=\mathrm{1,2},...,M\}$ Be maximum rate bit load phase subcarrier number of bits b _nSurpass b _MaxThe set of subcarrier sequence number;

$\underset{~}{N}=\{n:0<{{\stackrel{\&OverBar;}{b}}_n\&le;b}_{\max },n=\mathrm{1,2},...,M\}$ , be maximum rate bit load phase subcarrier number of bits b _nBe no more than b _MaxAnd the set of subcarrier sequence number greater than zero;

The expression set Radix;

The expression set

Radix;

Ask the value of loading parameters u as follows:

Step (211), if $\tilde{L}=0$ , be calculated as follows the value of u:

Step (212), if $\tilde{L}\&NotEqual;0$ , be calculated as follows the u value:

$v=\underset{n\&Element;\tilde{N}}{\max }({\stackrel{\&OverBar;}{b}}_n-b_{\max })$ Be b _nWith b _MaxThe maximum of difference, $n\&Element;\tilde{N};$

Step (22) is carried out the parallel bit deletion according to the following steps, obtains new number of bits b _n:

Step (221) according to the result of step (211) or (212), is set with sequence number

The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _n, n=1,2 ..., M;

Step (222) is in the step (221), if u＞1 is set with sequence number ${\tilde{N}}_{s1}=\{n:b_{\max }<{\stackrel{\&OverBar;}{b}}_n{<b}_{\max }+u,n\&Element;\tilde{N}\}$ The number of bits deletion u-(b of each subcarrier of middle element _n-b _Max) bit, promptly sequence number is

The subcarrier number of bits of middle element is reduced to b _n-u obtains new number of bits b _n

Step (23) is with b _nThe bit position zero of the subcarrier n of＜0 correspondence obtains new number of bits b _n, and the new bit rate of computing system $B=\underset{n=1}{\overset{M}{\mathrm{\&Sigma;}}}{b}_n;$

Step (24) is calculated new Bdiff=B-B _T, if Bdiff=0, the bit loading procedure finishes; If Bdiff＜0, then execution in step (3); If Bdiff＞0, the initial value with loading parameters u leaves in the Δ earlier, i.e. Δ=u asks the new value of loading parameters u then according to the following steps:

Step (241) is asked the parallel bit deletion new number of bits b in back _nSet for the subcarrier sequence number of positive integer ${\underset{~}{N}}_s^{+}=\{n:0<b_n,n\&Element;\underset{~}{N}\}$ And radix

Step (242), ask the new value of u by following formula:

Step (25), if the parallel bit deletion is carried out in u ≠ 0, otherwise execution in step (4); The parallel bit deletion contains following steps successively:

Step (251) is if u ≠ 0 is set with sequence number ${\underset{~}{N}}_s^{+}\&cup;{\tilde{N}}_{s1}$ The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _n

Step (252), if u ≠ 0 and $\tilde{L}-{\tilde{L}}_{s1}\&NotEqual;0,$

Be set Radix, with sequence number for the set ${\tilde{N}}_{s2}=\{n:{\stackrel{\&OverBar;}{b}}_n=b_{\max }+\mathrm{\&Delta;},n\&Element;\tilde{N}\}$ The number of bits deletion u bit of each subcarrier of middle element obtains new number of bits b _nOtherwise, execution in step (26);

Step (253), if u ≠ 0, $\tilde{L}-{\tilde{L}}_{s1}\&NotEqual;0,$ $\tilde{L}-{\tilde{L}}_{s1}-{\tilde{L}}_{s2}\&NotEqual;0,$

Be set

Radix, with sequence number for the set ${\tilde{N}}_{s3}=\{n:b_{\max }+\mathrm{\&Delta;}<{\stackrel{\&OverBar;}{b}}_n{<b}_{\max }+\mathrm{\&Delta;}+u,n\&Element;\tilde{N}\}$ The number of bits of each subcarrier of middle element is reduced to b _n-Δ-u, described u are new value, obtain new number of bits b _nOtherwise, execution in step (26);

Step (26) is with b _nThe number of bits zero setting of each subcarrier n of＜0 correspondence obtains new number of bits b _n, calculate new $B=\underset{n=1}{\overset{M}{\mathrm{\&Sigma;}}}{b}_n$ With new Bdiff=B-B _T, if Bdiff=0, then bit loads and finishes; If Bdiff＜0, then execution in step (3); Otherwise the value of loading parameters u is upgraded in (241) set by step-(242), and u=0 is generally arranged, therefore also direct execution in step (4);

Step (3) is set in sequence number ${\tilde{N}}_p=\{n:0\&le;b_n{<b}_{\max },n=\mathrm{1,2},...,M\}$ In carry out between the subcarrier of element | Bdiff| greedy bit increase, execution in step (5) then, described greedy bit increase contains following steps successively:

Step (31) determines to increase the required transmitted power increment Delta of 1 bit P _n ⁺(b _n) minimum subcarrier sequence number n ⁺, $n\&Element;{\tilde{N}}_p,$ Promptly $n^{+}=\arg \left\{\underset{n\&Element;{\tilde{N}}_p}{\min }\right[\mathrm{\&Delta;}{P}_n^{+}\left(b_n\right)\left]\right\}$ The independent variable of arg representative function, $\arg \left\{\underset{n\&Element;X}{\min }\right[f\left(n\right)\left]\right\}$ Representative function f (n), n ∈ X, the independent variable of minimum value correspondence;

Be calculated as follows for the first time described transmitted power increment Delta P _n ⁺(b _n):

$\mathrm{\&Delta;}{P}_n^{+}\left(b_n\right)=2^{b_n}\frac{\mathrm{\&Gamma;}}{{\mathrm{CNR}}_n},$ 0≤b _n＜b _max；

Step (32) is with n ⁺The bit of individual subcarrier increases by 1, promptly $b_{n^{+}}=b_{n^{+}}+1;$

Step (33), if $b_{n^{+}}{<b}_{\max }$ , then will

Be updated to 2 times of initial value; Otherwise, will Value be changed to infinity; Return step (31) then;

Step (4) is set in sequence number ${\underset{~}{N}}_p=\{n:0<b_n\&le;b_{\max },n=\mathrm{1,2},...,M\}$ In carry out Bdiff greedy bit deletion between the subcarrier of element, execution in step (5) then, described greedy bit is deleted and is contained following steps successively:

Step (41) determines to reduce the required transmitted power decrement of 1 bit Δ P _n ^-(b _n), $n\&Element;{\underset{~}{N}}_p$ , maximum subcarrier sequence number n ^-, promptly $n^{-}=\arg \left\{\underset{n\&Element;{\underset{~}{N}}_p}{\max }\right[{\mathrm{\&Delta;P}}_n^{-}\left(b_n\right)\left]\right\};$

Be calculated as follows for the first time described transmitted power decrement Δ P _n ^-(b _n):

$\mathrm{\&Delta;}{P}_n^{-}\left(b_n\right)=2^{(b_n-1)}\frac{\mathrm{\&Gamma;}}{{\mathrm{CNR}}_n},$ 0＜b _n≤b _max；

Step (42) is with n ^-The bit of individual subcarrier reduces 1, promptly $b_{n^{-}}=b_{n^{-}}-1;$

Step (43), if $0{<b}_{n^{-}}$ , then with Δ P _N- ^-(b _N-) be updated to 1/2 of initial value; Otherwise, with Δ P _N+ ⁺(b _N+) value be changed to zero; Return step (41) then;

Step (5), the bit fine setting stage, realize the minimum transmit power Bit Allocation in Discrete, described bit fine setting contains following steps successively:

Step (51) determines that sequence number is set ${\tilde{N}}_p=\{n:0\&le;b_n<b_{\max },n=\mathrm{1,2},...,M\}$ The number of bits of each subcarrier of middle element increases the required transmitted power increment Delta of 1 bit P respectively _n ⁺(b _n), 1≤n≤M, minimum subcarrier sequence number n ⁺, promptly $n^{+}=\arg \left\{\underset{n\&Element;{\tilde{N}}_p}{\min }\right[{\mathrm{\&Delta;P}}_n^{+}\left(b_n\right)\left]\right\};$

Step (52) determines that sequence number is set ${\underset{~}{N}}_p=\{n:0{<b}_n{\&le;b}_{\max },n=\mathrm{1,2},...,M\}$ The number of bits of each subcarrier of middle element reduces the required transmitted power decrement of 1 bit Δ P respectively _n ^-(b _n), 1≤n≤M, maximum subcarrier sequence number n ^-, promptly $n^{-}=\arg \left\{\underset{n\&Element;{\underset{~}{N}}_p}{\max }\right[\mathrm{\&Delta;}{P}_n^{-}\left(b_n\right)\left]\right\};$

Step (53), if ${\mathrm{\&Delta;P}}_{n^{+}}^{+}\left(b_{n^{+}}\right)<\mathrm{\&Delta;}{P}_{n^{-}}^{-}\left(b_{n^{-}}\right)$ , then carry out described step (531)-(534) successively; Otherwise Bit Allocation in Discrete finishes;

Step (531) is with n ⁺The number of bits of individual subcarrier increases by 1, promptly $b_{n^{+}}=b_{n^{+}}+1;$

Step (532) is with n ^-The number of bits of individual subcarrier reduces 1, promptly $b_{n^{-}}=b_{n^{-}}-1;$

Step (533), if $b_{n^{+}}{<b}_{\max }$ , then with Δ P _N+ ⁺(b _N+) be updated to 2 times of initial value; Otherwise, with Δ P _N+ ⁺(b _N+) value be changed to infinity;

Step (534), if $0{<b}_{n^{-}}$ , then with Δ P _N- ^-(b _N-) be updated to 1/2 of initial value; Otherwise, with value be changed to zero; And return step (51).

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