CN1881562A - Method for extracting interconnection parasitic capacitance capable of automatically adapting process characteristic size - Google Patents

Abstract

The invention relates to a linked parasitic capacitance extracting method, which can automatically adapt characteristic size, belonging to the integrated circuit computer aided design, wherein arrange the scan band width reduced in ratio with the characteristic size to save memory; reduce the environment conductor horizontally according to the characteristic size after cutting to improve the capacitance extracting speed, and increase the environment conductor longitudinally to improve the extracting accuracy; then divide the edge length from the relative length of characteristic size, to be divided with edge unit to improve the extracting accuracy; at last, solve the discrete edge integral equation to obtain the parasitic capacitance between conductors to improve the property of linked parasitic capacitance extracting program.

Description

A kind of method for extracting interconnection parasitic capacitance of automatically adapting process characteristic size

Technical field

A kind of method for extracting interconnection parasitic capacitance of automatically adapting process characteristic size belongs to the interior interconnection line parasitic parameter extractive technique field of chip in the integrated circuit CAD (IC-CAD).

Background technology

Development along with the semiconductor integrated circuit technology, ripe manufacturing process has reached below the 90nm, circuit work frequency is more and more higher, constantly the reducing of the growth of the depth-width ratio of interconnection line and distance between centers of tracks in the circuit, the parasitic Electromagnetic Environmental Effect of interconnection line has become the principal element of circuit performances such as influence such as time delay, power consumption, power supply integrality and signal integrity.Therefore, in the design cycle of integrated circuit, must consider the influence of interconnection line ghost effect to circuit.

The design of current integrated circuit at first proposes functional description at front end, carries out logic synthesis, functional verification.If functional verification can't reach the functional requirement of setting originally, also to get back to the front and correct logical design, repeat an iterative process; Carry out layout design in the rear end and obtain a domain of describing the semiconductor technology structure, domain is made Design Rule Checking, the electricity rule is checked and layout verifications such as parasitic parameter extraction and circuit simulation.If domain satisfies the performance requirement of design originally, can pay Foundry and manufacture, correct layout design or logical design otherwise turn back to the front.The parasitic parameter extraction is an important step in the layout verification, for layout verification provides as far as possible near electrical parameters such as real interconnection resistance, electric capacity and inductance.The parasitic parameter that the adding Front-end Design is ignored when emulation could reflect the actual operation state of chip accurately, reduces the possibility of throwing the sheet failure to greatest extent.

The calculating of interconnection dead resistance is simple relatively, though and the research that inductance calculates is started in the beginning of the seventies, just cause people's attention as of late gradually.At present, in influencing all electrical parameters of circuit performance, people are concerned about that maximum parasitic capacitances that are still calculate.

Current, the interconnection capacitance computational chart under the deep submicron process technical conditions reveals following characteristics:

1. high density of integration promptly comprises the insulating barrier of nearly ten kinds of differing dielectric constants and tens of, hundreds of so that thousands of metallic conductor pieces in very little interconnection parasitic capacitance device.

2. high labyrinth, this shows the shape of shape of medium and mutually nested relation and conductor block and mutually on the complexity of geometrical relationship.It shows very outstanding in the calculating of labyrinths such as conformal dielectric, shallow moat substrate and dynamic random memory.

3. extensive, this shows two aspects.The one, contained medium of each capacitor and number of conductors are often very big; Two is that the number of a critical path (Critical Path) or one section contained interconnection capacitance device of gauze is also often very big.At present, the contained number of capacitors of critical path can reach thousands of so that tens thousand of.

These characteristics propose higher requirement to algorithm and software, that is:

1. high calculating speed.

2. higher labyrinth adaptability.

3. higher result reliability can rely on experiment or measure the correctness of verifying result of calculation.

The computational methods of parasitic capacitance can be divided into two classes substantially: analytic modell analytical model method and Method for Numerical.

The analytic modell analytical model method obtains the analytic modell analytical model formula based on experiment, measurement or The results of numerical simulation by methods such as interpolation and curve fits.Its computational speed is fast, but precision is lower, is difficult to accurately handle the complex three-dimensional structure.

Method for numerical simulation calculates interconnection capacitance by finding the solution field equation.Its precision height can adapt to very complicated three-dimensional structure, but computational speed is lower.

The method for numerical simulation of finding the solution field equation has finite difference calculus (Finite Difference Method, FDM), Finite Element, measurement equation invariance method (Measured Equation of Invariance, MEI), walk random method (Random Walk, or Monte Carlo) with boundary element method (Boundary Element Method, BEM) etc.

At present, boundary element method is widely used in interconnection resistance, electric capacity calculates to form and is prevailing numerical method.Boundary element method is a kind of border discretization method, has to calculate the distinguishing feature that dimension reduces one dimension, and is different from discrete region methods such as finite difference and finite element with this.

In recent years, the boundary Element of interconnection capacitance has obtained many achievements and progress, mainly shows the following aspects:

1. raising computational speed, its main promotion are derived from multipole accelerating algorithm that people such as Nabors proposed Rokhlin in 91 years and are successfully applied to three-dimensional capacitance and extract (the FastCap parasitic capacitance is extracted software).In addition, also have the strong virtual multi-medium algorithm of analogy literary composition, and the quick hierarchy type algorithm of Shi Weiping etc.

2. the research of self-adaptive computing method in order to guarantee result reliability, improves the precision of separating.The groundwork of this respect have " Jinsong Hou; Zeyi Wang and Xianlong Hong; ' The Hierarchical h-Adaptive 3-D BoundaryElement Computation of VLSI Interconnect Capacitanee '; in Proceedings of ASP-DAC ' 99; pp93-96,1999 ".

3. utilize boundary element method to set up the macro model matrix of interconnecting unit, decomposing domain then is a plurality of interconnecting units, and the variable that merges the macro model matrix of each unit correspondence and cancellation element interface obtains the electric capacity on the conductor.The groundwork of this respect have " Dai Binhua, Lu Taotao, Wang Zeyi, Hong Xianlong, ' new way of 3D interconnection capacitance rapid extraction---medium building blocks storehouse method ', computer-aided design and graphics journal. the 16th the volume, the 3rd phase, pp343-347,2004 ".

The basic step that DIRECT BOUNDARY ELEMENT is calculated parasitic capacitance comprises:

1. handle input domain and technical papers, the two-dimensional geometry body in the domain is made necessary geometric operation, the combined process fileinfo forms three-dimensional interconnection parasitic capacitance model.In interconnection parasitic capacitance calculated, circuit designer was often paid close attention to the conductor (being called leading body) and its coupling capacitance between certain distance inner wire (being called the environment conductor) on every side on the critical path.To an actual domain, because it is on a grand scale, often a critical path or gauze to be cut into plurality of sections, calculated respectively then.In the every segment structure that cuts down, generally be that a leading body is embedded in the different multilayer insulation media with some environment conductors, be called an interconnection parasitic capacitance model.

At first with every gauze of each interconnection layer on the scanning strip algorithm cutting domain, the gauze part in the current sweep bandwidth scope will be cut into conductor segment.The scanning strip width need manually be specified or can't help artificial the appointment and be got a fixing empirical value.In the every section two-dimensional structure that cuts down, comprise the leading body section and the environment conductor segment of certain distance on every side.Distance between environment conductor segment and the leading body section is less than a default empirical value.Under 0.5um feature process size, recommendation will be that 5um gets with all interior conductor segment and makes the environment conductor apart from the leading body segment distance.

Utilize the information of technical papers and the every section two-dimentional domain structure that cuts down then, the All Media that will be from bottom substrate (special conductive surface) to top layer and the interconnection parasitic capacitance model of a three-dimensional of conductor generation.The three-dimensional interconnection parasitic capacitance model that the electric capacity extracting tool that has generates only comprises conductor and the medium with leading body layer adjacent layer, to accelerate extraction rate.After generating three-dimensional interconnection parasitic capacitance model, will form All Media and surface of conductors and divide to make boundary element.

2. the boundary element division is done on the enantiomorph surface.For the surface of each conductor or medium, according to the umber of cutting apart of appointment, even or heterogeneous is the boundary element that specifies number with surperficial subdivision.The body boundary element speed of dividing directly has influence on the whole speed of finding the solution, and it is divided quality the speed and the precision of subsequent calculations also had very direct influence.The boundary element of body is divided should be under the prerequisite that guarantees the subsequent calculations precision, the number of the minimizing boundary element of maximum possible, thus the variable number after minimizing is dispersed accelerates to find the solution speed.At present, the boundary element on each limit is cut apart umber and is determined by the body character under the length of side and this limit on the surface.

3. make the boundary element integration, form the coefficient matrix and the right-hand member vector of linear algebraic equation group.

4. the group of solving an equation obtains the normal electric field intensity of conductive surface.

5. calculate parasitic capacitance by the normal electric field intensity of conductive surface.

Extract in the step 1 of parasitic capacitance in above-mentioned Direct Boundary Element Method, the scanning strip width of cutting gauze is the fixedly default value of appointment of dependence user experience or program setting, and the fixed-bandwidth of program setting can only keep computational efficiency under some technology characteristics size.Along with constantly dwindling of technology characteristics size equal proportion, conductor hop count in the fixing scanning strip width scope must be multiplied, and all conductors in the scanning strip scope all will be read into internal memory, cause the algorithm memory cost to be multiplied, and reduce the operational efficiency of parasitic capacitance extraction procedure.Though manually specify a suitable scanning strip width can keep the runnability of program, but this makes each domain to the different characteristic process all need manually to specify the sweep bandwidth degree, and the performance of the parasitic capacitance extraction procedure of Direct Boundary Element Method depends on user's experience to a great extent.

Extract in the step 1 of parasitic capacitance in above-mentioned Direct Boundary Element Method, if the distance of near the conductor the leading body section and leading body section is less than within the default empirical value, to be considered the environment conductor and cut in the lump in the two-dimentional physique structure, be added into then in the three-dimensional interconnection parasitic capacitance model.The environment conductor that joins in the three-dimensional interconnection parasitic capacitance model is many more, and parasitic capacitance is calculated accurate more, and computational speed is slow more.When the environment conductor number that joins the interconnection parasitic capacitance model is increased to certain value, it is very slow to extract the precision increase, and extraction rate then reduces greatly.The default upper limit of distance between environment conductor of setting in the step 1 and the leading body section, generally can add abundant environment conductor to the interconnection parasitic capacitance model, guarantee the precision that parasitic capacitance is extracted, but can not adjust the upper limit of environment conductor and the intersegmental distance of leading body automatically according to the technology characteristics size of domain.Along with constantly dwindling of technology characteristics size, and the upper limit of environment conductor and the intersegmental distance of leading body is constant, must add too much environment conductor to the interconnection parasitic capacitance model.The result has sacrificed the CPU time of several times so that tens of times obtaining minimum precision improvement.

Extract in the step 1 of parasitic capacitance in general Direct Boundary Element Method, in the three-dimensional interconnection parasitic capacitance model of generation or comprise and the conductor and the medium of all layers perhaps only comprise conductor and medium with leading body layer and adjacent layer.The three-dimensional parasitic capacitance model that only comprises leading body layer and adjacent bed conductor and medium can accurately be simulated more than 0.18um technology, and the error of this model is bigger below 0.18 technology.The three-dimensional parasitic capacitance model that comprises the medium of all layers and conductor is very accurate, but simulated time is greater than the three-dimensional parasitic capacitance model that only comprises leading body adjacent bed conductor and medium.Along with increasing of the medium number of plies of domain, the simulated time that comprises the three-dimensional parasitic capacitance model of All Media layer and conductor layer may increase several times or more.

Extract in the step 2 of parasitic capacitance in above-mentioned Direct Boundary Element Method, the character on border, boundary element place and the influencing factors such as length on border have only been considered in the division of boundary element, do not consider the influence of different domain feature process sizes.With the leading body is example, and the boundary element that provides each limit is cut apart the umber formula:

S _x＝Min{4ln(Length _x+2.2)，20}

S _y＝Min{4ln(Length _y+2.2)，20}

S _z＝Min{Max{4·Length _z，3}，6}

Wherein, S _x, S _y, S _zRepresent body respectively along x, y, z is axial to divide umber with reference to boundary element.Min{} gets minimum value function, and Max{} gets max function, and ln () is for taking from right logarithmic function.Length _x, Length _y, Length _zBe respectively each body along x, y, the axial length of z, um gets in unit."   " rounds symbol under being.Along with reducing of domain technology characteristics size, the height and width of conductor all can constantly reduce, and each length of side of the leading body section that cuts down also constantly reduces, and are example with 90nm technology, and the boundary element on each limit of leading body section is divided umber and equaled:

S _x＝Min{4ln(Length _x+2.2)，20}＝4

S _y＝Min{4ln(Length _y+2.2)，20}＝4

S _z＝Min{Max{4·Length _z，3}，6}＝4

Boundary element on the leading body section that makes is divided too sparse, has influenced the precision that follow-up Direct Boundary Element Method is calculated parasitic capacitance value.

To sum up, general Direct Boundary Element Method parasitic capacitance extraction procedure can reach the extraction precision of appointment with too much CPU time and memory cost along with the minimizing of domain technology characteristics size, and is poor to the automatic adaptive capacity of different process characteristic size.

Summary of the invention

In order to overcome the deficiency of present interconnection parasitic capacitance extraction procedure to different process characteristic size adaptive ability difference.The utility model provides a kind of interconnection parasitic capacitance extraction procedure, can be according to the feature process size of input domain, the width of scanning strip in the Automatic Optimal cutting algorithm, optimize near choosing of the horizontal direction environment conductor of leading body, optimize choosing of parasitic capacitance model inner conductor layer, dielectric layer, optimize the division of body surface-boundary unit, improve the speed of service and precision that parasitic capacitance is extracted on the whole, the use of save memory.

The technical scheme that its technical problem that solves the utility model adopts is:

At first the program pretreatment stage before setting up three-dimensional interconnection parasitic capacitance model uses and the proportional sweep bandwidth scanning domain that dwindles of the technology characteristics size of input domain.The technology characteristics size of input domain is read in from the technical papers of input.When cutting the environment conductor of crucial gauze ambient level direction in the scanning strip, set Δ _CapTake as the leading factor allowed between body and the environment conductor apart from the upper limit; Apart from upper limit Δ _CapValue with the input domain proportional the dwindling of technology characteristics size.When choosing in the scanning strip around the crucial gauze environment conductor of short transverse, by feature process size S _fDetermine that concrete formula is as follows:

Leading body is finally formed three-dimensional interconnection parasitic capacitance model with some environment conductors in being embedded in different multilayer insulation media.

Then when adopting boundary element method simulation three-dimensional interconnection parasitic capacitance model, with the body length of side divided by feature process size S _fRelative length replace the foundation that its absolute growth is divided as boundary element.The concrete formula that boundary element is divided is:

1) body is a medium:

S _x＝Min{Length _x/S _f，10}

S _y＝Min{Length _y/S _f，10}

S _z=Min{  Length _z/ S _f if this medium of 6} comprises the adjacent layer of leading body or leading body place layer, then works as S _zGot 3 less than 3 o'clock.

Wherein, Min{} gets minimum value function, Length _x, Length _y, Length _zBe respectively each body along x, y, the axial length of z, um gets in unit.S _fTechnology characteristics size for domain."   " is following rounding operation symbol.(down together)

2) body is taken body as the leading factor:

S _x＝Min{4ln(Length _x/S _f+2.2)，20}

S _y＝Min{4ln(Length _y/S _f+2.2)，20}

S _z＝Min{Max{4·Length _z/S _f，3}，6}

Wherein, ln () is for taking from right logarithmic function, and Max{} gets max function.(down together)

3) body is the environment conductor:

If environment conductor block and leading body piece belong to a dielectric layer together,

S _z＝Min{Max{4·Length _z/S _f，3}，6}

If environment conductor block and leading body piece do not belong to a dielectric layer,

S _z＝Min{2·Length _z/S _f，6}

4) body is a metal substrate:

If it is adjacent with leading body place dielectric layer,

S _x＝Min{1.5·Length _x/S _f，20}

S _y＝Min{1.5·Length _y/S _f，20}

If it is not adjacent with leading body place dielectric layer,

S _x＝Min{1.5·Length _x/S _f，15}

S _y＝Min{1.5·Length _y/S _f，15}

To this conductive surface of metal substrate, z is axial to divide umber S with reference to boundary element _zNonsensical.

After such boundary element division, this method is the same with common boundaries unit method, begin to set up the boundary integral equation of discretization, find the solution the normal electric field intensity distributions that this boundary integral equation obtains conductive surface, normal electric field intensity is obtained the parasitic capacitance and the output of conductor do integral operation at conductive surface.

The beneficial effect of this method is:

1. on the cutting domain during near the environment the crucial gauze, use with the proportional scanning strip width of domain technology characteristics size and scan, make the number of conductor and the domain process equal proportion that enter in the scanning strip sphere of action reduce.Because the scanning strip algorithm only reads in the conductor geological information in the scanning strip sphere of action worksheet of internal memory, the corresponding minimizing of internal memory that the minimizing of number of conductor consumes the scanning strip algorithm.

2. along with constantly the reducing of technology characteristics size of input domain, the intersegmental equal proportion apart from the upper limit of environment conductor and leading body reduces can avoid adding too much environment conductor to three-dimensional interconnection parasitic capacitance model.Under the situation of not sacrificing any extraction precision, obtained consequently tens of times speed lifting of several times.

3. along with the reducing of technology characteristics size of input domain, the number of environment conductor layer had both guaranteed the precision that electric capacity extracts on the expansion short transverse of equal proportion, again the speed extracted of the raising electric capacity of maximum possible.

4. the foundation of dividing as boundary element divided by the relative length of the feature process size of input domain with the body length of side can be avoided such situation: along with reducing of the technology characteristics size of importing domain, the division of boundary element is too sparse, finally reduces the precision that parasitic capacitance is extracted.

Description of drawings

Below in conjunction with drawings and Examples the utility model is further specified.

Fig. 1 is that the parasitic capacitance of automatically adapting process characteristic size is extracted flow chart.

Fig. 2 is input domain schematic diagram.

Fig. 3 is the interconnection structure schematic diagram under cutting from domain.

Fig. 4 is a three-dimensional interconnection parasitic capacitance model schematic diagram.

1. leading bodies, 2. environment conductors, 3. medium outer surfaces, 4. dielectric interfaces, 5. substrates among the figure

Embodiment

Get among the embodiment following steps that the utility model is carried out successively by computer shown in Figure 1:

1) reads in the technology characteristics size S that imports domain from technical papers _fFig. 2 is the schematic diagram of input domain.

2) scan whole domain from left to right with the vertical scanning band.

The width W of scanning strip in this method _SbBe set at the feature process size that is proportional to domain.

Scanning strip width W in this method _SbRecommendation be 60 * S _f

Scanning strip stops at each website.The scanning strip website is the left and right sides end points on domain upper conductor limit and the intersection point between the conductor limit.When scanning strip stops at each website, do following action:

A) read in all conductors of originating in current scanning strip right-hand member worksheet to internal memory.

B) deletion ends at all conductors of current scanning strip left end from worksheet, and discharges shared internal memory.

C) from worksheet, delete the part that is positioned at current scanning strip left end in all conductors of crossing over current scanning strip left end, keep remaining part in worksheet.

D) in the body of work at present table, find out all and current scanning strip left end distance less than Δ _CapConductor form a conductor set, all belong to the conductor of crucial gauze as leading body in the conductor set; To each leading body (1), cutting leading body (1) is Δ on every side _CapEach layer environment conductor (2) in the worksheet in the scope forms a two-dimensional geometry structure.Be no more than Δ apart from leading body around comprising leading body (1) and leading body in this two-dimensional geometry structure _CapEach layer environment conductor (2), together as the two-dimensional simulation environment of this leading body.The two-dimentional interconnection geometries schematic diagram of Fig. 3 for obtaining after the domain cutting.

Δ wherein _CapTake as the leading factor allowed between body (1) and the environment conductor (2) apart from the upper limit, the conductor that exceeds this distance range can be as the environment conductor.

Δ in this method _CapValue should be proportional to domain feature process size.

Δ in this method _CapRecommendation be 5 * S _f

3) for step 2) in each two-dimensional geometry structure of cutting out, the combined process fileinfo generates three-dimensional interconnection parasitic capacitance model.The information of two-dimensional geometry structure input comprises conductor and medium position coordinates and the geometrical length in XOY plane.The information of technical papers input comprises the dielectric coefficient of each layer medium, the origin coordinates of height and z axle.The information of technical papers input also comprises the height of each layer conductor and the origin coordinates of z axle.The three-dimensional interconnection parasitic capacitance model that generates is that a leading body (1) is embedded in the different multilayer insulation media with some environment conductors (3), places a three-dimensional cartesian coordinate system.And make the x that is parallel to coordinate system of the limit correspondence of cuboid, y, three axles of z.

In this three-dimensional interconnection parasitic capacitance model, must comprise all conductors of leading body place layer and the medium that comprises this layer, also comprise all conductors of the interconnection layer adjacent and the medium that comprises these conductors with leading body place layer.Whether the conductor of other interconnection layers and the medium that comprises conductor are included in the three-dimensional interconnection parasitic capacitance model by feature process size S _fDetermine that concrete formula is as follows:

Behind the dielectric layer of having determined to comprise in the three-dimensional parasitic capacitance model and conductor layer, from technical papers, read the height of respective media layer and conductor layer, in conjunction with the two-dimensional geometry structure that cuts out, form six surfaces of All Media and conductor in the three-dimensional parasitic capacitance model.

Fig. 4 is the schematic diagram of an interconnection parasitic capacitance model of domain cutting back generation, has 5 conductors to be embedded in and contains in 3 layers of medium of substrate (5).Here, substrate (5) is counted as a special conductor, and it only is made of a face.The interconnection parasitic capacitance device is generally surrounded by three kinds of borders: conductive surface (1) (2), and be called and force the border, satisfy the Dirichlet boundary condition, be designated as Γ _u, electromotive force is determined by bias voltage on it, is known; Medium outer surface (3) is called natural boundary, satisfies the Neumann boundary condition, is designated as Γ _q, normal electric field intensity is constant 0 on it; And dielectric interface (4), be positioned at the intersection of two kinds of different mediums, be designated as Γ _I, electromotive force and normal electric field intensity are all the unknown on it.

With the interconnection parasitic capacitance model of certain bias voltage, its Potential Distributing can be used the Laplace's equation of band mixed boundary condition

Describe:

Wherein, wait to separate territory Ω=∪ Ω _k, Ω _kBe the zone that medium k is occupied, M is contained medium sum.U is an electromotive force, and q= u/  n represents border surface normal electric field intensity, and n is the outer normal direction of border units.ε _kIt is the dielectric constant of medium k.At dielectric interface Γ _IOn, subscript a and b represent respectively its adjacent two media.

4) it is as follows to make the method that boundary element divides for each the body surface in the three-dimensional interconnection parasitic capacitance model in the step 3):

Body in the three-dimensional interconnection parasitic capacitance model can be divided into conductor block according to the difference of analytic target, a kind of in three kinds of bodies of metal substrate or medium.If S _x, S _y, S _zRepresent body respectively along x, y, z is axial to divide umber with reference to boundary element.Distinguish different bodies below, introduce S _x, S _y, S _zCalculating:

A) medium:

S _x＝Min{Length _x/S _f，10}

S _y＝Min{Length _y/S _f，10}

S _z=Min{  Length _z/ S _f if this medium of 6} comprises the adjacent layer of leading body or leading body place layer, then works as S _zGot 3 less than 3 o'clock.

Wherein, Min{} gets minimum value function, Length _x, Length _y, Length _zBe respectively each body along x, y, the axial length of z, um gets in unit.S _fTechnology characteristics size for domain."   " is following rounding operation symbol.(down together)

B) conductor segment of composition leading body:

S _x＝Min{4ln(Length _x/S _f+2.2)，20}

S _y＝Min{4ln(Length _y/S _f+2.2)，20}

S _z＝Min{Max{4·Length _z/S _f，3}，6}

Wherein, ln () is for taking from right logarithmic function, and Max{} gets max function.(down together)

C) environment conductor block:

If environment conductor block and leading body piece belong to a dielectric layer together,

S _z＝Min{Max{4·Length _z/S _f，3}，6}

If environment conductor block and leading body piece do not belong to a dielectric layer,

S _z＝Min{2·Length _z/S _f，6}

4) metal substrate:

If it is adjacent with leading body place dielectric layer,

S _x＝Min{1.5·Length _x/S _f，20}

S _y＝Min{1.5·Length _y/S _f，20}

If it is not adjacent with leading body place dielectric layer,

S _x＝Min{1.5·Length _x/S _f，15}

S _y＝Min{1.5·Length _y/S _f，15}

To this conductive surface of metal substrate, z is axial to divide umber S with reference to boundary element _zNonsensical.

5) make the boundary element integration, form the coefficient matrix and the right-hand member vector of linear algebraic equation group.If matter k (k=1 ..., border  Ω M) _kDiscrete is N _kIndividual boundary element (unit on the dielectric interface belongs to adjacent two media simultaneously).Each first central point is got as source point and get and make variable nodes by employing constant unit, can obtain the boundary integral equation of discretization:

$\frac{1}{2}\·u_i^k+\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{u}_j^k{\∫}_{{\mathrm{\Γ}}_j^k}{q}^{*}\mathrm{d\Γ}=\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{q}_j^k{\∫}_{{\mathrm{\Γ}}_j^k}{u}^{*}\mathrm{d\Γ},(i=1,\mathrm{\Λ},N_k,k=1,\mathrm{\Λ},M)---\left(2\right)$

Wherein, Γ _j ^kBe  Ω _kOn j boundary element.u _j ^kWith q _j ^kRepresent Γ respectively _j ^kOn electromotive force and normal electric field intensity.Two function expressions in the sign of integration are:

${u^{*}}_{\left(k\right)}=\frac{1}{4\mathrm{\π}{r}_{\left(k\right)}},q_{\left(k\right)}^{*}=\frac{\∂{u^{*}}_{\left(k\right)}}{\∂n}$

In the formula, r _(k)For boundary element k central point to boundary element Γ _j ^kThe distance of the d Γ of point.N is boundary element Γ _j ^kNormal vector outside the last unit.

Formula (1) is carried out the boundary element integration, can obtain:

$\frac{1}{2}\·u_i^k+\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{\stackrel{)}{H}}_{\mathrm{ij}}^k{u}_j^k=\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{G}_{\mathrm{ij}}^k{q}_j^k,(i=1,\mathrm{\Λ},N_k,k=1,\mathrm{\Λ},M)---\left(3\right)$

Wherein, With G _Ij ^kBe respectively with boundary element Γ _i ^kCentral point be source point, at boundary element Γ _j ^kObtain as integration, that is:

${\stackrel{)}{H}}_{\mathrm{ij}}^k={\∫}_{{\mathrm{\Γ}}_j^k}{q}^{*}\mathrm{d\Γ},G_{\mathrm{ij}}^k={\∫}_{{\mathrm{\Γ}}_j^k}{u}^{*}\mathrm{d\Γ}---\left(4\right)$

If get:

Then can obtain by (2) formula:

$\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{H}_{\mathrm{ij}}^k{u}_j^k=\underset{j=1}{\overset{N_k}{\mathrm{\Σ}}}{G}_{\mathrm{ij}}^k{q}_j^k,(i=1,\mathrm{\Λ},N_k,k=1,\mathrm{\Λ},M).---\left(6\right)$

Current potential and electric displacement condition of continuity substitution (6) with on boundary condition (electromotive force is given bias voltage on the conductor border, and normal electric field intensity is 0 on the medium external boundary) and the dielectric interface obtain one group of linear algebraic equation group:

Ax＝b， (7)

Wherein x is the electromotive force unknown on each boundary element and the vector of normal electric field intensity composition.

6) group of solving an equation obtains the normal electric field intensity of conductive surface.Find the solution system of linear equations (7) with the GMRES algorithm of pre-condition, can obtain electromotive force and normal direction field intensity on all boundary elements.

7) calculate parasitic capacitance by the normal electric field intensity of conductive surface.Charge Q _iCan obtain by following formula:

$Q_i={\∫}_{{\mathrm{\Γ}}_i}\mathrm{\ϵ}\·\frac{\∂u}{\∂n}\mathrm{d\Γ}=\underset{j=1}{\overset{N_i}{\mathrm{\Σ}}}({\mathrm{\ϵ}}_i\·\frac{{\∂u}_j}{\∂n})---\left(8\right)$

Γ wherein _iIt is the surface of conductor i.N _iIt is the sum of conductor i coboundary unit. Be the normal electric field intensity on the boundary element j.ε _jDielectric constant for the medium that comprises conductor.

Claims (6)

1. method for extracting interconnection parasitic capacitance, from domain around the crucial gauze of cutting the conductor of certain limit and medium as the two-dimensional simulation environment, the combined process file is set up three-dimensional interconnection parasitic capacitance model on the two-dimensional simulation environment then, calculates the parasitic capacitance that this capacitor model obtains crucial gauze with boundary element method at last.It is characterized in that: the following link of extracting at the dimensionally-optimised parasitic capacitance of technology characteristics of input domain: the cutting of crucial gauze two-dimensional simulation environment, the foundation of three-dimensional interconnection parasitic capacitance model, the boundary element when boundary element method calculates is divided.

2. method for extracting interconnection parasitic capacitance according to claim 1, the following steps of carrying out successively by computer when it is characterized in that cutting crucial gauze two-dimensional simulation environment:

1) reads in the technology characteristics size S that imports domain from technical papers _f

2) scan whole domain from left to right with the vertical scanning band; The width W of scanning strip _SbBe set at the feature process size S that is proportional to domain _fWhen the left and right sides end points on scanning strip each conductor limit on domain and the intersection point between the conductor limit stop, do following action:

A) read in all conductors of originating in current scanning strip right-hand member worksheet to internal memory;

B) deletion ends at all conductors of current scanning strip left end from worksheet, and discharges shared internal memory;

C) from worksheet, delete the part that is positioned at current scanning strip left end in all conductors of crossing over current scanning strip left end, keep remaining part in worksheet;

D) in the conductor of work at present table, search with current scanning strip left end distance less than Δ _CapAll conductors form a conductor set, all belong to the conductor of crucial gauze as leading body in the conductor set; To each leading body, Δ around this leading body in the cutting worksheet _CapEach layer conductor in the scope forms a two-dimensional geometry structure, as the two-dimensional simulation environment of this leading body;

Δ wherein _CapTake as the leading factor allowed between body and the environment conductor apart from the upper limit; Δ _CapValue and domain feature process size S _fBe directly proportional.

3. method for extracting interconnection parasitic capacitance according to claim 1 is characterized in that scanning strip width W _SbRecommendation be 60 * S _f

4. method for extracting interconnection parasitic capacitance according to claim 1 is characterized in that described Δ _CapRecommendation be 5 * S _f

5. method for extracting interconnection parasitic capacitance according to claim 1 is characterized in that: when setting up three-dimensional interconnection parasitic capacitance model on the two-dimensional simulation environment, the environment conductor number of plies that this capacitor model should comprise on short transverse is by feature process size S _fDetermine.

6. method for extracting interconnection parasitic capacitance according to claim 1, it is as follows to it is characterized in that the method that boundary element divides is made on each the body surface in the three-dimensional interconnection parasitic capacitance model: the body in the three-dimensional interconnection parasitic capacitance model can be divided into conductor block according to the difference of analytic target, a kind of in three kinds of bodies of metal substrate or medium; Each body is along x, y, and z is axial to divide umber by feature process size S with reference to boundary element _fDetermine with the body physical dimension.

Images