CN1874149A - Digital filter - Google Patents

Digital filter Download PDF

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CN1874149A
CN1874149A CN 200510026353 CN200510026353A CN1874149A CN 1874149 A CN1874149 A CN 1874149A CN 200510026353 CN200510026353 CN 200510026353 CN 200510026353 A CN200510026353 A CN 200510026353A CN 1874149 A CN1874149 A CN 1874149A
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data
output
selector
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CN100488049C (en
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金佑灿
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Shanghai LG Electronics Co Ltd
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Shanghai LG Electronics Co Ltd
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Abstract

Without need of calculating output delay induced, reducing size of filter, the invention combines 4Tab real filter with 1Tab plural filter into one structure of the disclosed digital filter. Especially, after combining 4Tab real filter with 1Tab plural filter, the invention decides action of real filter and plural filter based on signal of mode selection. Based on signal of mode selection, output of filter is obtained within a period of one time unit. Thus, a calculator executes two times of calculation within a symbol clock pulse (a period of one time unit). Comparing with real filter and plural filter of current filter, where one calculator executes one time of calculation, the invention can reduces amount of multiplier and adder greatly.

Description

Digital filter
[technical field]
The present invention is that the relevant filter that need not calculates the output delay that causes, and when reducing the filter size, 4Tab real filter and 1Tab complex filter is combined into the invention of the digital filter of a filter construction.
[background technology]
The digital filter that utilizes LMS (Least Mean Square lowest mean square) to adapt to algorithm that uses now be can the continuous updating coefficient filter.This digital filter is mainly used in equalizer or noise killer etc., plays a part the distortion (change in long term) that compensation channel or system cause self.
At this moment, the kind of adaptive filter can be divided into filter with real number input signal and real number coefficient and the filter with complex input signal and plural coefficient.As the Digital Television of VSB (vestigial sideband) mode, when only having real data, can use filter with real number coefficient and real number input.On the contrary, as digital cable TV, use the system of QAM (quadrature amplitude modulation) modulation all to have the data of real number and imaginary number, use is had the filter of complex input signal and plural coefficient because of using.If reveal two above-mentioned systems, just should use two kinds of filters with a chip body.
If but two systems that embody with a chip make action simultaneously, but make action selectively, just only use in two kinds of filters, all the other filters can not cut any ice.In addition, under the more situation of the Tab number of filter, filter is with dual embodiment, so the whole filter size becomes bigger, causes the obstruction that embodies, becomes the factor of system resource waste.Equally, if the filter size is bigger, the filter construction that calculates a Tab mode with symbol clock pulse also becomes the hindering factor when embodying.
[summary of the invention]
At this moment, two systems embody with a chip, if but two systems make action simultaneously, but according to user's selection, only use in two systems, just can be combined into one to two kinds of filters, according to system's kind, making the function of action with real filter and making in the function of action, use the function of the system that is suitable for selecting with complex filter with plural number input and plural coefficient with real number input and real number coefficient.In addition, if the filter of combination once calculates with interior operation with a symbol clock pulse,, become the obstruction of embodiment just according to the size of filter.Therefore, if be presented as with a symbol clock pulse and make a reckoner move twice calculating, can reduce the size of whole filter with interior.
So, the objective of the invention is to, in conjunction with 4Tab real filter and 1Tab complex filter, when cycle unit interval is with the interior output that obtains filter, make a reckoner with a symbol clock pulse (cycle unit interval) with twice calculating of interior operation, provide to need not the output delay that filter calculating causes, and reduce the digital filter of filter complexity.
To achieve these goals, digital filter of the present invention comprises that following part constitutes characteristics: produce the mode select signal of decision real filter, complex filter action and with in the unit period signal, signal, the control part of the line output of going forward side by side are selected in the calculating that makes corresponding reckoner move twice calculating and control; According to above-mentioned mode select signal, select the real data and the imaginary number data of input, postpone respectively, and once more according to mode select signal with after calculating the data of the data of selecting signal to select input and delay, for the output of coefficient update and filter, the data input part of exporting; Above-mentioned data input part is selected the data of output to multiply by by mode select signal and is calculated the improper value of selecting signal to select, and the multiplication result with added up to by mode select signal and conversion coefficient that calculate to select signal to select, with the first coefficient update portion of a unit period time with the real number coefficient update of two coefficients of interior operation real filter or complex filter; Above-mentioned data input part is selected the data of output to multiply by by mode select signal and is calculated the improper value of selecting signal to select, and the multiplication result with added up to by mode select signal and conversion coefficient that calculate to select signal to select, with the second coefficient update portion of a unit period time with the imaginary number coefficient update of two coefficients of interior operation real filter or complex filter; Select two data of output to multiply by two coefficients of real filter of above-mentioned first coefficient update portion output or the real number coefficient of complex filter with interior above-mentioned data input part with a unit period time, with the first filtering efferent of a unit period time with two outputs of two Tab output of interior generation real filter or complex filter; Select two data of output to multiply by two coefficients of real filter of above-mentioned second coefficient update portion output or the imaginary number coefficient of complex filter with interior above-mentioned data input part with a unit period time, with the second filter efferent of a unit period time with two outputs of two Tab output of interior generation real filter or complex filter.
Above-mentioned data input part is to constitute characteristics with following part: in postponing the real data and imaginary number data of setting-up time respectively, with the unit period time with interior with mode select signal with calculate to select signal to select two data, export to the first data selection portion of the first coefficient update portion; Postponing does not respectively have to postpone and the real data and the imaginary number data of input, in the data of the data of above-mentioned input and delay, with the unit period time with interior with mode select signal with calculate to select signal to select two data, export to the second data selection portion of the first filtering efferent; In postponing the real data and imaginary number data of setting-up time respectively, with the unit period time with interior with mode select signal with calculate and select signal to select two data, export to the 3rd data selection portion of the second coefficient update portion; Postponing does not respectively once more have to postpone and the real data of input and the data of imaginary number data and the input of the above-mentioned second data selection portion, in the data of data of importing and delay, with the unit period time with interior with mode select signal with calculate to select signal to select two data, export to the 4th data selection portion of the second filtering efferent.
As mentioned above, digital filter of the present invention is in conjunction with the real filter of 4Tab and the complex filter of 1Tab, obtain filter output time with interior with cycle unit interval, use a reckoner in the structure of a symbol clock pulse (cycle unit interval) with twice calculating of interior operation, can solve the existing LMS of utilization adaptive filter with this, the size issue of the filter that is produced when embodying real filter and complex filter.That is, the present invention can reduce about 69% (18/26) to the quantity of multiplier and adder.
By above-mentioned description, the related work personnel can carry out various change and modification fully in the scope that does not depart from this invention technological thought.
Therefore, the technical scope of this invention is not limited to the content on the specification, must determine its technical scope according to interest field.
Other purpose of the present invention, characteristics and strong point will describe in detail by the embodiment with reference to accompanying drawing, can more be expressly understood.
[description of drawings]
Fig. 1 a and Fig. 1 b are the formation integration maps of digital filter of the present invention.
(a) of Fig. 2 is that expression is used for the clock pulse of digital filter configuration of the present invention and the phase relation of selection signal to (d).
Fig. 3 a and Fig. 3 b are the schematic diagrames that the signal flow when Fig. 1 digital filter is made action with the 4Tab real filter is represented with thick solid line.
(a) of Fig. 4 is each action timing diagram partly of Fig. 3 a to (k).
Fig. 5 a and Fig. 5 b are the schematic diagrames that the signal flow the when digital filter of Fig. 1 is made action with the 1Tab complex filter is represented with thick solid line.
(a) of Fig. 6 is each action timing diagram partly of Fig. 5 a to (k).
[embodiment]
Below with reference to accompanying drawings embodiments of the invention formation and effect thereof are described, as shown in the figure, and the formation of the present invention of explanation thus and effect be the explanation of carrying out with more than one embodiment at least, not can so and above-mentioned technological thought of the present invention and core and act on restricted.
Characteristics of the present invention are, in conjunction with 4Tab real filter and 1Tab complex filter, make it can from two filter functions, select to use, embody the complexity that both can reduce filter, also do not have filter to calculate the digital filter configuration of the output delay that causes.
Fig. 1 a and Fig. 1 b are the formation integration maps of expression digital filter embodiment of the present invention, constitute with data input part 100, the first and second coefficient update portions 200,300, the first and second filtering efferents 400,500.
Above-mentioned data input part 100 be obtain real data and imaginary number data, postpone above-mentioned real data the delay real data, postpone the input of the delay imaginary number data of imaginary number data, postpone according to mode select signal (mode_sel) respectively, and select signal (nclk) to select the data of input and the data of delay according to mode select signal and calculating once more, export to the above-mentioned first and second coefficient update portions 200,300 and the first and second filtering efferents 400,500.
Such data input part 100 is divided into first to fourth data selection portion 110～140.
The above-mentioned first data selection portion 110 is to select the real data of delay and the imaginary number data of delay according to mode select signal, postpone once more, and according to above-mentioned mode select signal and calculating selection signal, select the signal of above-mentioned delay or the signal of the second data selection portion, 120 outputs, export to the first coefficient update portion 200.
In more detail, the above-mentioned first data selection portion 110 is to constitute with 111,113 and four selectors of a plurality of delayers 112,114～116.Above-mentioned delayer 111 is that the real data xdi that postpones is postponed unit period signal (clk) time, exports to selector 112,114.If mode select signal is 0, above-mentioned selector 112 is just selected the output xdio of delayer 111; If mode select signal is 1, just select the imaginary number data xdq of delay, export to delayer 113.Above-mentioned delayer 113 is exported to selector 115 and the 3rd data selection portion 130 to the output delay unit period signal time of selector 112.If mode select signal is 0, above-mentioned selector 114 is just selected the output of the second data selection portion 120; If mode select signal is 1, just select the output of delayer 111, export to selector 116.If mode select signal is 0, above-mentioned selector 115 is just selected the output of the above-mentioned second data selection portion 120; If mode select signal is 1, just select the output of delayer 113, export to selector 116.Above-mentioned selector 116 is selected signal according to calculating, and selects the output of above-mentioned selector 114 or selector 115, exports to the first coefficient update portion 200.
The above-mentioned second data selection portion 120 is selected the real data of input and the imaginary number data of input according to mode select signal, and postpone once more, when exporting to the above-mentioned first data selection portion 110, select signal according to above-mentioned mode select signal and calculating, select the signal of above-mentioned input or the signal of delay, export to the first filtering efferent 400.
In more detail, the above-mentioned second data selection portion 120 is to constitute with 121,123 and four selectors of a plurality of delayers 122,124～126.The real data xi of input provides to delayer 121 and selector 124.Above-mentioned delayer 121 is that the real data xi of input is postponed the unit period signal time, exports to the selector 114 of the first data selection portion 110 and the selector 122,124,125 of the second data selection portion 120.Above-mentioned selector 122 is selected the output xio of above-mentioned delayer 111 and the imaginary number data xq of input according to mode select signal, exports to delayer 123.Above-mentioned delayer 123 is exported to the selector 115 of the first data selection portion 110 and the selector 125 and the 4th data selection portion 140 of the second data selection portion 120 to the output delay unit period signal time of selector 122.If mode select signal is 0, above-mentioned selector 124 is just selected real number input xi; If mode select signal is 1, just select the output of delayer 121, export to selector 126.If mode select signal is 0, above-mentioned selector 125 is just selected the output of delayer 121; If mode select signal is 1, just select the output of delayer 123, export to selector 126.Above-mentioned selector 126 selects signal to select the output of above-mentioned selector 124 or selector 125 according to calculating, and exports to the first filtering efferent 400.
Above-mentioned the 3rd data selection portion 130 is selected the real data of delay and the imaginary number data of delay according to mode select signal, postpone once more, and according to above-mentioned mode select signal and calculating selection signal, select the signal of above-mentioned delay or the signal of the 4th data selection portion 140 outputs, export to the second coefficient update portion 300.
In more detail, above-mentioned the 3rd data selection portion 130 is to constitute with 132,134 and five selectors of a plurality of delayers 131,133,135～137.The imaginary number data xdq that postpones is exported to selector 131.If mode select signal is 0, above-mentioned selector 131 is just selected the output A of the first data selection portion 110; If be 1, just select the imaginary number data xdq of above-mentioned delay, export to delayer 132.Above-mentioned delayer 132 is exported to selector 133,135 to the output delay unit period signal time of above-mentioned selector 131.If mode select signal is 0, above-mentioned selector 133 is just selected the output of delayer 132; If be 1, just select the real data xdi of delay, export to delayer 134.Above-mentioned delayer 134 is exported to selector 136 to the output delay unit period signal time of selector 133.If mode select signal is 0, above-mentioned selector 135 is just selected the output of above-mentioned the 4th data selection portion 140; If be 1, just select the output of delayer 132, export to selector 137.If mode select signal is 0, above-mentioned selector 136 is just selected the output of above-mentioned the 4th data selection portion 140; If be 1, just select the output of delayer 134, export to selector 137.Above-mentioned selector 137 selects signal to select the output of above-mentioned selector 135 or selector 136 according to calculating, and exports to the second coefficient update portion 300.
Above-mentioned the 4th data selection portion 140 is selected the real data of input and the imaginary number data of input according to mode select signal, and postpone once more, when exporting to the 3rd data selection portion 130, select signal to select the signal of above-mentioned input signal or delay according to above-mentioned mode select signal and calculating, export to the second filtering efferent 500.
In more detail, above-mentioned the 4th data selection portion 140 is to constitute with 142,144 and five selectors of a plurality of delayers 141,143,145～147.The imaginary number data xq of input exports to selector 141.If mode select signal is 0, above-mentioned selector 141 is just selected the output B of the above-mentioned second data selection portion 120; If be 1, just select above-mentioned imaginary number data xq, export to delayer 142.Above-mentioned delayer 142 is exported to the selector 135 of the 3rd data selection portion 130 and the selector 143,145,146 of the 4th data selection portion 140 to the output delay unit period signal time of above-mentioned selector 141.If mode select signal is 0, above-mentioned selector 143 is just selected the output of above-mentioned delayer 142; If be 1, just select real data xi, export to delayer 144.Above-mentioned delayer 144 is exported to the selector 136 of the 3rd data selection portion 130 and the selector 146 of the 4th data selection portion 140 to the output delay unit period signal time of above-mentioned selector 143.If mode select signal is 0, above-mentioned selector 145 is just selected the output of above-mentioned selector 141; If be 1, just select the output of above-mentioned delayer 142, export to selector 147.If mode select signal is 0, above-mentioned selector 146 is just selected the output of delayer 142; If be 1, just select the output of delayer 144, export to selector 147.Above-mentioned selector 147 selects signal to select the output of above-mentioned selector 145 or selector 146 according to calculating, and exports to the second filtering efferent 500.
The above-mentioned first coefficient update portion 200 selects the data of output to multiply by improper value with the first data selection portion 110, and the conversion coefficient of total multiplication result and feedback, move renewal with this, select signal according to calculating, upgrade two coefficient c0, c1 with interior intersection with the unit period time, export to the first filtering efferent 400.
In more detail, the selector 201 of the above-mentioned first coefficient update portion 200 selects signal to select bad real erri or imaginary number mistake errq according to calculating, and exports to selector 202.If mode select signal is 0, above-mentioned selector 202 is just selected bad real erri; If be 1, just select the output of above-mentioned selector 201, export to multiplier 203.Above-mentioned multiplier 203 is the output of multiply by the selector 116 of the above-mentioned first data selection portion 110 with the output of above-mentioned selector 202, exports to interests portion 204 and selector 205.The part that above-mentioned interests portion 204 uses when making action with complex filter, the output multiplication by constants A of above-mentioned multiplier 203, correct its size after, export to selector 205.If mode select signal is 0, above-mentioned selector 205 is just selected the output of above-mentioned multiplier 203; If be 1, just select the output of above-mentioned interests portion 204, export to adder 206.Above-mentioned adder 206 adds up to the output of above-mentioned selector 205 and the conversion coefficient of feedback, exports to saturator 207.
Above-mentioned saturator 207 is to make the output of above-mentioned adder 206 saturated, exports to coefficient and stores with delayer 212,213.Above-mentioned saturator 207 comprises selector 208, symbol extraction device 209, comparator 210 and selector 211.Above-mentioned symbol extraction device 209 extracts symbol from the output of above-mentioned adder 206, provides as the selection signal of selector 211.After above-mentioned comparator 210 is obtained 2 powers of above-mentioned adder 206 outputs, compare, its result is provided as the selection signal of selector 208 with constant B.Above-mentioned selector 211 is selected positive constant B or negative constant-B according to the symbol that extracts from above-mentioned symbol extraction device 209, exports to selector 208.Above-mentioned selector 208 is selected the output of above-mentioned adder 206 or the output of selector 211 according to the comparative result of comparator 210 outputs, exports to delayer 212,213.Above-mentioned delayer 212 is exported to adder 218 and selector 214 after the output of above-mentioned selector 208 is stored synchronously with clk2.Above-mentioned clk2 is that phase place has the clock pulse of 1/2 gap than unit period signal (clk).Above-mentioned delayer 213 is exported to selector 214 and selector 215 and adder 218 after the output of above-mentioned selector 208 is stored with the unit period signal Synchronization.The signal that above-mentioned adder 218 adds up to above-mentioned delayer 212,213 to feed back is respectively exported to selector 219.Above-mentioned selector 219 is selected signal according to calculating, and selector 217 is exported in the output of selection ' 0 ' or above-mentioned adder 218.If mode select signal is 0, above-mentioned selector 217 is just selected the signal of above-mentioned selector 214 feedbacks; If be 1, just select the output of above-mentioned selector 219, feed back to above-mentioned adder 206 as conversion coefficient.Above-mentioned selector 215 is selected signal according to calculating, and selects the output of selector 214 or the output of delayer 213, exports to interests portion 216.Above-mentioned interests portion 216 be the output of above-mentioned selector 215 divided by constant C, and it is exported to the first filtering efferent 400.
The above-mentioned first filtering efferent 400 is to multiply by the multiplier 401 of the output of the above-mentioned second data selection portion 120, the output of above-mentioned multiplier 401 is stored synchronously delayer 402 formations of back output with clk1 with the coefficient that the above-mentioned first coefficient update portion 200 upgrades.Above-mentioned clk1 is than unit period signal, and phase place is lower than 1/4 clock pulse.The above-mentioned first filtering efferent, 400 output two values y0 and y1.That is, the output valve that postpones the delayer 402 of above-mentioned multiplier 401 outputs is y0, and the output valve of above-mentioned multiplier 401 is y1.Above-mentioned two value y0 and y1 have the different meanings according to the function of filter.
The above-mentioned second coefficient update portion 300 selects the data of output to multiply by improper value with the 3rd data selection portion 130, and the conversion coefficient of total multiplication result and feedback, operating factor upgrades, select signal according to calculating, upgrade two coefficient c1 and c2 with interior intersection with a unit period time, export to the second filtering efferent 500.
In more detail, the above-mentioned second coefficient update portion 300 is that selector 301 selects signal to select bad real erri or imaginary number mistake errq according to calculating, and exports to selector 302.If mode select signal is 0, above-mentioned selector 302 is just selected bad real erri; If be 1, just select the output of above-mentioned selector 301, export to multiplier 303.Above-mentioned multiplier 303 is the output of multiply by the selector 137 of above-mentioned the 3rd data selection portion 130 with the output of above-mentioned selector 302, exports to interests portion 304 and selector 305.The part that above-mentioned interests portion 304 utilizes when making action with complex filter, the output multiplication by constants A of above-mentioned multiplier 303, correct its size after, export to selector 305.If mode select signal is 0, above-mentioned selector 305 is just selected the output of above-mentioned multiplier 303; If be 1, just select the output of above-mentioned interests portion 304, export to adder 306.Above-mentioned adder 306 is to add up to the output of above-mentioned selector 305 and the conversion coefficient of feedback, exports to saturator 307.
Above-mentioned saturator 307 makes the output of above-mentioned adder 306 saturated, exports to coefficient and stores with delayer 312,313.Above-mentioned saturator 307 comprises selector 308, symbol extraction device 309, comparator 310, selector 311.Above-mentioned symbol extraction device 309 extracts symbol from the output of above-mentioned adder 306, provides as the selection signal of selector 311.After above-mentioned comparator 310 is obtained 2 powers of above-mentioned adder 306 outputs, compare, its result is provided as the selection signal of selector 308 with constant B.Above-mentioned selector 311 is selected positive constant B or negative constant-B according to the symbol that extracts from above-mentioned symbol extraction device 309, exports to selector 308.Above-mentioned selector 308 is selected the output of above-mentioned adder 306 or the output of selector 311 according to the comparative result of comparator 310 outputs, exports to delayer 312,313.Above-mentioned delayer 312 is exported to adder 318 and selector 314 after the output of above-mentioned selector 308 is stored synchronously with clk2.Above-mentioned clk2 is that phase place has the clock pulse of 1/2 gap than unit period signal (clk).Above-mentioned delayer 313 is exported to selector 314 and selector 315 and subtracter 318 after the output of above-mentioned selector 308 is stored with the unit period signal Synchronization.Above-mentioned subtracter 318 is obtained the signal difference that above-mentioned delayer 312,313 feeds back respectively, exports to selector 319.Above-mentioned selector 319 is selected signal according to calculating, and selector 317 is exported in the output of selection ' 0 ' or above-mentioned subtracter 318.If mode select signal is 0, above-mentioned selector 317 is just selected the signal of above-mentioned selector 314 feedbacks; If be 1, just select the output of above-mentioned selector 319, feed back to above-mentioned adder 306 as conversion coefficient.Above-mentioned selector 315 is selected signal according to calculating, and selects the output of selector 314 or the output of delayer 313, exports to interests portion 316.Above-mentioned interests portion 316 be the output of above-mentioned selector 315 divided by constant C, and it is exported to the second filtering efferent 500.
The above-mentioned second filtering efferent 500 is to multiply by the multiplier 501 of the output of above-mentioned the 4th data selection portion 140, the output of above-mentioned multiplier 501 is stored synchronously delayer 502 formations of back output with clk1 with the coefficient that the above-mentioned second coefficient update portion 300 upgrades.Above-mentioned clk1 is than unit period signal, and phase place is lower than 1/4 clock pulse.Two Tab output y2 of the above-mentioned second filtering efferent 500 outputs and y3.That is, the output valve that postpones the delayer 502 of above-mentioned multiplier 501 outputs is y2, and the output valve of above-mentioned multiplier 501 is y3.Above-mentioned two value y2 and y3 have the different meanings according to the function of filter.
Here, the 3rd data selection portion 130 can be shared with the first data selection portion 110.That is,, from 110,130 two of the first and the 3rd data selection portions, can only use a signal because of the xdio as a result of the delayer 134 of the xdio as a result of the delayer 111 of the first data selection portion 110 and the 3rd data selection portion 130 is same signals.Same reason, the xdqo as a result of the output xdqo of the delayer 113 of the first data selection portion 110 and the delayer 132 of the 3rd data selection portion 130 also is a same signal, therefore also can from 110,130 two of the first and the 3rd data selection portions, only use a signal.Can obtain the input of output xdqo of the delayer 113 of the first data selection portion 110 such as, the selector 135 that substitutes delayer 132, the three data selection portions 130.In addition, the delayer 136 that substitutes delayer 134, the three data selection portions 130 can obtain the input of output xdio of the delayer 111 of first selection portion 110.Under these circumstances, delayer 132,134 and selector 131,133 that just need not the 3rd data selection portion 130.
Simple on illustrating, the present invention's hypothesis utilizes the delayer 132,134 of the 3rd data selection portion 130 and selector 131,133, the second coefficient update portions 300 operating factors to upgrade.
In addition, the mode select signal of above-mentioned Fig. 1 is that digital filter decision of the present invention is to make action with the 4Tab real filter, still makes the signal of action with the 1Tab complex filter.Embodiments of the invention are, if mode select signal is 0, just with real filter; If be 1, just make action with complex filter.
(a) of Fig. 2 is that expression is used for the clock pulse of digital filter configuration of the present invention and the phase relation of selection signal to (d).The clk of Fig. 2 (a) is the symbol clock pulse with cycle unit interval.The clk1 of Fig. 2 (b) is than clk, and phase place is lower than 1/4 the clock pulse in cycle unit interval.The clk2 of Fig. 2 (c) is than clk, and phase place and cycle unit interval have the clock pulse of 1/2 gap.The nclk of Fig. 2 (d) is that its waveform is identical with above-mentioned clk2, but has the calculating selection signal of delayed slightly.At this moment, in the selector of above-mentioned Fig. 1, nclk as select that signal uses be for digital filter of the present invention with in the symbol period, make each reckoner move twice calculating and use.
In addition, suppose that above-mentioned mode select signal and each clock pulse (that is, clk, clk1, clk2, nclk) are to produce at control part (not diagram), offer digital filter of the present invention.
The present invention of Gou Chenging is the situation when being divided into that the digital filter of Fig. 1 is made when action with the 4Tab real filter and making action with the 1Tab complex filter like this, describes respectively.
Signal flow when the digital filter of Fig. 3 a and Fig. 3 b presentation graphs 1 is made action with the 4Tab real filter is to represent with thick solid line.At this moment, mode select signal is ' 0 '.
Fig. 4 is each action timing diagram partly of Fig. 3 a, and the action timing diagram of Fig. 3 b is also basic identical with Fig. 4, but because of the gap of its input value, its output valve is different.(a) of Fig. 4 is the expression and the example of the identical clock pulse of above-mentioned Fig. 2 to (d), the clk is-symbol clock pulse of (a) of Fig. 4, i.e. unit period signal; The clk1 of Fig. 4 (b) is the clk than (a), and phase place is lower than the clock pulse in cycle unit interval 1/4.The clk2 of Fig. 4 (c) is than clk, and phase place has the clock pulse of 1/2 gap in cycle unit interval.The nclk of Fig. 4 (d) is that its waveform is identical with above-mentioned clk2, selects signal but have the calculating of time delay slightly.In addition, Fig. 4 does not indicate constant calculations value (that is, A, B, C).
That is delayer 201,203,142,144 when mode select signal is ' 0 ', the second and the 4th data selection portion 120,140 of data input part 100) postpones (x1～x4) to the data xi of input successively with the unit period signal Synchronization.In addition, each selector the 114,115,122,124,125,141,143,145, the 146th of first to fourth data selection portion 110～140, its mode select signal is ' 0 ', therefore select to be input to the signal of ' 0 ' input, export by output.This is in the selector shown in Fig. 3 a and Fig. 3 b, to all applicable as the selector of selecting signal to use with mode select signal.
So, the input signal xi of above-mentioned delayer 201 (=x0) be by selector 124, output to selector 126.
The output signal x1 of above-mentioned delayer 201 exports to delayer 123 by selector 122, postpones, and exports to selector 126 by selector 125, exports to selector 116 by the selector 114 of the first data selection portion 110.
The output signal x2 of above-mentioned delayer 123 exports to selector 116 by the selector 115 of the first data selection portion 110, exports to delayer 142 by the selector 141 of the 4th data selection portion 140, postpones.In addition, the output of above-mentioned selector 141 is to export to selector 147 by selector 145.
The output signal x3 of above-mentioned delayer 142 exports to delayer 144 by selector 143, postpones, and exports to selector 147 by selector 146, exports to selector 137 by the selector 135 of the 3rd data selection portion 130.
The output signal x4 of above-mentioned delayer 144 exports to selector 137 by the selector 136 of the 3rd data selection portion 130.
The selector the 116,126,137, the 147th of above-mentioned first to fourth data selection portion 110～140 is selected signal according to calculating, and selects the selector of output input signal.
It is that its waveform is identical with the clk2 of Fig. 2 (c) that aforementioned calculation is selected signal (nclk), but has the clock pulse of time delay slightly, is that digital filter of the present invention uses with twice calculating of interior operation with a symbol period in order to make each reckoner.This is because with twice reckoner of interior use, be intended to obtain two outputs with a unit period signal (clk).
So, be 0 if calculate the selection signal, the selector 116 of the above-mentioned first data selection portion 110 is just selected the output x1 of selector 114; If be 1, just select the output x2 of selector 115, export to the multiplier 203 of the first coefficient update portion 200.
If calculating and selecting signal is 0, the selector 137 of above-mentioned the 3rd data selection portion 130 is just selected the output x3 of selector 135; If be 1, just select the output x4 of selector 136, export to the multiplier 303 of the second coefficient update portion 300.
In addition, be 0 if calculate the selection signal, the selector 126 of the above-mentioned second data selection portion 120 is just selected the output x0 of selector 124; If be 1, just select the output x1 of selector 125, export to the multiplier 401 of the first filtering efferent 400.
If calculating and selecting signal is 0, the selector 147 of above-mentioned the 4th data selection portion 140 is just selected the output x2 of selector 145; If be 1, just select the output x3 of selector 146, export to the multiplier 501 of the second filtering efferent 500.
Digital filter of the present invention is made when action with real filter, and when promptly mode select signal be ' 0 ', each Tab coefficient update formula that forms in the first and second coefficient update portions 200,300 was with regard to mathematical expression 1 in the following example
[mathematical expression 1]
c3(n+1)＝c3(n)+x4(n)*erri(n)
Here, x1 (n), x2 (n), x3 (n), x4 (n) be real number input xi by the symbol clock pulse-delay unit 121,123,142,144 of data input part 100 once to four times with the unit period signal Synchronization, the signal of Yan Chiing successively.In addition, c1 (n), c2 (n), c3 (n), c4 (n) are the filter coefficients of present time; C1 (n+1), c2 (n+1), c3 (n+1), c4 (n+1) are the filter coefficient of next time, i.e. updated filter coefficient; In addition, erri (n) is the bad real value.
Promptly, as Fig. 4 (h), if calculate selecting signal is after signal x1 that the multiplier 203 of 0, the first coefficient update portion 200 is just selected to export with the first data selection portion 110 multiply by bad real erri, to export to adder 206 (x1*erri) by selector 205; If calculating and selecting signal is 1, after multiply by bad real erri, export to adder 206 (x2*erri) by selector 205 with output signal x2.Above-mentioned bad real erri offers above-mentioned multiplier 203 by selector 202.
Above-mentioned adder 206 is as Fig. 4 (i), and the output valve of above-mentioned selector 205 multiply by the conversion coefficient value of feedback, and operating factor is exported to saturator 207 after upgrading.
If the output of above-mentioned adder 206 is saturated to more than the certain value, above-mentioned saturator 207 just be restricted to certain set point (such as, B or-B) output, otherwise the output of exporting above-mentioned adder 206 strictly according to the facts.For this reason, symbol extraction device 209 is to extract symbol from the output of above-mentioned adder 206, as the selection signal output of selector 211.If the symbol that extracts from above-mentioned symbol extraction device 209 is just (+), above-mentioned selector 211 is just selected positive constant B; If be negative (-), just select negative constant-B, export to selector 208.In addition, after comparator 210 was obtained the absolute value of above-mentioned adder 206 outputs, relatively whether its absolute value was greater than constant B.Then, comparative result is exported to above-mentioned selector 208.If above-mentioned comparator 210 is judged as absolute value greater than constant B, above-mentioned selector 208 is just selected the output of selector 211; Otherwise just select the output of adder 206, export to delayer 212,213.
Above-mentioned delayer 212 as Fig. 4 (j), synchronously store the output of above-mentioned saturator 207 with clk2 after, as coefficient c0 (=c0+x1erri) export to selector 214.Delayer 213 as Fig. 4 (k), synchronously store the output of above-mentioned saturator 207 with clk after, as coefficient c1 (=c1+x2erri) export to selector 214.
If calculating and selecting signal is 0, above-mentioned selector 214 is just selected coefficient c0; If be 1, just select coefficient c1, when exporting to interests portion 216, export to adder 206 by selector 217 by selector 215.That is, be 0 if calculate the selection signal, above-mentioned adder 206 adds up to the conversion coefficient c0 that feeds back just by the x1*erri and the selector 217 of selector 205 outputs, and operation is to the renewal of coefficient c0.In addition, be 1 if calculate the selection signal, just, add up to the conversion coefficient c1 that feeds back by the x2*erri and the selector 217 of selector 205 outputs, operation is to the renewal of coefficient c1.
In addition, above-mentioned interests portion 216 be the update coefficients (c0 or c1) of above-mentioned selector 215 outputs divided by constant C, export to the multiplier 401 of the first filtering efferent 400.Above-mentioned multiplier 401 is as Fig. 4 (e), and the selection portion 126 that the second data selection portion 120 is multiply by in the output of above-mentioned interests portion 216 is selected the data of output, strictly according to the facts output the time, by delayer 402 outputs of making action with clk1 synchronously.That is, be 0 if calculate to select signal, above-mentioned multiplier 401 is just in interests portion 216, and coefficient c0 is divided by constant C, and multiply by above-mentioned selector 126 with its value (c0/C) and select the x0 that exports, exports; If be 1, in interests portion 216, coefficient c1 is divided by constant C, and multiply by the x1 that above-mentioned selector 126 is selected output with its value (c1/C), exports.Here, simple on illustrating omits constant C from accompanying drawing and explanation.
At this moment, the output of above-mentioned multiplier 401 is when carrying out strictly according to the facts, by delayer 402 outputs.Above-mentioned delayer 402 is after storing the output of multiplier 401 synchronously with clk1, to export.Above-mentioned clk1 is as Fig. 2 (b), and than clk, phase place is lower than 1/4 the clock pulse in cycle unit interval.Promptly, as Fig. 4 (f), export (y0=x0*c0) by delayer 402 with the y0 value from the x0*c0 of above-mentioned multiplier 401 outputs, as Fig. 4 (g), the x1*c1 that exports from above-mentioned multiplier 401 is can be by delayer 402 faithfully with y1 value output (y1=x1*c1).
Like this, output y0 and the y1 of above-mentioned two Tab obtained a unit period time.That is, in the time, twice use reckoner (that is, selecting signal as the selector of selecting signal to obtain importing calculating) obtains two outputs with a unit period.
In addition, the above-mentioned second coefficient update portion 300 and the second filtering efferent 500 also with the above-mentioned first coefficient update portion 200, the first filtering efferent, 400 identical process, upgrade coefficient c2 and the c3 of two Tab, obtain output y2 and y3.
Digital filter of the present invention is made when action with real filter, and the above-mentioned first coefficient update portion 200 and the second coefficient update portion 300 be, the input signal difference of having only data input part 100 to provide, and its renewal process is identical.That is, the multiplier 303 of the above-mentioned second coefficient update portion 300 is, is 1 if calculate the selection signal, just selects the data x2 of output to multiply by bad real erri output with the 3rd data selection portion 130; If be 1, just select the data x3 of output to multiply by bad real erri output with the 3rd data selection portion 130.Action afterwards is identical with the first above-mentioned coefficient update portion 200, therefore with detailed.
Equally, when digital filter of the present invention was made action with real filter, the above-mentioned first filtering efferent 400 also was to have only the signal of its input different with the second filtering efferent 500, and the output procedure of two Tab is identical.Promptly, if calculating and selecting signal is 0, the selector 147 that the multiplier 501 of the second filtering efferent 500 just multiply by above-mentioned the 4th data selection portion 140 with the coefficient c2 of the renewal of the second coefficient update portion, 300 outputs is selected the data x2 that exports, exports (x2*c2); If be 1, just the selector 147 that multiply by above-mentioned the 4th data selection portion 140 with the coefficient c3 of the renewal of the second coefficient update portion, 300 outputs is selected the data x3 that exports, exports (x3*c3).At this moment, the x2*c2 of above-mentioned multiplier 501 outputs exports (y2=x2*c2) by delayer 502 with the y2 value, and the x3*c3 of above-mentioned multiplier 501 outputs is not by delayer 502, directly with y3 value output (y3=x3*c3).
So digital filter of the present invention is made when action with real filter, (y0～y3) just as following mathematical expression 2 for the 4Tab output by 400,500 outputs of the first and second filtering efferents.
[mathematical expression 2]
y3＝x3*c3
Here, x0 is input signal xi, x1, x2, x3 be real number input xi by the symbol clock pulse-delay unit 121,123,142 of data input part 100 from once to three times with the unit period signal Synchronization, the signal of Yan Chiing successively.C0, c1, c2 and c3 are the coefficients of the renewal of each Tab.
In addition, (total of y0～y3) is to obtain from the accumulative total interval of (a) expression of Fig. 4 in above-mentioned filtering output.
Like this, digital filter of the present invention is, if mode select signal is 0, just makes action with the 4Tab real filter with 4 Tab outputs.
Simultaneously, Fig. 5 a and Fig. 5 b are that the digital filter of the above-mentioned Fig. 1 of expression is made the signal flow in when action with the 1Tab complex filter, are to represent with thick solid line.At this moment mode select signal is 1.
(a) of Fig. 6 is each action timing diagram partly of Fig. 5 a to (k), and the action timing diagram of Fig. 5 b is also basic identical with Fig. 6, but because of the gap of its input value, output valve is different.Because of (a) to (d) and the identical clock pulse of above-mentioned Fig. 4 (a) to (d) of Fig. 6, with detailed.In addition, Fig. 6 does not indicate constant calculations value (that is, A, B, C) yet.
That is, filter will be made action with complex filter, all needs real number input and imaginary number input.In addition, because of mode select signal is the signal that each selector 114,115,122,124,125,141,143,145,146 of 1, first to fourth data selection portion 110～140 selects to be input to ' 1 ' input, export by output.This all is applicable to the selector that mode select signal is used as the selection signal in the selector shown in Fig. 5 a and Fig. 5 b.In addition, each data of 111,113,121,123,132,134,142,144 inputs of each delayer of above-mentioned first to fourth data selection portion 110～140 are with the unit period signal Synchronization, and output after postponing.
So the real data xdi of delay is the delayer 111 that is input to the first data selection portion 110, the selector 133 by the 3rd data selection portion 130 is input to delayer 134, postpones with the unit period signal time.
The imaginary number data xdq that postpones is input to delayer 113 by the selector 112 of the first data selection portion 110, and the selector 131 by the 3rd data selection portion 130 is input to delayer 132, postpones with the unit period signal time.
The real data xi of input is input to the delayer 121 of the second data selection portion 120, and the selector 143 by the 4th data selection portion 140 is input to delayer 144, postpones with the unit period signal time.
The selector 122 of the imaginary number data xq of input by the second data selection portion 120 is input to delayer 123, and the selector 141 by the 4th data selection portion 140 is input to delayer 142, postpones with the unit period signal time.
In addition, the output xdio of the delayer 111 of the above-mentioned first data selection portion 100 exports to selector 116 by selector 114, and the output xdqo of above-mentioned delayer 112 exports to selector 116 by selector 115.Above-mentioned selector 116 is that calculating and selecting signal is 0 o'clock, selects the output xdio of above-mentioned selector 114; Calculating and selecting signal is 1 o'clock, selects the output xdqo of selector 115, exports to the multiplier 203 of the first coefficient update portion 200.
The output xio of the delayer 121 of the above-mentioned second data selection portion 120 exports to selector 126 by selector 124, and the output xqo of above-mentioned delayer 123 exports to selector 126 by selector 125.Above-mentioned selector 126 is that calculating and selecting signal is 0 o'clock, selects the output xio of above-mentioned selector 124; Calculating and selecting signal is 1 o'clock, selects the output xqo of selector 125, exports to the multiplier 501 of the first filtering efferent 400.
The output xdqo of the delayer 132 of above-mentioned the 3rd data selection portion 130 exports to selector 137 by selector 135, and the output xdio of delayer 134 exports to selector 137 by selector 136.Above-mentioned selector 137 is that calculating and selecting signal is 0 o'clock, selects the output xdqo of above-mentioned selector 135; Calculating and selecting signal is 1 o'clock, selects the output xdio of selector 136, exports to the multiplier 303 of the second coefficient update portion 300.
The output xqo of the delayer 142 of above-mentioned the 4th data selection portion 140 exports to selector 147 by selector 145, and the output xio of above-mentioned delayer 144 exports to selector 147 by selector 146.Above-mentioned selector 147 is that calculating and selecting signal is 0 o'clock, selects the output xqo of above-mentioned selector 145; Calculating and selecting signal is 1 o'clock, selects the output xio of selector 146, exports to the multiplier 501 of the second filtering efferent 500.
At this moment, first of above-mentioned data input part 100 obtains the input of identical real number and imaginary number data (xdi, xdq) respectively with the 3rd data selection portion 110,130, produce unit period time of delay respectively, promptly be equivalent to the identical dateout (xdio, xdqo) of symbol clock pulse; Second also obtains the input of identical real number and imaginary number data (xi, xq) respectively with the 4th data selection portion 120,140, produces the identical dateout (xio, xqo) that postpones a unit period time respectively.So the above-mentioned first and second coefficient update portions 200,300 can obtain input from the first and the 3rd data selection portion 110,130 respectively; Also can only obtain input from the first data selection portion 110 or the 3rd data selection portion 130.This depends on the designer, therefore will can not be confined to the foregoing description.
In the present invention, the first coefficient update portion 200 is from the first data selection portion 100; The second coefficient update portion 300 is provided as embodiment from the data that the 3rd data selection portion 130 obtains being used for coefficient update.
In addition, digital filter of the present invention is made action with complex filter, and promptly mode select signal is 1 o'clock, and each Tab coefficient update formula in the first and second coefficient update portions 200,300 is in the following example mathematical expression 3 just.At this moment, because of coefficient is a plural number, is divided into real number coefficient part and imaginary number coefficient and partly calculates.
[mathematical expression 3]
Real number coefficient: icoef (n+1)=erri*xdio+errq*xdqo+icoef (n)
Imaginary number coefficient: qcoef (n+1)=-erri*xdqo+errq*xdio+qcoef (n)
At the digital filter configuration of Fig. 1, the c1 coefficient of real filter becomes the real number coefficient icoef of complex filter as above-mentioned mathematical expression 3; The c3 coefficient of real filter becomes the imaginary number coefficient qcoef of complex filter.
In addition, in above-mentioned mathematical expression 3, erri is a bad real; Errq is the imaginary number mistake.Xdio is that input xdio postpones the data of a symbol; Xdqo is that input xdq postpones the data of a symbol.Above-mentioned icoef (n), qcoef (n) is the filter coefficient of present time; Above-mentioned icoef (n+1), qcoef (n+1) are the filter coefficient of next time, i.e. updated filter coefficient.
That is, as Fig. 6 (h), the multiplier 203 of the first coefficient update portion 200 is, is 0 if calculate the selection signal, just selects the real number signal xdio of output to multiply by bad real erri with the first data selection portion 110, exports to interests portion 204.Above-mentioned interests portion 204 after xdio*erri multiply by A as a result with multiplication, exports to adder 206 (xdio*erri*A) by selector 205.In addition, above-mentioned multiplier 203 is, if calculating and selecting signal is 1, just select the imaginary signal xdqo of output to multiply by imaginary number mistake errq with the first data selection portion 110, export to interests portion 204, above-mentioned interests portion 204 after xdqo*errq multiply by A as a result with multiplication, exports to adder 206 (xdqo*errq*A) by selector 205.For this reason, selector 201 is, is 0 if calculate the selection signal, just selects bad real erri; If be 1, just select imaginary number mistake errq after, export to multiplier 203 by selector 202.Above-mentioned A is the constant for correction ratio (Scale).
Above-mentioned adder 206 is as Fig. 6 (i), and the output valve of above-mentioned selector 205 multiply by the conversion coefficient value of feedback, and operating factor is exported to saturator 207 after upgrading.
After above-mentioned saturator 207 is obtained the absolute value of above-mentioned adder 206 outputs, if its absolute value surpass certain value (such as, B), just be restricted to certain value (such as, B or-B), export to delayer 212,213; Otherwise,, just above-mentioned delayer 212,213 is exported in the output of above-mentioned adder 206 faithfully if promptly do not have saturatedly.The detailed action of above-mentioned saturator 207 is because of being illustrated in the 4Tab real filter, with the detailed action specification of omitting on the 1Tab complex filter.
Above-mentioned delayer 212 is after storing the output of above-mentioned saturator 207 synchronously with clk2, to feed back to adder 218; Above-mentioned delayer 213 is after storing the output of above-mentioned saturator 207 synchronously with clk, to feed back to adder 218.The coefficient value that above-mentioned adder 218 adds up to above-mentioned delayer 212,213 to export is respectively exported to selector 219.At this moment, the output of above-mentioned delayer 213 by selector 215 and interests portion 216, is also exported to the multiplier 401 of the first filtering efferent 400 as real number coefficient icoef.
Above-mentioned selector 219 is, is 0 if calculate the selection signal, just selects ' 0 '; If be 1, just select the output of above-mentioned adder 218 after, export to adder 206 by selector 217.
Promptly, adder 218 adds up to as above-mentioned Fig. 6 (j), the coefficient xdio*erri of delayer 212 output and as Fig. 6 (k), the conversion real number coefficient icoef of delayer 213 outputs, its aggregate result (xdio*erri+icoef) is, the calculating selection signal that is input to selector 219 is 1 o'clock, by above-mentioned selector 218 and selector 217, inputs to adder 206.If calculating and selecting signal is 0, after above-mentioned selector 219 just selects 0, export to adder 206 by selector 217.So above-mentioned adder 206 is, is 0 if calculate the selection signal, just the value xdio*erri of above-mentioned multiplier 203 outputs is exported to saturated 207 faithfully; If be 1, just add up to the value xdiq*errq of above-mentioned multiplier 203 outputs and the output (xdio*erri+icoef) of above-mentioned selector 217, export to saturated 207.Above-mentioned saturated 207 output valve is exactly the coefficient value newc0 that upgrades as Fig. 6 (i).At this moment, in order to upgrade each coefficient, need carry out plural coefficient update.So in above-mentioned update coefficients value newc0, xdio*erri exports as Fig. 6 (j) by make the delayer 212 of action synchronously with clk2; Icoef+xdio*erri+xdqo*errq exports as Fig. 6 (k) by make the delayer 213 of action synchronously with clk, and the output valve of above-mentioned delayer 212,213 is to feed back to adder 218.
In addition, in the present invention, the 1Tab complex filter is only two coefficients in four coefficients of 4Tab real filter to be used as coefficient of efficiency.That is, at Fig. 3 a, the c1 coefficient uses as real number coefficient icoef; At Fig. 3 b, the c3 coefficient uses as imaginary number coefficient qcoef.Above-mentioned real number coefficient icoef is through selector 215 and interests portion 216, exports to the multiplier 401 of the first filtering efferent 400.Above-mentioned imaginary number coefficient qcoef is through selector 315 and interests portion 316, exports to the multiplier 501 of the second filtering efferent 500.
Above-mentioned multiplier 401 is as Fig. 6 (e), the selection portion 126 that the real number coefficient icoef of above-mentioned interests portion 216 outputs multiply by the second data selection portion 120 is selected the data (xio or xqo) of output, when directly exporting, by delayer 402 outputs of making action with clk1 synchronously.Above-mentioned delayer 402 is synchronous with clk1, exports after the output of delay multiplier 401.That is, above-mentioned multiplier 401 is, is 0 if calculate the selection signal, and just the real number coefficient icoef with 216 outputs of interests portion multiply by the real data xio that above-mentioned selector 126 is selected output, the line output of going forward side by side; If be 1, just the real number coefficient icoef with 216 outputs of interests portion multiply by the imaginary number data xqo that above-mentioned selector 126 is selected output, exports.Here, simple on illustrating omits the constant C of interests portion 216 from accompanying drawing and explanation.
In addition, it is 0 o'clock that aforementioned calculation is selected signal, and the xio*icoef of multiplier 401 outputs is as Fig. 6 (f), by delayer 402, with y0 value output (y0=xio*icoef); It is 1 o'clock that aforementioned calculation is selected signal, and the xqo*icoef of multiplier 401 outputs is not by delayer 402, strictly according to the facts with y1 value output (y1=xqo*icoef).
Like this, above-mentioned two output y0, y1 obtain in the time a unit period.That is,, obtain two outputs with unit period reckoner of twice use in the time (that is, selecting signal as the selector of selecting signal to obtain importing) calculating.
Simultaneously, the above-mentioned second coefficient update portion 300 and the second filtering efferent 500 also with the above-mentioned first coefficient update portion 200, process that the first filtering efferent 400 is identical, upgrade imaginary number coefficient qcoef, obtain two y2, y3.
When digital filter of the present invention is made action with complex filter, the above-mentioned first coefficient update portion 200 and the second coefficient update portion 300 are that the input signal that provides except data input part 100 is different, the adder 218 of the first coefficient update portion 200 is beyond the second coefficient update portion 300 replaces with subtracter 318, and other formation is all identical with action.
That is, the multiplier 303 of the above-mentioned second coefficient update portion 300 is, is 0 if calculate the selection signal, just selects the imaginary number data xdqo of output to multiply by bad real erri output with the 3rd data selection portion 130; If be 1, just select the real data xdio of output to multiply by imaginary number mistake errq output with the 3rd data selection portion 130.In addition, above-mentioned subtracter 218 is after cutting the coefficient xdqo*erri of delayer 312 feedbacks from the conversion imaginary number coefficient qcoef that delayer 313 feeds back, by selector 317, to export to adder 306.Action afterwards is identical with the first above-mentioned coefficient update portion 200, therefore with detailed.
Equally, when digital filter of the present invention was made action with complex filter, the above-mentioned first filtering efferent 400 also had only the signal of input different with the second filtering efferent 500, and two output procedure is identical.Promptly, the multiplier 501 of the second filtering efferent 500 is, if calculating and selecting signal is 0, just the imaginary number coefficient qcoef that upgrades with the second coefficient update portion 300 multiply by the imaginary number data xqo of the selector 147 selection outputs of above-mentioned the 4th data selection portion 140, exports (xqo*qcoef); If be 1, just the imaginary number coefficient qcoef that upgrades with the second coefficient update portion 300 multiply by the real data xio of the selector 147 selection outputs of the 4th data selection portion 140, exports (xio*qcoef).At this moment, the xqo*qcoef of above-mentioned multiplier 501 outputs exports (y2=xqo*qcoef) by delayer 502 with the y2 value, and the xio*qcoef of above-mentioned multiplier 501 outputs is without delayer 502, faithfully with y3 value output (y3=xio*qcoef).
So digital filter of the present invention is made when action with complex filter, the real number output of the 1Tab complex filter by 400,500 outputs of the first and second filtering efferents and imaginary number output are just as following mathematical expression 4.
[mathematical expression 4]
Real number output=y0-y2=xio*icoef-xqo*qcoef
Imaginary number output=y1+y3=xqo*icoef+xio*qcoef
Here, xio is the signal of the symbol of delay of xi; Xqo is the signal of the symbol of delay of xq; Icoef is the real number coefficient; Qcoef is the imaginary number coefficient.
In addition, interval in Fig. 6 (a) accumulative total, export xio*icoef and xqo*icoef simultaneously; Also export xio*qcoef and xqo*qcoef simultaneously.Therefore interval in above-mentioned accumulative total, if operation y0-y2 and y1+y 3 just can obtain real number output and imaginary number output.
So digital filter of the present invention is that mode select signal is, make action at 1 o'clock with 1Tab plural number real filter with a Tab output.
Like this, the digital filter of motion of the present invention is in conjunction with the real filter of 4Tab and the complex filter of 1Tab, with a cycle unit interval time with the interior output that obtains filter, make a reckoner in a symbol clock pulse (cycle unit interval) with twice calculating of interior operation.Therefore, compare with the existing filter that complex filter once calculates with reckoner's operation of interior usefulness with a symbol clock pulse with real filter, the present invention can reduce about 69% (18/26) to the multiplier that uses and the quantity of adder.

Claims (15)

1, digital filter comprises:
Generation can determine the mode select signal of real filter, complex filter action and with in the unit period signal, makes corresponding reckoner move twice calculating and signal, the control part of exporting are selected in the calculating controlled;
According to above-mentioned mode select signal, select the real data and the imaginary number data of input, postpone respectively, and once more according to mode select signal with after calculating the data and delayed data of selecting signal to select input, for the output of coefficient update and filter, the data input part of exporting;
Above-mentioned data input part is selected the data of output to multiply by by mode select signal and is calculated the improper value of selecting signal to select, and the multiplication result with added up to by mode select signal and conversion coefficient that calculate to select signal to select, with the first coefficient update portion of a unit period time with the real number coefficient update of two coefficients of interior operation real filter or complex filter;
Above-mentioned data input part is selected the data of output to multiply by by mode select signal and is calculated the improper value of selecting signal to select, and the multiplication result with added up to by mode select signal and conversion coefficient that calculate to select signal to select, with the second coefficient update portion of a unit period time with the imaginary number coefficient update of two coefficients of interior operation real filter or complex filter;
Above-mentioned data input part multiply by two coefficients of real filter of above-mentioned first coefficient update portion output or the real number coefficient of complex filter with two data of interior selection output with a unit period time, with the first filtering efferent of a unit period time with two outputs of two Tab output of interior generation real filter or complex filter;
Above-mentioned data input part multiply by two coefficients of real filter of above-mentioned second coefficient update portion output or the imaginary number coefficient of complex filter with two data of interior selection output with a unit period time, with the second filtering efferent of a unit period time with two outputs of two Tab output of interior generation real filter or complex filter.
2, as claim item 1 described digital filter, it is characterized in that,
It is the clock pulse delay certain hour that phase place and the symbol clock pulse (clk) with unit period time is existed 1/2 gap that aforementioned calculation is selected signal.
3, as claim item 1 described digital filter, it is characterized in that,
Above-mentioned data input part comprises:
In postponing the real data and imaginary number data of setting-up time respectively, with the unit period time with interior with mode select signal with calculate and select signal to select two data, export to the first data selection portion of the first coefficient update portion;
Postponing does not respectively have to postpone and the real data and the imaginary number data of input, in the data of the data of above-mentioned input and delay, with the unit period time with interior with mode select signal with calculate to select signal to select two data, export to the second data selection portion of the first filtering efferent;
In postponing the real data and imaginary number data of setting-up time respectively, with the unit period time with interior with mode select signal with calculate and select signal to select two data, export to the 3rd data selection portion of the second coefficient update portion;
Postponing does not once more respectively have to postpone and the real data of input and the data of imaginary number data and the input of the above-mentioned second data selection portion, in the data of data of importing and delay, with the unit period time with interior with mode select signal with calculate to select signal to select two data, export to the 4th data selection portion of the second filtering efferent.
4, as claim item 3 described digital filters, it is characterized in that,
The above-mentioned first data selection portion comprises:
First delayer of the real data that postpones input with the delay of unit period signal Synchronization;
According to mode select signal, selection and output delay and one first selector in the real data that the imaginary number data imported and above-mentioned first delayer postpone;
Second delayer of the data of above-mentioned first selector output with the delay of unit period signal Synchronization;
According to mode select signal, select and export one second selector in the data of above-mentioned second data selection portion output and the real data that first delayer postpones;
According to mode select signal, select and export one third selector in the data of above-mentioned second data selection portion output and the data that above-mentioned second delayer postpones;
With a unit period signal time with interior with calculate to select signal above-mentioned second and the data exported of third selector export to the 4th selector of the above-mentioned first coefficient update portion successively.
5, as claim item 3 described digital filters, it is characterized in that,
The above-mentioned second data selection portion comprises:
First delayer of the real data that does not have to postpone and import with unit period signal time synchronization delay;
According to mode select signal, select and output not have to postpone and one first selector in the real data of the imaginary number data of input and the delay of above-mentioned first delayer;
Second delayer of the data of above-mentioned first selector output with the delay of unit period signal Synchronization;
According to mode select signal, select and output not have to postpone and one second selector in the data of the real data of input and the delay of first delayer;
According to mode select signal, select and export one third selector in the data that the data that above-mentioned first delayer postpones and second delayer postpone;
In a unit period signal, above-mentioned second and the data of third selector output export to the 4th selector of the above-mentioned first filtering efferent successively with calculating the selection signal.
6, as claim item 3 described digital filters, it is characterized in that,
Above-mentioned the 3rd data selection portion comprises:
According to mode select signal, selection and output delay and one first selector in the data that second delayer of the imaginary number data imported and the above-mentioned first data selection portion postpones;
First delayer of the data of above-mentioned first selector output with the delay of unit period signal Synchronization;
According to mode select signal, selection and output delay and one second selector in the real data that the real data imported and first delayer postpone;
Second delayer of the data of above-mentioned second selector output with the delay of unit period signal Synchronization;
According to mode select signal, select and export one third selector in the data of above-mentioned the 4th data selection portion output and the imaginary number data that first delayer postpones;
According to mode select signal, select and export one the 4th selector in the data of above-mentioned the 4th data selection portion output and the data that second delayer postpones;
In the unit period signal, select the data of above-mentioned third and fourth selector output signal to export to the 5th selector of the above-mentioned second coefficient update portion successively with calculating.
7, as claim item 3 described digital filters, it is characterized in that,
Above-mentioned the 4th data selection portion comprises:
According to mode select signal, select and output not have to postpone and one first selector in the data of second delayer delay of the imaginary number data of input and the above-mentioned second data selection portion;
First delayer of the data of above-mentioned first selector output with the delay of unit period signal Synchronization;
According to mode select signal, select and output not have to postpone and one second selector in the data of the real data of input and the delay of above-mentioned first delayer;
Second delayer of the data of above-mentioned second selector output with the delay of unit period signal Synchronization;
According to mode select signal, select and export one third selector in the dateout of the dateout of above-mentioned first selector and first delayer;
According to mode select signal, select and export one the 4th selector in the data that the data that above-mentioned first delayer postpones and second delayer postpone;
In the unit period signal, the data of above-mentioned third and fourth selector output are exported to the 5th selector of the above-mentioned second filtering efferent successively with calculating the selection signal.
8, as claim item 1 described digital filter, it is characterized in that,
The above-mentioned first coefficient update portion comprises:
In a unit period signal, the bad real of input and imaginary number mistake with calculating the first selector that the selection signal is exported successively;
According to mode select signal, one second selector in the bad real of selection and output input and the dateout of above-mentioned first selector;
The data of above-mentioned first data selection portion output multiply by the multiplier of the data of above-mentioned second selector output;
The interests portion of interests constant A is multiply by in the output of above-mentioned multiplier;
According to mode select signal, select and export one third selector in the dateout of the dateout of above-mentioned multiplier and interests portion;
The first adder that adds up to the conversion coefficient of the dateout of above-mentioned third selector and feedback;
If the aggregate result of above-mentioned first adder surpasses certain value, just be restricted to the saturated portion of certain value;
First delayer that the dateout of above-mentioned saturated portion is existed the unit period signal Synchronization delay of 1/2 gap with phase place and unit period signal;
Second delayer of the dateout of above-mentioned saturated portion with the delay of unit period signal Synchronization;
In a unit period signal, with calculating the 4th selector of selecting signal to export the data of above-mentioned first and second delayers delay successively;
According to mode select signal, select and export one the 5th selector in the dateout of the dateout of above-mentioned the 4th selector and second delayer;
The data of above-mentioned the 5th selector output are divided by the interests portion of interests constant C;
The second adder that adds up to the data of above-mentioned first and second delayers output;
With six selector of a unit period signal with the dateout of interior usefulness calculating selection signal output constant 0 successively and above-mentioned second adder;
According to mode select signal, select in the data of the data of above-mentioned the 6th selector output and the output of above-mentioned the 4th selector, export to the 7th selector of first adder as conversion coefficient.
9, as claim item 8 described digital filters, it is characterized in that,
Above-mentioned saturated portion comprises:
Extract the symbol extraction portion of symbol from the dateout of above-mentioned first adder;
Obtain the absolute value of the dateout of above-mentioned first adder, and the comparator relatively big or small with the constant B that has set;
If detect positive symbol from above-mentioned symbol extraction portion, just select positive constant B output, if detect negative symbol, just select the 8th selector of negative constant-B output;
If above-mentioned comparator is judged as above-mentioned absolute value greater than constant B, just select the output of the 8th selector, otherwise select the output of above-mentioned first adder, export to the 9th selector of above-mentioned first and second delayers.
10, as claim item 1 described digital filter, it is characterized in that,
The above-mentioned second coefficient update portion comprises:
In a unit period signal, the bad real of input and imaginary number mistake with calculating the first selector that the selection signal is exported successively;
According to mode select signal, one second selector in the bad real of selection and output input and the dateout of above-mentioned first selector;
The data of above-mentioned the 3rd data selection portion output multiply by the multiplier of the data of above-mentioned second selector output;
The interests portion of interests constant A is multiply by in the output of above-mentioned multiplier;
According to mode select signal, select and export one third selector in the dateout of the dateout of above-mentioned multiplier and interests portion;
The first adder that adds up to the conversion coefficient of the dateout of above-mentioned third selector and feedback;
If the aggregate result of above-mentioned adder surpasses certain value, just be restricted to the saturated portion of certain value;
First delayer that the dateout of above-mentioned saturated portion is existed the unit period signal Synchronization delay of 1/2 gap with phase place and unit period signal;
Second delayer of the dateout of above-mentioned saturated portion with the delay of unit period signal Synchronization;
Successively export four selector of the data of above-mentioned first and second delayers delay with interior with calculating the selection signal with a unit period signal;
According to mode select signal, select and export one the 5th selector in the dateout of the dateout of above-mentioned the 4th selector and second delayer;
The data of above-mentioned the 5th selector output are divided by the interests portion of interests constant C;
Obtain the subtracter of the difference of the data of above-mentioned first delayer delay and the data that second delayer postpones;
With six selector of a unit period signal with the dateout of interior usefulness calculating selection signal output constant 0 successively and above-mentioned subtracter;
According to mode select signal, select in the data of the data of above-mentioned the 6th selector output and the output of above-mentioned the 4th selector, export to the 7th selector of first adder as conversion coefficient.
11, as claim item 10 described digital filters, it is characterized in that,
Above-mentioned saturated portion comprises;
Extract the symbol extraction portion of symbol from the dateout of above-mentioned adder;
Obtain the absolute value of the dateout of above-mentioned adder, and the comparator relatively big or small with the constant B that has set;
If detect positive symbol from above-mentioned symbol extraction portion, just select positive constant B output, if detect negative symbol, just select the 8th selector of negative constant-B output;
If above-mentioned comparator is judged as absolute value greater than constant B, just select the output of the 8th selector, otherwise select the output of above-mentioned first adder, export to the 9th selector of above-mentioned first and second delayers.
12, as claim item 1 described digital filter, it is characterized in that,
The above-mentioned first filtering efferent is to constitute with following part:
The coefficient of above-mentioned first coefficient update portion output multiply by the multiplier of the data of above-mentioned second data selection portion output;
The data of above-mentioned multiplier output are had the delayer of the unit period signal Synchronization delay of 1/4 gap with phase place and unit period signal,
And the output of above-mentioned delayer as first output, the output of multiplier as second output.
13, as claim item 1 described digital filter, it is characterized in that,
The above-mentioned second filtering efferent is to constitute with following part:
The coefficient of above-mentioned second coefficient update portion output multiply by the multiplier of the data of above-mentioned the 4th data selection portion output;
The data of above-mentioned multiplier output are had the delayer of the unit period signal Synchronization delay of 1/4 gap with phase place and unit period signal,
And the output of above-mentioned delayer as the 3rd output, the output of multiplier as the 4th output.
14, as claim item 12 or 13 described digital filters, it is characterized in that,
Above-mentioned digital filter is according to mode select signal, when making action with real filter,
In the accumulative total interval of having set, add up to above-mentioned first to fourth output, draw final real filter output.
15. as claim item 12 or 13 described digital filters, it is characterized in that,
Above-mentioned digital filter is according to mode select signal, when making action with complex filter,
In the accumulative total interval of having set, deduct first output and the 3rd output, draw real number output, and add up to second output and the 4th output, draw imaginary number output.
CNB200510026353XA 2005-06-01 2005-06-01 Digital filter Expired - Fee Related CN100488049C (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104753496A (en) * 2015-04-09 2015-07-01 西安电子科技大学 Frequency band self-tuning three-level complex band-pass filter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104753496A (en) * 2015-04-09 2015-07-01 西安电子科技大学 Frequency band self-tuning three-level complex band-pass filter

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