CN1870757B - Multistandard video decoder - Google Patents

Multistandard video decoder Download PDF

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Publication number
CN1870757B
CN1870757B CN 200510074637 CN200510074637A CN1870757B CN 1870757 B CN1870757 B CN 1870757B CN 200510074637 CN200510074637 CN 200510074637 CN 200510074637 A CN200510074637 A CN 200510074637A CN 1870757 B CN1870757 B CN 1870757B
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decoding
information
coding
module
packing data
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CN 200510074637
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CN1870757A (en
Inventor
斯蒂芬·戈登
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Broadcom Corp
Zyray Wireless Inc
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Zyray Wireless Inc
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Priority claimed from US10/963,680 external-priority patent/US7688337B2/en
Priority claimed from US10/963,677 external-priority patent/US7613351B2/en
Priority claimed from US10/965,172 external-priority patent/US7680351B2/en
Priority claimed from US10/970,923 external-priority patent/US20050259735A1/en
Priority claimed from US10/972,931 external-priority patent/US8090028B2/en
Priority claimed from US10/974,872 external-priority patent/US7570270B2/en
Priority claimed from US10/974,179 external-priority patent/US7515637B2/en
Priority claimed from US10/981,218 external-priority patent/US7742544B2/en
Priority claimed from US10/985,110 external-priority patent/US20050259742A1/en
Priority claimed from US10/985,501 external-priority patent/US7573406B2/en
Priority claimed from US11/000,731 external-priority patent/US7590059B2/en
Application filed by Zyray Wireless Inc filed Critical Zyray Wireless Inc
Publication of CN1870757A publication Critical patent/CN1870757A/en
Publication of CN1870757B publication Critical patent/CN1870757B/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

Methods and systems for processing an encoded video stream are disclosed herein. Aspects of the method may comprise receiving on a chip, packetized data within the encoded video stream. An identifier within the received packetized data may be determined on the chip, where the identifier may define one of a plurality of encoding types associated with packets in the encoded video stream. A decoding process may be selected on the chip from a plurality of decoding processes, based on the determined identifier. A portion of the received packetized data in the encoded video stream may be decoded on the chip utilizing the selected decoding process. A header may be determined within the received packetized data that separates packets within the encoded video stream. A plurality of bytes within the received packetized data may be matched with a determined byte sequence.

Description

Multi-standard video decoder
Technical field
The present invention relates to handle the method and system of encoded video streams.
Background technology
In the video signal coding process, one or more coding techniquess, as H.261, H.263, H.263+ (Annex J), H.264, SMPTE VC-1, MPEG-1, MPEG-2 and/or MPEG-4, can be used to based on macro block by macro block this vision signal of encoding.In the video signal coding process, for example, need other other information the same with decode procedure, prediction error information can be encoded with prediction mode information.Be the coded prediction error message, before quantification or entropy coding, can use discrete cosine transform is frequency domain information with the prediction error information conversion.In this process, for example, the information of relevant prediction error may be lost.The result that this drain message causes is that the quality of decoded video signal descends.More specifically be that for example, the transform block effect may appear in the decoded video with the form of grid human factor.Other also may appear in the decoded video owing to omitting video information.
Conventional video decoder be suitable for decoding according to single coding standard as H.261, the elementary video stream of coding standard codings such as E VC-1, MPEG-1, MPEG-2 and/or MPEG-4.Elementary video stream can be encoded with single coding techniques.Yet the code stream of the arbitrary standard code in the multiple standards can be supported just using in the application space.For example, the blue light read-only memory standard of high definition DVD playing device allows video flowing to use MPEG-2, H.264 or the VC-1 coding.
Yet because of two or more decoders need be used for processing or decoding according to the elementary video stream of different coding standard code, the decoding efficiency of conventional video treatment system reduces greatly.
By below in conjunction with the accompanying drawing description of this invention, routine and conventional method and the present invention are compared, those skilled in the art understand the more limitation and the shortcoming of routine more than you know and conventional method.
Summary of the invention
The invention provides a kind of several embodiment that handle the method and system of encoded video streams.This method is included in the packing data in the received code video flowing on the chip on the one hand.The identifier in the packing data that receives can on this chip, determine one of a plurality of type of codings that this identifier definable is associated with packets of information in this encoded video streams on this chip.Coding/decoding method can be selected from a plurality of coding/decoding methods on this chip based on determined identifier.The part that this institute receives packing data in the encoded video streams can use selected coding/decoding method to decode on this chip.Separator can be determined in the reception packing data, separates the packets of information in the encoded video streams.A plurality of bytes in the reception packing data and definite byte sequence are complementary.If these a plurality of bytes determine that with this byte sequence is complementary, then receive packing data and remove this a plurality of bytes from this institute.
If determined identifier meets H.264 video coding, then the packing data that receives can use fixed-length code (FLC) (fixed length coding, abbreviation FLC) method, variable length code (varible length coding, be called for short VLC) method and/or context adaptive binary algorithm coding (context adaptive binary arithmetic coding is called for short CABAC) method decoding.If determined identifier meet VC-1, H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video coding, then the packing data that receives can be with FLC method and/or the decoding of VLC method.The packing data of this decoding comprises coding/decoding method control information and/or prediction error information.Decoded video streams can use the packing data of this decoding to generate.The decoded video streams of this generation can be used the lapped transform method and/or separate block method filtering.These a plurality of coding/decoding methods for each, the available inverse transformation of a part, re-quantization and/or the motion compensation of the packing data that receives are decoded on this chip.
An alternative embodiment of the invention provides a kind of machine readable memory, stores computer program on it, and this computer program has the executable code section of machine at least, so that this machine can be carried out the step of above-mentioned processing encoded video streams.
An aspect of of the present present invention also comprises at least one processor, the packing data in the encoded video streams on chip on the receiving chip.This processor can be determined the identifier in the packing data of receiving on this chip, one of a plurality of type of codings that this identifier definition is associated with packets of information in this encoded video streams.Coding/decoding method can be selected from a plurality of coding/decoding methods by this processor based on determined identifier.The part that this institute receives packing data in the encoded video streams can use selected coding/decoding method to decode by this processor.The separator in the packing data that receives, this separator is determined by this processor, separates the packets of information in the encoded video streams.This processor can be complementary a plurality of bytes in the reception packing data and definite byte sequence, if these a plurality of bytes determine that with this byte sequence is complementary, then this processor receives from this institute and removes this a plurality of bytes the packing data.
If determined identifier meets H.264 video coding, then the packing data that receives can be by this processor with fixed-length code (FLC) method, variable length decoding method and/or the decoding of context adaptive binary algorithm coding method.If determined identifier meet VC-1, H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video coding, then the packing data that receives can be by this processor with FLC method and/or the decoding of VLC method.The packing data of this decoding comprises coding/decoding method control information and/or prediction error information.Decoded video streams can use the packing data of this decoding to generate by processor.This processor can use the lapped transform method and/or separate the decoded video streams filtering that block method will generate.
One aspect of the present invention provides a kind of method of handling encoded video streams, and this method comprises:
Packing data on chip in the received code video flowing;
Determine that on described chip institute receives the identifier in the packing data, this identifier defines one of a plurality of type of codings that are associated with packets of information in this encoded video streams;
On described chip,, from a plurality of coding/decoding methods, select a coding/decoding method based on determined identifier; And
On described chip, use at least a portion of the packing data that receives in the selected coding/decoding method decoding and coding video flowing.
Preferably, described method further is included on the described chip initial code of determining in institute's packing data that receives, the interior packets of information of this initial code separation encoded video streams.
Preferably, described method further comprises a plurality of bytes in the reception packing data and a definite byte sequence is complementary.
Preferably, described method further comprises if these a plurality of bytes determine that with this byte sequence is complementary, then receives from this institute and remove this a plurality of bytes the packing data.
Preferably, described method further comprises if determined identifier meets H.264 video coding, then uses described at least a portion of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method, variable length code (VLC) method and context adaptive binary algorithm coding (CABAC) method.
Preferably, described method further comprises if determined identifier meets the VC-1 video coding, then uses described at least a portion of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, described method further comprises if H.261 determined identifier meets, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding one of at least, then use described at least a portion of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, described decoding packing data comprises the one at least of predict pixel information and prediction error information.
Preferably, described method comprises that further at least a portion of using described decoding packing data generates decoded video streams.
Preferably, described method further comprises, to each described a plurality of decode procedure, uses described at least a portion of the decoding of the one at least packing data that receives of inverse transformation, re-quantization and motion compensation on described chip.
According to an aspect of the present invention, provide a kind of machine-readable memory, storage has the computer program of at least one code section, and to handle encoded video streams, this at least one code section is carried out by machine, and the step of execution comprises:
Packing data on chip in the received code video flowing;
Determine that on described chip institute receives the identifier in the packing data, this identifier defines one of a plurality of type of codings that are associated with packets of information in this encoded video streams;
On described chip,, from a plurality of coding/decoding methods, select a coding/decoding method based on determined identifier; And
On described chip, use at least a portion of the packing data that receives in the selected coding/decoding method decoding and coding video flowing.
Preferably, described memory further is included on the described chip code of determining the initial code in institute's packing data that receives, the interior packets of information of described initial code separation encoded video streams.
Preferably, described memory further comprises a plurality of bytes in the reception packing data and the code that definite byte sequence is complementary.
Preferably, described memory further comprises if these a plurality of bytes determine that with this byte sequence is complementary, then receives the code that removes these a plurality of bytes the packing data from this institute.
Preferably, described memory further comprises if determined identifier meets H.264 video coding, then uses the code of described at least a portion of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method, variable length code (VLC) method and context adaptive binary algorithm coding (CABAC) method.
Preferably, described memory further comprises if determined identifier meets the VC-1 video coding, then uses the code of described at least a portion of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, described memory further comprises if H.261 determined identifier meets, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding one of at least, then use described at least a portion code of the decoding of the one at least packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, described decoding packing data comprise predict pixel information and prediction error information one of at least.
Preferably, described memory comprises that further at least a portion of using described decoding packing data generates the code of decoded video streams.
Preferably, described memory further comprises the code that uses the lapped transform method and/or separate one of at least decoded video streams that filtering generated of block method.
An aspect of of the present present invention provides a kind of system that handles encoded video streams, and this system comprises:
At least one processor, it is the packing data in the received code video flowing on chip;
Described at least one processor determines that on described chip institute receives the identifier in the packing data, and this identifier defines one of a plurality of type of codings that are associated with packets of information in this encoded video streams;
Described at least one processor is selected a coding/decoding method based on the identifier that this is determined from a plurality of coding/decoding methods on described chip; And
Described at least one processor uses at least a portion of the packing data that receives in the selected coding/decoding method decoding and coding video flowing on described chip.
Preferably, described at least one processor is definite initial code that receives in the packing data on described chip, and this initial code is separated the packets of information in encoded video streams.
Preferably, described at least one processor determines that with a plurality of bytes in the reception packing data and a byte sequence is complementary.
Preferably, if these a plurality of bytes determine that with this byte sequence is complementary, described at least one processor then receives from this institute and removes this a plurality of bytes the packing data.
Preferably, if determined identifier meets H.264 video coding, described at least one processor then uses one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method, variable length code (VLC) method and context adaptive binary algorithm coding (CABAC) method.
Preferably, if determined identifier meets the VC-1 video coding, described at least one processor then uses described at least a portion of one of at least decoding packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, if H.261 determined identifier meets, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding one of at least, described at least one processor then uses one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
Preferably, described decoding packing data comprises that predict pixel information and prediction error information are one of at least.
Preferably, described at least one processor uses at least a portion of described decoding packing data to generate decoded video streams.
Preferably, described at least one processor uses the lapped transform method to conciliate one of at least decoded video streams that filtering generated of block method.
According to an aspect of the present invention, it provides a kind of method of handling encoded video streams, and this method comprises:
Use the header information of CPU decoding from encoded video streams; And
When a described CPU decodes described header information, use the macro block information of the 2nd CPU decoding from encoded video streams.
These or other feature and advantage of the present invention will be from obtaining more fully to understand below in conjunction with the accompanying drawing detailed description of the present invention.
Description of drawings
Fig. 1 is the structure chart that has the encapsulate video payload of separator according to an embodiment of the invention.
Fig. 2 is the structure chart that the exemplary according to an embodiment of the invention interior byte of elementary video stream data is removed.
Fig. 3 A is the high-level structure chart of exemplary according to an embodiment of the invention multi-standard video decoder.
Fig. 3 B is the high-level structure chart of the multi-standard video decoder of exemplary according to an embodiment of the invention use single CPU.
Fig. 3 C is the high-level structure chart of the right multi-standard video decoder of exemplary according to an embodiment of the invention use CPU.
Fig. 4 A is the structure chart of the exemplary according to an embodiment of the invention multi-standard video decoder with hardware auxiliary block and single CPU.
Fig. 4 B is the exemplary according to an embodiment of the invention structural representation with the right multi-standard video decoder of hardware auxiliary block and CPU.
Fig. 5 is exemplary according to an embodiment of the invention when decoding H.264 video data, the structure chart of the operation of multi-standard video decoder shown in Figure 4.
Fig. 6 is exemplary according to an embodiment of the invention when decoding VC-1 video data, the structure chart of the operation of multi-standard video decoder shown in Figure 4.
Fig. 7 is exemplary according to an embodiment of the invention when decoding MPEG-1 or PMEG-2 video data, the structure chart of the operation of multi-standard video decoder shown in Figure 4.
Fig. 8 is exemplary according to an embodiment of the invention when decoding MPEG-4 video data, the structure chart of the operation of multi-standard video decoder shown in Figure 4.
Fig. 9 is the flow chart of the exemplary method of processing video data stream according to an embodiment of the invention.
Embodiment
The invention provides a kind of several embodiment that handle the method and system of encoded video streams.In the video flowing cataloged procedure, the different coding standard can be used to carry out in the elementary video stream coded data.In one aspect of the invention, multi-standard video decoder can be suitable for obtaining according to coding standard as H.261, H.263, H.263+ (Annex J), H.264, the elementary video stream of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.These many standard decoders can be provided with one or more separators in this elementary video stream, this separator can be separated the packets of information in the encapsulate video payload in this elementary video stream.Each separator comprises the initial code information and the coding type information of the beginning that shows the video payload.
This coding type information can be associated with the coding method of the corresponding video payload that is used to by encoder to encode.These many standard decoders also can remove or remove one or more bytes from the encapsulate video payload, byte such in the encapsulate video payload is inserted to avoid wrong initial code to appear in the video payload by encoder.According to this coding type information, the encapsulate video payload can be used the decoding of corresponding decoding module on chip.For example, time or spatial prediction pixel can generate from the coding/decoding method control information in the encapsulate video payload.In addition, prediction error can generate from the sampling frequency coefficient in the encapsulate video payload.Then, up time and/or spatial prediction pixel and prediction error information are rebuild decoded video streams.According to an aspect of the present invention, these many standard decoders can use single central processing unit (central processing unit is called for short CPU) to handle header information and macro block information in the packets of information in the coded bit stream.In another aspect of the present invention, can use CPU right, wherein a CPU can handle following header information, and the 2nd CPU can handle current macro information.
Fig. 1 is the structure chart that has the encapsulate video payload 100 of separator according to an embodiment of the invention.As shown in Figure 1, this encapsulate video payload 100 comprises separator 104 and elementary video stream data 105.This separator 104 comprises initial code 101 and initial code suffix 103, and can be used for as establishing start bit for encapsulate video payload 100 and establishing start bit for elementary video stream data 105 by decoded device.In addition, separator 104 comprises the relevant information of coding method with the elementary video stream data 105 that is used to encode.This elementary video stream data comprises a plurality of bytes, and each byte comprises two nibble.
Initial code 101 comprises a plurality of bytes, can be arranged to represent with unique combination the beginning of encapsulate video payload 100 in the encoded video streams.For example, initial code 101 comprises exemplary byte sequence " 00 00 01 ".Initial code suffix 103 comprises one or more bytes, be located at the initial code 101 in the encapsulate video payload 100 after.In one aspect of the invention, this initial code suffix 103 is corresponding with the coding method of coding elementary video stream data 105 in being used for encapsulate video payload 100.For example, when these coding methods are used to encode elementary video stream data 105, this initial code suffix 103 can corresponding to H.264, VC-1, MPEG-1, MPEG-2 and/or MPE-4.Before this encoded video flow data was sent to Video Decoder, initial code 101 and initial code suffix 103 can be generated by encoder.
Fig. 2 is the structure chart that the exemplary according to an embodiment of the invention interior byte of elementary video stream data is removed.As shown in Figure 2, elementary video stream data 200 comprises basic video data sequence 201 and 203.This elementary video stream data 200 can be separated the symbol precede by, comprises initial code sequence and initial code suffix, as shown in Figure 1.In the video signal coding process and encoder be after this elementary video stream data 200 generates separators, this encoder can insert one or more bytes in elementary video stream data 200, so that corresponding initial code sequence may not discerned by encoder in elementary video stream data 200 during the coding.
For example, during elementary video stream data 200 codings, encoder can use the initial code that comprises byte sequence " 00 00 01 ".During elementary video stream data 200 decodings, the initial code sequence " 00 00 01 " in the decoder possible errors identification elementary video stream data 200.For avoiding any this mistake identification of initial code sequence, encoder can insert one or more additional characters or symbol, or byte of padding, so that the initial code sequence is not discerned in elementary video stream data 200 during the decoding by mistake.For example, additional characters string or byte of padding " 03 " can be inserted in the byte sequence 205 in the basic video data sequence 201.Same, byte of padding " 03 " also can be inserted in the byte sequence 207 in the basic video data sequence 203.By this way, can stop decoder during elementary video stream 200 decodings, to discern initial code " 00 00 01 "
In elementary video stream 200 decode procedures, any additional characters that is inserted in the cataloged procedure in the elementary video stream 200 can be removed or remove to Video Decoder.Therefore, additional characters string " 03 " can be removed by the byte sequence 205 in basic video data sequence 201, and additional characters " 2 " can be removed by the byte sequence 207 in basic video data sequence 203.By this way, remove any additional characters in the elementary video stream 200 after, generate untreated video payload.Then, this untreated video payload that obtains can be by for example symbol translation device decoding.
Fig. 3 A is the high-level structure chart of exemplary multi-standard video decoder according to an embodiment of the invention.As shown in Figure 3, this multi-standard video decoder 200 can comprise memory block 301, port encoder (code-in-port, CIP) 305, code stream analyzing device 307 and processing module 303.This port encoder 305 comprises suitable circuit, logic and/or code, is suitable for obtaining elementary video stream 309.Port encoder 305 also can be suitable for establishing initial code and initial code suffix in elementary video stream 309, and removes extra byte from elementary video stream 309, generates untreated elementary video stream thus.
The new code stream information that this multi-standard video decoder 300 can use code stream analyzing device 307 to handle the initial code information and can obtain from port encoder 305.For example, code stream analyzing device 307 can be suitable for handling the header information and/or the macro block information of the untreated elementary bit stream that generates from port encoder 305.Header information from untreated elementary video stream comprises as frag info, image information, GOP/ cutting point information and/or sequence information.Frag info bag in this untreated elementary video stream that port encoder 305 generates comprises section headers information and the macro block information corresponding to specific fragment.In addition, code stream analyzing device 307 can be suitable for handling header and/or the macro block information from the untreated elementary stream that port encoder 305 obtains, and generates the coefficient of frequency information and/or the additional side information of the required quantification of macro block information decoding in this untreated elementary video stream for example.
Code stream analyzing device 307 comprises the one or more decoding auxiliary block at every kind of coding mode, can be used for this untreated elementary video stream of decoding.Output signal from code stream analyzing device 307 can be sent to processing module 303 by bus 311.This bus 311 can realize in this multi-standard video decoder, as one tunnel bus information is sent to processing module 303, to increase treatment effeciency and to simplify implementation.The temporal information that this untreated elementary video stream decode procedure generates can be stored code stream analyzing device 307 and/or 305 storages of port encoder in the module 301.This memory module 301 comprises DRAM.
In aspect exemplary one of the present invention, this code stream analyzing device 307 can use single CPU and single respective symbol translater (SI) to realize.This single CPU or SI configuration can be used for handling the complete elementary video stream that comprises initial code/suffix, header information and/or macro block information.In another aspect of the present invention, code stream analyzing device 307 can use two independent CPU and symbol translation device (SI) to realize, to improve treatment effeciency.For example, in exemplary pair of CPU/SI structure, a CPU and a SI can be used for handling the header information in the elementary video stream, and the 2nd CPU with corresponding the 2nd SI can be used for handling the macro block information from elementary bit stream.In this, follow-up header information can be handled by a CPU and a SI, and the 2nd CPU and the 2nd SI can handle current macro information simultaneously.
Processing module 303 can use the process information that is generated by code stream analyzing device 307 to generate decoded video streams 313.This processing module 303 comprises suitable circuit, logic and/or code, and can be suitable for carrying out one or more following Processing tasks: macro block filtering and/or macro block reprocessing in spatial prediction, motion compensation, re-quantization and conversion, macro block reconstruction, the loop.Each Processing tasks in the processing module 303 can use one or more auxiliary block, and this auxiliary block meets the specific coding method of the elementary video stream 33 1 that is used to encode.In this, processing module 303 can be suitable for decoding use a plurality of coding methods as H.261, H.263, H.263+ (Annex J), H.264, the elementary video stream of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.
Fig. 3 B is the high-level structure chart of the multi-standard video decoder 320 of exemplary according to an embodiment of the invention use single CPU.Shown in Fig. 3 B, this multi-standard video decoder 320 comprises memory module 321, port encoder 329, home loop central processing unit (ILCPU) 325, home loop symbol translation device (ILSI) 327 and processing module 323.This port encoder 329 comprises suitable circuit, logic and/or code, and is suitable for obtaining elementary video stream 331.This port encoder 329 also can be suitable for establishing initial code and/or initial code suffix in this elementary video stream 331, and removes extra byte from this elementary video stream 331, thereby generates untreated elementary video stream.
In an one exemplary embodiment of the present invention, this multi-standard video decoder 320 can use home loop central processing unit 325 and home loop symbol translation device 327 to handle the header information and/or the macro block information of the untreated elementary bit stream that generates from port encoder 329.Header information from untreated elementary bit stream comprises as frag info, image information, GOP/ cutting point information and/or sequence information.Frag info bag in the untreated elementary video stream that port encoder 329 generates comprises section headers information and the macro block information corresponding to specific fragment.
Home loop symbol translation device 327 comprises suitable circuit, logic and/or code, and can be suitable for handling header and/or macro block information from the untreated elementary video stream that port encoder 329 obtains, and generate as this untreated elementary video stream in the coefficient of frequency information and/or the additional side information of the required quantification of macro block information decoding.This home loop symbol translation device 327 comprises one or more decoding supplementary modules specific to each coding mode that uses, with this untreated elementary video stream of decoding.
Home loop central processing unit 325 can be suitable for by providing decoding instruction with 327 sequencing of home loop symbol translation device as providing to home loop symbol translation device 327 by bus 333.This bus 333 can realize in this multi-standard video decoder, as one tunnel bus information is sent to processing module 303, to increase treatment effeciency and to simplify implementation.The temporal information that this untreated elementary video stream decode procedure generates can be stored home loop central processing unit 325, port encoder 329 and/or 327 storages of home loop symbol translation device in the module 321.This memory module 301 comprises DRAM.
In operating process, the elementary video stream 331 of input comprise according to a plurality of coding standards as H.261, H.263, H.263+ (Annex J), H.264, the video data of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.Port encoder 329 can be suitable for detecting one or more initial code and initial code suffix that meet these elementary video stream 331 coding modes.This port encoder 329 also is suitable for generating the untreated elementary video stream that comprises header and/or macro block information.This initial code and untreated elementary video stream can be sent to home loop central processing unit 325 and home loop symbol translation device 327 by memory 321, further to handle.This home loop symbol translation device 327 uses the instruction from home loop central processing unit 325, can be suitable for handling header and/or the macro block information that port encoder 329 transmits.Then, this home loop symbol translation device 327 can generate output signal, and this output signal comprises macro block type information, clip types information, prediction mode information, motion vector information and/or the sampling frequency coefficient as obtaining.This output signal can be sent to processing module 323 by bus 333, uses during the macro block decoding.
The process information that processing module 323 can use home loop symbol translation device 327 to generate generates decoded video streams 335.This processing module 323 comprises suitable circuit, logic and/or code, is suitable for carrying out one or more following Processing tasks: macro block filtering and/or macro block reprocessing in spatial prediction, motion compensation, re-quantization and conversion, macro block reconstruction, the loop.Each Processing tasks in the processing module 323 can use one or more auxiliary block, and this auxiliary block meets the specific coding method of the elementary video stream 331 that is used to encode.In this, processing module 323 can be suitable for decoding use a plurality of coding methods as H.261, H.263, H.263+ (Annex J), H.264, the elementary video stream of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.
Fig. 3 C is the high-level structure chart of the right multi-standard video decoder 340 of exemplary according to an embodiment of the invention use CPU.Shown in Fig. 3 C, this multi-standard video decoder 340 can comprise memory module 341, external circuit central processing unit (OLCPU) 349, port encoder (CPI) 351, external circuit symbol translation device (OLSI) 353, home loop central processing unit (ILCPU) 345, home loop symbol translation device (OLSI) 347 and processing module 343.This port encoder 351 comprises suitable circuit, logic and/or code, and is suitable for obtaining elementary video stream 355.This port encoder 329 also can be suitable for establishing initial code and/or initial code suffix in this elementary video stream 355, and removes extra byte from this elementary video stream 355, thereby generates untreated elementary video stream.
In an one exemplary embodiment of the present invention, this multi-standard video decoder 320 can use CPU right, as home loop central processing unit 345 and external circuit central processing unit 349, have corresponding home loop symbol translation device 347, external circuit symbol translation device 353, to handle the header information and/or the macro block information of the untreated elementary bit stream that generates from port encoder 351 respectively.Header information from untreated elementary bit stream can comprise as frag info, image information, GOP/ cutting point information and/or sequence information.Frag info bag in the new elementary video stream that port encoder 351 generates comprises section headers information and the macro block information corresponding to specific fragment.For example, external circuit central processing unit 349 and external circuit symbol translation device 353 can be suitable for handling the header information of the new elementary bit stream that generates from port encoder 351.In addition, home loop central processing unit 345 and home loop symbol translation device 347 can be suitable for handling the macro block information of the untreated elementary bit stream that generates from port encoder 351.By this way, can in multi-standard video decoder 340, realize parallel processing, when external circuit central processing unit 349 and the following header information of external circuit symbol translation device 353 processing, home loop central processing unit 345 and home loop symbol translation device 347 can be handled current macro information.
Home loop symbol translation device 347 comprises suitable circuit, logic and/or code, and can be suitable for handling macro block information from the untreated elementary video stream that port encoder 351 obtains, and generate as this untreated elementary video stream in the coefficient of frequency information and/or the additional side information of the required quantification of macro block information decoding.This home loop symbol translation device 347 comprises one or more decoding supplementary modules specific to each coding mode that uses, with this untreated elementary video stream of decoding.External circuit symbol translation device 353 comprises suitable circuit, logic and/or code, and can be suitable for handling the header information from the untreated elementary video stream that port encoder 351 obtains.
Home loop central processing unit 345 can be suitable for by as provide decoding instruction with 347 sequencing of home loop symbol translation device by bus 357 to home loop symbol translation device 347.This bus 357 can realize in this multi-standard video decoder, as one tunnel bus information is sent to processing module 343, to increase treatment effeciency and to simplify implementation.The temporal information that this untreated elementary video stream decode procedure generates can be stored home loop central processing unit 345, external circuit central processing unit 349, external circuit symbol translation device 353, port encoder 351 and/or 347 storages of home loop symbol translation device in the module 341.This memory module 301 comprises as DRAM.
In the operating process, the elementary video stream 355 of input comprise according to a plurality of coding standards as H.261, H.263, H.263+ (Annex J), H.264, the video data of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.Port encoder 351 can be suitable for detecting one or more initial code and initial code suffix that meet these elementary video stream 355 coding modes.This port encoder 351 also is suitable for generating the untreated elementary video stream that comprises header and/or macro block information.Header information in the untreated elementary video stream that this port encoder 351 generates can be sent to external circuit central processing unit 349 and external circuit symbol translation device 353 with further processing.Initial code and macro block information in the untreated elementary video stream can be sent to home loop central processing unit 345 and home loop symbol translation device 347 by memory 341, further to handle.In aspect exemplary one of the present invention, this external circuit central processing unit 349 and external circuit symbol translation device 353 can be suitable for processing subsequent or following header information, and home loop central processing unit 345 and home loop symbol translation device 347 can be handled current macro information.
This home loop symbol translation device 347 can be suitable for handling the macro block information that port encoder 329 transmits in the untreated elementary video stream.Then, this home loop symbol translation device 347 can generate output signal, and this output signal comprises macro block type information, clip types information, prediction mode information, motion vector information and/or the sampling frequency coefficient as obtaining.This output signal can be sent to processing module 343 by bus 3 57, uses during the macro block decoding.
The process information that processing module 343 can use home loop symbol translation device 347 to generate generates decoded video streams 361.This processing module 343 comprises suitable circuit, logic and/or code, is suitable for carrying out one or more following Processing tasks: macro block filtering and/or macro block reprocessing in spatial prediction, motion compensation, re-quantization and conversion, macro block reconstruction, the loop.Each Processing tasks in the processing module 343 can use one or more auxiliary block, and this auxiliary block meets the specific coding method of the elementary video stream 331 that is used to encode.In this, processing module 323 can be suitable for decoding use a plurality of coding methods as H.261, H.263, H.263+ (Annex J), H.264, the elementary video stream of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.
Fig. 4 A is the structure chart of the exemplary according to an embodiment of the invention multi-standard video decoder with hardware auxiliary block and single CPU.Shown in Fig. 4 A, this multi-standard video decoder 400 comprises port encoder (CIP) 403, symbol translation device 405, central processing unit (CPU) 407, spatial prediction module 409, re-quantization and conversion (IQT) module 411, motion compensating module 413, reconstructor 415, home loop filter 417, frame buffer 419 and post-processing module 421.
This port encoder 403 comprises suitable circuit, logic and/or code, can be suitable for receiver, video elementary stream 401 and generate initial code, initial code suffix and untreated basic stream.Port encoder 403 comprises that initial code is sought module 423 and byte is removed module 425.This initial code is sought module 423 can be suitable for determining initial code and initial code suffix, as shown in Figure 1.Byte is removed module 425 and can be suitable for removing extra byte from video elementary code stream 401, and generates untreated basic flow data, as shown in Figure 2.After initial code, initial code suffix and untreated basic stream generated in port encoder 403, this initial code suffix 426 can be transferred into central processing unit 407, and untreated basic stream can be transferred into symbol translation device 405, with further processing.
In an one exemplary embodiment of the present invention, this multi-standard video decoder 400 can use central processing unit 407 and symbol translation device 405 to handle the header information and/or the macro block information of the untreated elementary bit stream that generates from port encoder 403.Header information from untreated elementary bit stream can comprise frag info, image information, GOP/ cutting point information and/or sequence information.The frag info bag comprises section headers information and the macro block information corresponding to specific fragment in the untreated elementary video stream that port encoder 403 generates.
Symbol translation device 405 comprises suitable circuit, logic and/or code, can be suitable for translating the untreated basic stream 424 that obtains from port encoder 403, obtain the coefficient of frequency information and/or the additional other information of the required quantification of untreated elementary video stream 424 decodings.This symbol translation device 405 also can be sent to central processing unit 407 by connecting 406 with the video information on the frame in following macroblocks and/or the untreated elementary video stream.After this central processing unit 407 obtains initial code suffix 426 from port encoder 403, can be according to the coding method relevant, one or more decoding instructions of generation symbol translation device with the initial code suffix that obtains 426.This central processing unit 407 can be suitable for by connecting 408 these decoding instructions being offered symbol translation device 405 with these symbol translation device 405 sequencing.This central processing unit 407 also can transmit decoding instruction to symbol translation device 45 by connecting 406 according to the receiver, video information on follow-up macro block or frame.
According to an aspect of the present invention, the elementary video stream 401 of input comprise according to a plurality of coding standards as H.261, H.263, H.263+ (Annex J), H.264, the video data of one of VC-1, MPEG-1, MPEG-2 and/or MPEG-4 coding.Symbol translation device 405 uses the instruction from central processing unit 407, and can be suitable for decoding one or more symbols and/or additional treatments information as header and/or macro block information, are used to finish the decoding from the untreated basic stream 424 of port encoder 403 receptions.This symbol translation device can comprise a plurality of decoding supplementary modules specific to each coding mode that is used, with the untreated basic stream 424 of decoding.
In an exemplary embodiment of the present invention, this symbol translation device 405 comprises fixed-length code (FLC) (fixed length coding, abbreviation FLC) module 427, variable length code (variblelength coding, be called for short VLC) module 429 and/or context adaptive binary algorithm coding (context adaptive binary arithmetic coding is called for short CABAC) module 433, coefficients to construct module 435 and vectorial structure module 437.Decoding supplementary module in the symbol translation device 405 can be used for obtaining and being sent to the coding/decoding method information decoding process of central processing unit 407 according to the initial code suffix 426 that generates from port encoder 403.FLC module 427, VLC module 429 and CABAC module 433 can be used for the single grammer of decoding/translation unit by symbol translation device 405, and this single grammer unit is from the untreated basic stream 424 that uses fixed-length code (FLC), variable length code or CABAC coding techniques coding respectively.
Coefficients to construct module 435 can be suitable for generating one or more sampling frequency coefficients from untreated basic stream 424.The coefficient of frequency of the quantification that this coefficients to construct module 435 generates is used in the multi-standard video decoder 400 subsequently, to generate the prediction error information of using in one or more macro block process of reconstruction.The sampling frequency coefficient of this generation can be sent to IQT module 411 by symbol translation device 405, with further processing.
Similarly, vectorial structure module 437 can be suitable for generating one or more motion vectors from untreated basic stream 424.The motion vector that this vectorial structure module 437 generates can be used in the multi-standard video decoder 400, to generate the predict pixel of using in one or more macro block process of reconstruction.The motion vector information of this generation can be sent to motion compensating module 413 by the symbol translation device, with further processing.
Spatial prediction module 409 comprises suitable circuit, logic and/or code, can be suitable for generating rebuilt device 415 and be used for the predict pixel of generating solution decoding macroblock.This spatial prediction module 409 can be suitable for as obtaining macro block type information, clip types information and/or prediction mode information from the symbol translation device.Then, this spatial prediction module 409 can use obtained macro block type information, clip types information and/or prediction mode information be macro block generation forecast pixel predicted on the space.
Motion compensating module 413 comprises suitable circuit, logic and/or code, can be suitable for using the motion vector information that receives from symbol translation device 405, generation forecast pixel.For example, this motion compensating module 413 can be last predicted macro block generation forecast pixel of time, and the motion compensation vector in frame/territory that can be adjacent with present frame/territory is associated.This motion compensating module 413 can obtain formerly and/or frame/territory subsequently from frame buffer 419, and uses elder generation and/or the frame subsequently/interior temporal encoded pixels of territory prediction current macro that obtains.
This motion compensating module 413 comprises a plurality of motion compensation supplementary modules, can be used for the method generation forecast pixel according to the untreated basic flow data 424 that is used to encode.For example, this motion compensating module 413 comprises that scope resets module 447, intensity compensation module 449, insert module 451, variable block length module 453 and bi-directional predicted module 455.This insert module 451 can be suitable for using the motion vector information that receives from symbol translation device 45 to insert in the present frame one or more predict pixel and insert one or more times and go up the reference frame adjacent with present frame.
If only use a reference frame to insert predict pixel, this insert module 451 can be used for the generation forecast pixel.Yet if be used to more than a prediction reference frame in the time prediction process of current pixel, motion compensating module 413 can use bi-directional predicted module 455 generation forecast pixels.For example, if several reference frame is used to the prediction of current pixel, bi-directional predicted module 455 can be determined the mean value of current predict pixel as the predict pixel in the reference frame.
But scope is reseted the cataloged procedure that module 447 passive movement compensating modules 413 are used for the untreated basic stream of VC-1 standard code.More specifically be, this scope is reseted module 447 and is used in before insert module 451 insertions, resets the dynamic range of reference frame.But intensity compensation module 449 passive movement compensating modules 413 are used for the strength level of reference frame being adjusted to the strength level of present frame before insert module 451 is inserted.
But variable block length module 453 passive movement compensating modules 413 are used to control the application from the reference frame of frame buffer 419 acquisitions.For example, this variable block length module 453 can from frame buffer 419 get one 16 * 16,16 * 8 and/or 4 * 4 Pixel Dimensions macro blocks with the time prediction that is used for pixel in the current macro during.When needing during the motion compensated prediction in the motion compensating module 413, other macro blocks and/or frame size also can be supported by frame buffer 419.
IQT module 411 comprises suitable circuit, logic and/or code, and the sampling frequency coefficient that can be suitable for receiving from the symbol translation device is converted to one or more prediction error.More specifically be that this IQT module 411 can be suitable for using inverse quantization module 443 and inverse transform module 445 the sampling frequency transformation of coefficient to be returned spatial domain, generation forecast error message thus.Then, the prediction error information that this IQT module 411 generates is transferred into reconstructor 415, further handles during rebuilding at macro block.
Contrary sawtooth module 439 can be used for rearranging the sampling frequency coefficient that receives from symbol translation device 405 before by inverse transform module 445 inverse transformations by IQT module 411.The sampling frequency coefficient that symbol translation device 405 generates can be arranged sawtooth (Z-shaped) scanning sequency, so that coding.Therefore contrary sawtooth module 439 can use one or more look-up tables with the sampling frequency coefficient with as continuous order arrange.
According to untreated basic stream 424 ground coding methods, IQT module 41 can be used AC/DC prediction module 441 during the prediction error information decoding.For example, the sampling frequency coefficient can use prediction residue and the prediction error from neighbor, is encoded in untreated basic stream 424.Further, the DC prediction in the AC/DC prediction module 441 can be corresponding to the employed zero frequency coefficient of generation forecast error message.AC prediction in the AC/DC prediction module 441 can be corresponding to the employed low frequency coefficients of generation forecast error message.It is 10/963 that operational other information of symbol translation device, motion compensating module, spatial prediction module and re-quantization and conversion module are exposed in sequence number more fully, 677 (the Institution Code case is numbered 15748US02), the applying date are in the U.S. Patent application on October 13rd, 2004, and this application is in this conduct reference comprehensively.
Reconstructor 415 can be suitable for obtaining spatial prediction pixel or time prediction pixel from spatial prediction module 409 or motion compensating module respectively.In addition, this reconstructor 415 can be suitable for obtaining the prediction error information that IQT module 411 generates.Then, this reconstructor can use predict pixel and prediction error information to rebuild current macro.This reconstruction macro block can be sent to home loop filter 417 to be for further processing.
This home loop filter 417 comprises suitable circuit, logic and/or code, can be suitable for decoding/reconstruction macro block that further filtering obtains from reconstructor 415.According to untreated basic stream 424 ground coding methods, this home loop filter 417 can comprise the lapped transform module 457 and the module 459 of deblocking.This lapped transform module 457 can be used for the process of filtering of the macro block that generates from the untreated basic stream 424 with the VC-1 standard code.More specifically be that the macro block that lapped transform module 457 can be applied to lapped transform to rebuild is to reduce along the edge human factor at the one or more edges of macro block of this reconstruction.Similarly, the module 459 of deblocking also can be used to reduce along the one or more border lands of the macro block of this reconstruction edge human factor and transform block effect by home loop filter 417.Deblocking in the decoder and being exposed in sequence number more fully with last other the relevant information of storage application of deblocking is 10/965,172 (the Institution Code case is numbered 15756US02), the applying date are that on October 13rd, 2004 and sequence number are 10/972,931 (the Institution Code case is numbered 15757US02), the applying date are in the U.S. Patent application on October 25th, 2004, and this two application is in this conduct reference comprehensively.
Rebuild macro block by 417 filtering of home loop filter after, additional reprocessing can be carried out by post-processing module 421.According to the coding method of new basic stream 424, post-processing module can be used one or more following reprocessing supplementary modules: scope is reseted module 461, size adjustment module 463, the module of deblocking 465 and/or the module 467 of unlinking.If in the process with the VC-1 standard code, the dynamic range of a macro block or one group of macro block is changed, and then this scope is reseted module 46 and can be post-treated module 421 uses.By this way, all are sent to the decoded macroblock 469 that shows preprocessor and are described by same dynamic range.
Size adjustment module 463 can be post-treated module 421 and be used for during convergent-divergent/coding of adjustment size by the macro block of size upgrade or downgrade.By using size adjustment module 463, post-processing module 421 can generate the macro block 469 of the decoding with identical definition.The module of unlinking 467 can be used for slackening " mosquito noise " in the reconstruct macro block that the AC coefficient of excessive quantification generates.The module of deblocking 465 is similar to the module 459 of deblocking in the home loop filter 417, can be used for further reducing the edge human factor, and has precedence over macro block is sent to as showing preprocessor, and conversion is along the blocking effect at the one or more edges of macro block of this reconstruction.
Fig. 4 B is the exemplary according to an embodiment of the invention structural representation with the right multi-standard video decoder of hardware auxiliary block and CPU.Shown in Fig. 4 B, this multi-standard video decoder 470 comprises port encoder (CIP) 471, external circuit central processing unit (OLCPU) 473, external circuit symbol translation device (OLSI) 475, home loop central processing unit (ILCPU) 477 and home loop symbol translation device (ILSI) 479.This multi-standard video decoder 470 also can comprise spatial prediction module, re-quantization and conversion module, motion compensating module, rebuilding module, home loop filtration module, frame buffer module and post-processing module (not showing among Fig. 4 B), as the specification specified and the description of multi-standard video encoder among Fig. 4 A.
In an one exemplary embodiment of the present invention, the header information that many standard decoders 470 can use external circuit central processing unit 473 and external circuit symbol translation device 475 to handle from video elementary bit stream 480.Home loop central processing unit 477 and home loop symbol translation device 479 can be used for handling the macro block information from video elementary bit stream 480.By this way, can in multi-standard video decoder 470, realize parallel processing, when external circuit central processing unit 473 and external circuit symbol translation device 475 can be handled following header information, home loop central processing unit 477 and home loop symbol translation device 479 can be handled current macro information.Header information from elementary bit stream 480 can comprise as frag info, image information, GOP/ cutting point information and/or sequence information.
In operating process, but port encoder 471 receiver, video elementary streams 480 and generate initial code and initial code suffix 481 and untreated basic stream 482.This initial code and initial code suffix 481 are transferred into external circuit central processing unit 473 and handle, and untreated basic stream 482 is transferred into external circuit symbol translation device 475 and handles.External circuit central processing unit 473 and external circuit symbol translation device 475 can be suitable for only handling the header information from initial code and initial code suffix 481 and untreated basic stream 482.External circuit central processing unit 473 is by being connected with the off-line processing system for video as system's delivery port 483.
External circuit symbol translation device 475 comprises variable length code (varible length coding is called for short VLC) module 484 and fixed-length code (FLC) (fixed length coding is called for short FLC) module 472.This VLC module 484 and FLC module 472 can be used for the decoding header information of the untreated basic stream 482 that receives from port decode device 471.For example, header information 485 can be taken out from untreated basic stream 482, generates output bit flow 486 thus.This output bit flow 486 comprises the macro block relevant information, and can be sent to home loop symbol translation device 479 and further handle.After the header information that external circuit central processing unit 473 is handled from initial code and initial code suffix 481, result treatment control information 476 can be transferred into home loop central processing unit 477 and further handle.This process control information 476 comprises control information, and this control information is corresponding to the packets of information that comprises macro block information, as the packets of information in the output bit flow 486.
When external circuit central processing unit 473 and external circuit symbol translation device 475 can be handled follow-up header information, it was that current macro is handled the information relevant with macro block simultaneously that home loop central processing unit 477 can be suitable for home loop symbol translation device 479.Home loop symbol translation device 479, similar to the symbol translation device 405 of Fig. 4 A, can be suitable for generating output signal 487.This output signal comprises macro block type information, clip types information, prediction mode information, motion vector information and/or the sampling frequency coefficient as obtaining.The macro block type information of this acquisition, clip types information and/or prediction mode information can be sent to spatial prediction module (figure does not show), spatial prediction module 409 shown in Fig. 4 A, and reaching with further processing is the macro block generation forecast pixel of predicting on the space.
Motion vector information 490 can be sent to motion compensating module (figure does not show), the motion compensating module 413 shown in Fig. 4 A, and reaching with further processing is the macro block generation forecast pixel that the time goes up prediction.Sampling frequency coefficient 489 can be sent to re-quantization and conversion module (figure does not show), and re-quantization shown in Fig. 4 A and conversion module 411 are with the prediction error of using during further processing and the decoding of generation macro block.
Fig. 5 is exemplary according to an embodiment of the invention when decoding H.264 video data, the structure chart of the operation of multi-standard video decoder 500 shown in Figure 4.As shown in Figure 5, this multi-standard video decoder 500 can be suitable for handling the video elementary code stream 401 that uses the coding of coding techniques H.264.Port encoder 403 can use initial code to seek module 423 to determine initial code and initial code suffix, uses byte to remove module 425 and removes extra byte from encoded video elementary stream 401 H.264.
Symbol translation device 405 can be suitable for translating the H.264 untreated basic stream 424 that obtains from port encoder 403, obtaining sampling frequency coefficient information and/or additional other information, the macro block type information, clip types information, prediction mode information and/or the motion vector information that need as untreated elementary video stream 424 decodings H.264.In sampling frequency coefficient information and/or the additional other information generative process, symbol translation device 405 can receive the instruction of central processing unit 407, and provides successive character information to central processing unit 407.In addition, the symbol translation device can use the one or more of following supplementary module: FLC module 427, VLC module 429, CABAC module 433, coefficients to construct module 435 and/or vectorial structure module 437.
The re-quantization coefficient of frequency can be sent to IQT module 411 from symbol translation device 405, but the generation forecast error message.IQT module 411 can be used contrary sawtooth module 439, inverse quantization module 443 and/or inverse transform module 445 generation forecast error messages.Other information from symbol translation device 405 can be transferred into spatial prediction module 409 or motion compensating module 413, generation forecast pixel.Motion compensating module 413 can use frame buffer 419 and intensity compensation module 449, insert module 451, variable block length module 453 and/or the predict pixel of bi-directional predicted module on 455 rise times.
Then, reconstructor 415 can be used to use respectively the predict pixel information that obtains from spatial prediction module 409 or motion compensating module 413 by many standard decoders 500, and from the prediction error information that IQT module 411 obtains, rebuilds current macro.The macro block of rebuilding can be used module 459 filtering of deblocking by home loop filter 417.Filtered macro block can further be post-treated module 421 and handle.Post-processing module 421 can use the module 467 of unlinking to generate the macro block 469 of decoding.Then, the macro block 469 of this decoding can be transferred into as showing preprocessor.
Fig. 6 is according to the present invention and embodiment exemplary when decoding VC-1 video data, the structure chart of the operation of multi-standard video decoder 600 shown in Figure 4.As shown in Figure 6, this multi-standard video decoder 600 can be suitable for handling the video elementary code stream 401 that uses VC-1 coding techniques coding.Port encoder 403 can use initial code to seek module 423 definite initial code and initial code suffix, uses byte to remove module 425 and removes extra byte from VC-1 encoded video elementary stream 401.
Symbol translation device 405 can be suitable for translating the untreated basic stream 424 of VC-1 that obtains from port encoder 403, to obtain sampling frequency coefficient information and/or additional other information, untreated elementary video stream 424 decodings need as VC-1 macro block type information, clip types information, prediction mode information and/or motion vector information.In sampling frequency coefficient information and/or the additional other information generative process, symbol translation device 405 can receive the instruction of central processing unit 407, and provides successive character information to central processing unit 407.In addition, the symbol translation device can use the one or more of following supplementary module: FLC module 427, VLC module 429, coefficients to construct module 43 5 and/or vectorial structure module 437.
The re-quantization coefficient of frequency can be sent to IQT module 411 from symbol translation device 405, but the generation forecast error message.IQT module 411 can be used contrary sawtooth module 439, AC/DC prediction module 441, inverse quantization module 443 and/or inverse transform module 445 generation forecast error messages.Other information from symbol translation device 405 can be transferred into motion compensating module 413, the generation forecast pixel.Motion compensating module 413 can use frame buffer 419 and intensity compensation module 449, scope to reset module 447, insert module 451, variable block length module 453 and/or the predict pixel of bi-directional predicted module on 455 rise times.Frame buffer 419 can be suitable for storage and provide at least two reference frame/pictures to motion compensating module 413.
Then, reconstructor 415 can be used to use the predict pixel information that obtains from motion compensating module 413 by many standard decoders 600, and from the prediction error information that IQT module 411 obtains, rebuilds current macro.The macro block of rebuilding can be used deblock module 459 and/or 457 filtering of lapped transform module by home loop filter 417.Filtered macro block can further be post-treated module 421 and handle.Post-processing module 421 can use the module 467 of unlinking, scope to reset module 461, size adjustment module 463 and/or the module 465 of deblocking generates the macro block 469 of decoding.Then, the macro block 469 of this decoding can be transferred into as showing preprocessor.
Fig. 7 is exemplary according to an embodiment of the invention when decoding MPEG-1 or PMEG-2 video data, the structure chart of the operation of multi-standard video decoder 700 shown in Figure 4.As shown in Figure 7, this multi-standard video decoder 700 can be suitable for handling the video elementary code stream 401 that uses MPEG-1 or MPEG-2 coding techniques coding.Initial code and initial code suffix that port encoder 403 can use initial code searching module 423 to determine in MPEG-1 or the MPEG-2 encoded video elementary stream 401.
Symbol translation device 405 can be suitable for translating MPEG-1 or the untreated basic stream 424 of MPEG-2 that obtains from port encoder 403, obtaining sampling frequency coefficient information and/or additional other information, the macro block type information, clip types information, prediction mode information and/or the motion vector information that need as MPEG-1 or untreated elementary video stream 424 decodings of MPEG-2.In sampling frequency coefficient information and/or the additional other information generative process, symbol translation device 405 can receive the instruction of central processing unit 407, and provides successive character information to central processing unit 407.In addition, the symbol translation device can use the one or more of following supplementary module: FLC module 427, VLC module 429, coefficients to construct module 435 and/or vectorial structure module 437.
The re-quantization coefficient of frequency can be sent to IQT module 411 from symbol translation device 405, but the generation forecast error message.IQT module 411 can be used contrary sawtooth module 439, inverse quantization module 443 and/or inverse transform module 445 generation forecast error messages.Other information from symbol translation device 405 can be transferred into motion compensating module 413, the generation forecast pixel.Motion compensating module 413 can use frame buffer 419 and insert module 451, variable block length module 453 and/or the predict pixel of bi-directional predicted module on 455 rise times.Frame buffer 419 can be suitable for storage and provide at least two reference frame/pictures to motion compensating module 413.
Then, reconstructor 415 can be used to use the predict pixel information that obtains from motion compensating module 413 by many standard decoders 700, and from the prediction error information that IQT module 411 obtains, rebuilds current macro.The macro block of rebuilding can further be post-treated module 421 and handle.Post-processing module 421 can be used the macro block 469 of the unlink module 467 and/or the module 465 generation decodings of deblocking.Then, the macro block 469 of this decoding can be transferred into as showing preprocessor.
Fig. 8 is exemplary according to an embodiment of the invention when decoding MPEG-4 video data, the structure chart of the operation of multi-standard video decoder 800 shown in Figure 4.As shown in Figure 8, this multi-standard video decoder 800 can be suitable for handling the video elementary code stream 401 that uses MPEG-4 coding techniques coding.Port encoder 403 can use initial code to seek initial code and initial code suffix that module 423 is determined in the MPEG-4 encoded video elementary stream 401.
Symbol translation device 405 can be suitable for translating the untreated basic stream 424 of MPEG-4 that obtains from port encoder 403, to obtain sampling frequency coefficient information and/or additional other information, untreated elementary video stream 424 decodings need as MPEG-4 macro block type information, clip types information, prediction mode information and/or motion vector information.In sampling frequency coefficient information and/or the additional other information generative process, symbol translation device 405 can receive the instruction of central processing unit 407, and provides successive character information to central processing unit 407.In addition, the symbol translation device can use the one or more of following supplementary module: FLC module 427, VLC module 429, coefficients to construct module 43 5 and/or vectorial structure module 437.
The re-quantization coefficient of frequency can be sent to IQT module 411 from symbol translation device 405, but the generation forecast error message.IQT module 411 can be used contrary sawtooth module 439, AC/DC prediction module 441, inverse quantization module 443 and/or inverse transform module 445 generation forecast error messages.Other information from symbol translation device 405 can be transferred into motion compensating module 413, the generation forecast pixel.Motion compensating module 413 can use frame buffer 419 and insert module 451, variable block length module 453 and/or the predict pixel of bi-directional predicted module on 455 rise times.Frame buffer 419 can be suitable for storage and provide at least two reference frame/pictures to motion compensating module 413.
Then, reconstructor 415 can be used to use the predict pixel information that obtains from motion compensating module 413 by many standard decoders 800, and from the prediction error information that IQT module 411 obtains, rebuilds current macro.The macro block of rebuilding can further be post-treated module 421 and handle.Post-processing module 421 can be used the macro block 469 of the unlink module 467 and/or the module 465 generation decodings of deblocking.Then, the macro block 469 of this decoding can be transferred into as showing preprocessor.
Fig. 9 is the flow chart of the exemplary method 900 of processing video data stream according to an embodiment of the invention.As shown in Figure 9, in step 901, the packing data in the receiver, video elementary stream, wherein video elementary code stream can be encoded according to one of a plurality of coding methods.In step 903, determine the initial code in this packing data, wherein this initial code definable encapsulate video payload.In step 905, determine the identifier in the packing data, this identifier define one or more with this video elementary code stream in the related type of coding of packets of information.In step 907,, from a plurality of coding/decoding methods, select a coding/decoding method based on determined identifier.In step 909, based on selected coding/decoding method, defined encapsulate video payload can be decoded.
Therefore, the present invention can realize in hardware, software, firmware or combination of hardware.The present invention can realize with centralized system at least one computer system or realize that with distribution mode this distribution mode is meant that different elements is distributed in several interconnective computer systems.The equipment that any computer or other are suitable for carrying out method as described herein all is fit to.The combination of a kind of typical hardware, software and firmware can be the multi-application computer system with computer program, and wherein computer program can be downloaded and carry out, and the control computer system is so that computer system is carried out method as described herein.
One embodiment of the present of invention also can be used as the component level product, realize as one chip, special purpose integrated circuit (ASIC), perhaps have to be integrated in one chip, not at the same level with other parts of system, realize as separate elements.The integrated level of this system is considered preliminary definite by speed or cost.Because the modern processors kind is numerous and diverse, it is possible using the processor of viable commercial, and the method that this processor can exceed the ASIC implementation of existing system realizes.As selection, if processor is effectively as ASIC nuclear or logical block, the part that so commercial effective processor can be used as the ASIC equipment that has various functions, realizes as firmware is implemented.
The present invention also can be embedded in the computer program, and this computer program comprises that all can carry out the feature of method as described herein, and in being downloaded to computer system the time, can carry out these methods.Here said computer program can adopt any expression-form of one group of instruction, as with any language, code or symbolic formulation, the instruction of this group can make a system with information processing capability carry out directly or one of should instruct in the following manner or all after the processing: a) convert another kind of language, code or symbol to, b) duplicate with the different materials form, carry out specific function.Yet the additive method of the understandable computer program of those of ordinary skill in the art can be expected by the present invention.
Though the present invention is described with reference to some embodiment, is appreciated that various changes to those skilled in the art and is equal to and not depart from the scope of the present invention.In addition, much the suitable particular case of content of the present invention and the modification of material are not departed from the scope of the present invention yet.Therefore, the invention is not restricted to the specific embodiment that disclosed, the present invention will comprise that all fall into the embodiment of claim scope.
The application advocates that the applying date is the priority of the U.S. Provisional Patent Application 60/568926 (the numbering 15747US01 of agency) on May 21st, 2004.This application is in this comprehensive reference as the application.
The application is relevant with following application, and wherein every application all can be in this comprehensive reference as the application:
U.S. Patent Application Serial Number is 10/963,677 (the case numbering 15748US02 of agency), and the applying date is on October 13rd, 2004;
U.S. Patent Application Serial Number is 10/985,501 (the case numbering 15749US02 of agency), and the applying date is on November 10th, 2004;
U.S. Patent Application Serial Number is (the case numbering 15750US02 of agency), the applying date is 2004
U.S. Patent Application Serial Number is 10/985,110 (the case numbering 15751US02 of agency), and the applying date is on November 10th, 2004;
U.S. Patent Application Serial Number is 10/981,218 (the case numbering 15754US02 of agency), and the applying date is on November 04th, 2004;
U.S. Patent Application Serial Number is 10/965,172 (the case numbering 15756US02 of agency), and the applying date is on October 13rd, 2004;
U.S. Patent Application Serial Number is 10/971,931 (the case numbering 15757US02 of agency), and the applying date is on October 25th, 2004;
U.S. Patent Application Serial Number is 10/974,179 (the case numbering 15759US02 of agency), and the applying date is on October 27th, 2004;
U.S. Patent Application Serial Number is 10/974,872 (the case numbering 15760US02 of agency), and the applying date is on October 27th, 2004;
U.S. Patent Application Serial Number is 10/970,923 (the case numbering 15761US02 of agency), and the applying date is on October 21st, 2004;
U.S. Patent Application Serial Number is 10/963,680 (the case numbering 15762US02 of agency), and the applying date is on October 13rd, 2004;
U.S. Patent Application Serial Number is (the case numbering 15763US02 of agency), the applying date is 2004
U.S. Patent Application Serial Number is (the case numbering 15792US01 of agency), the applying date is 2004
U.S. Patent Application Serial Number is (the case numbering 15810US02 of agency), the applying date is 2004 And
U.S. Patent Application Serial Number is (the case numbering 15811US02 of agency), the applying date is 2004

Claims (13)

1. a method of handling encoded video streams is characterized in that, comprising:
Packing data on chip in the received code video flowing;
Determine that on described chip institute receives the identifier in the packing data, this identifier defines one of a plurality of type of codings that are associated with packets of information in this encoded video streams;
On described chip,, from a plurality of coding/decoding methods, select a coding/decoding method based on determined identifier; And
On described chip, use at least a portion of the packing data that receives in the selected coding/decoding method decoding and coding video flowing;
Definite initial code that receives in the packing data on described chip, this initial code is separated the packets of information in encoded video streams;
A plurality of bytes in the reception packing data and one are determined that byte sequence matches;
If these a plurality of bytes are determined the byte sequence coupling with this, then receive packing data and remove this a plurality of bytes from this institute;
If determined identifier meets H.264 video coding, then use one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method, variable length code (VLC) method and context adaptive binary algorithm coding (CABAC) method;
Use the header information of CPU decoding from encoded video streams; And
When a described CPU decodes described header information, use the macro block information of the 2nd CPU decoding from encoded video streams.
2. the method for processing encoded video streams according to claim 1 is characterized in that, this method further comprises:
If determined identifier meets the VC-1 video coding, then use fixed-length code (FLC) (FLC) method and variable length code (VLC) method one of at least, the code of described at least a portion of the decoding packing data that receives.
3. the method for processing encoded video streams according to claim 1 is characterized in that, this method further comprises:
If H.261 determined identifier meets, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding one of at least, then use one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
4. the method for processing encoded video streams according to claim 1 is characterized in that, described decoding packing data comprises that predict pixel information and prediction error information are one of at least.
5. the method for processing encoded video streams according to claim 1 is characterized in that, this method further comprises: use at least a portion of described decoding packing data to generate decoded video streams.
6. the method for processing encoded video streams according to claim 1, it is characterized in that, this method further comprises: to each described a plurality of decode procedure, use one of at least described at least a portion of the decoding packing data that receives of inverse transformation, re-quantization and motion compensation on described chip.
7. a system that handles encoded video streams is characterized in that, comprising:
At least one processor, the packing data on chip in the received code video flowing;
Described at least one processor determines that on described chip institute receives the identifier in the packing data, and this identifier defines one of a plurality of type of codings that are associated with packets of information in this encoded video streams;
Described at least one processor is selected a coding/decoding method based on the identifier that this is determined from a plurality of coding/decoding methods on described chip; And
Described at least one processor uses at least a portion of the packing data that receives in the selected coding/decoding method decoding and coding video flowing on described chip; Definite initial code that receives in the packing data on described chip, this initial code is separated the packets of information in encoded video streams; A plurality of bytes in the reception packing data and one are determined that byte sequence matches; If these a plurality of bytes are determined the byte sequence coupling with this, then described at least one processor receives packing data from this institute and removes this a plurality of bytes.
8. system according to claim 7, it is characterized in that, if determined identifier meets H.264 video coding, then described at least one processor uses one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method, variable length code (VLC) method and context adaptive binary algorithm coding (CABAC) method.
9. system according to claim 7, it is characterized in that, if determined identifier meets the VC-1 video coding, then described at least one processor uses one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
10. system according to claim 7, it is characterized in that, if H.261 determined identifier meets, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding one of at least, then described at least one processor uses one of at least described at least a portion of the decoding packing data that receives of fixed-length code (FLC) (FLC) method and variable length code (VLC) method.
11. system according to claim 7 is characterized in that, described decoding packing data comprises that predict pixel information and prediction error information are one of at least.
12. system according to claim 7 is characterized in that, described at least one processor uses at least a portion of described decoding packing data to generate decoded video streams.
13. system according to claim 7 is characterized in that, described at least one processor uses the lapped transform method to conciliate one of at least decoded video streams that filtering generated of block method.
CN 200510074637 2004-05-21 2005-05-23 Multistandard video decoder Active CN1870757B (en)

Applications Claiming Priority (23)

Application Number Priority Date Filing Date Title
US60/573,357 2004-05-21
US10/963,680 US7688337B2 (en) 2004-05-21 2004-10-13 System and method for reducing image scaling complexity with flexible scaling factors
US10/963,677 2004-10-13
US10/965,172 US7680351B2 (en) 2004-05-21 2004-10-13 Video deblocking method and apparatus
US10/965,172 2004-10-13
US10/963,677 US7613351B2 (en) 2004-05-21 2004-10-13 Video decoder with deblocker within decoding loop
US10/963,680 2004-10-13
US10/970,923 US20050259735A1 (en) 2004-05-21 2004-10-21 System and method for video error masking using standard prediction
US10/970,923 2004-10-21
US10/972,931 US8090028B2 (en) 2004-05-21 2004-10-25 Video deblocking memory utilization
US10/972,931 2004-10-25
US10/974,872 2004-10-27
US10/974,872 US7570270B2 (en) 2004-05-21 2004-10-27 Buffer for driving display with asynchronous display engine
US10/974,179 US7515637B2 (en) 2004-05-21 2004-10-27 Video decoding for motion compensation with weighted prediction
US10/974,179 2004-10-27
US10/981,218 2004-11-04
US10/981,218 US7742544B2 (en) 2004-05-21 2004-11-04 System and method for efficient CABAC clock
US10/985,110 US20050259742A1 (en) 2004-05-21 2004-11-10 System and method for choosing tables in CAVLC
US10/985,110 2004-11-10
US10/985,501 US7573406B2 (en) 2004-05-21 2004-11-10 System and method for decoding context adaptive variable length coding
US10/985,501 2004-11-10
US11/000,731 US7590059B2 (en) 2004-05-21 2004-12-01 Multistandard video decoder
US11/000,731 2004-12-01

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CN103369311A (en) * 2012-04-04 2013-10-23 朱洪波 Method for preventing conflict of initial code
CN107979783B (en) * 2016-10-25 2020-03-24 杭州海康威视数字技术股份有限公司 Streaming data analysis method and device and electronic equipment
CN107977551B (en) * 2016-10-25 2020-07-03 杭州海康威视数字技术股份有限公司 Method and device for protecting file and electronic equipment

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