CN1860615A - 混合双极－mos沟槽栅极半导体器件 - Google Patents

混合双极－mos沟槽栅极半导体器件 Download PDF

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CN1860615A
CN1860615A CNA2004800283096A CN200480028309A CN1860615A CN 1860615 A CN1860615 A CN 1860615A CN A2004800283096 A CNA2004800283096 A CN A2004800283096A CN 200480028309 A CN200480028309 A CN 200480028309A CN 1860615 A CN1860615 A CN 1860615A
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T·莱塔维克
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Koninklijke Philips NV
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Abstract

公开了一种MOS器件(101)，具有被短接在一起的本体和沟槽栅极(110、102)，并独立地偏置源极(106)。结果，该器件用作具有与其并联的NPN双极晶体管的沟槽栅MOS器件，其允许更小尺寸的器件，以进行DC－DC转换。

Description

混合双极-MOS沟槽栅极半导体器件
技术领域
本发明涉及半导体，更具体地，涉及降低半导体器件开态电阻的改善器件。本发明特别应用于基于沟槽的器件中，其中本发明实现了与MOS器件并联的双极晶体管，以减小开态电阻，或者对于相同水平的总功耗来说，实质上等于减小了管芯尺寸。
背景技术
金属氧化物半导体沟槽器件(“沟槽MOS”)是本技术领域公知的器件。当用于完成DC-DC转换器时，这种MOS器件的优点的关键特征是对于给定的总功耗来说所需要的器件尺寸(面积)。在本领域的现状中，对特定的低功耗来说需要相对大的MOS器件，以实现用于高端微处理器的电源。
发明内容
本发明的目的在于提供一种可以在显著减小的尺寸下提供给定功耗的混合MOS器件，由此产生更低成本的器件。
本发明的目的还在于提供一种可以经受高击穿电压的混合MOS器件，大约200伏。
根据本发明涉及改进的混合MOS器件克服了现有技术的上述和其他问题。根据本发明，在混合模式中利用具有单一或多个栅(场)氧化物厚度的沟槽MOS型器件，其中一个电极用于被短接在一起的栅极和基极，另一个电极用作MOS器件的源极和双极器件的发射极。实质上，偏置该器件，以用作并联的MOS器件和双极器件。
在具体的改进实施例中，栅氧化物的厚度可以沿其硅沟槽的不同长度而不同，以便可以获得更高的击穿电压，并获得具有特定开态电阻和总电容的更有利的折衷方案。
附图说明
图1描绘了本发明的一个示例性实施例的截面图。
具体实施方式
图1示出了本发明的示例性实施例。一种典型的沟槽MOS器件101包括栅极102和电极103及104。与为DC-DC转换设计的常规MOS器件不同，源极区106和本体区110没有被单一电极一起短路和连接。相反地，电极104短路本体区110和栅极区102，如图所示。
通过用电极104将栅极区102和本体区110短接在一起，并通过如下所解释的那样正确地偏置该器件，源极106还将用作双极器件的发射极，本体区110还将用作双极器件的基极，漏极105还将用作双极器件的集电极。实际上，通过正确地偏置该器件并使双极器件在MOS器件内完成，实现了一种可以提供高得多的电流驱动能力的混合器件。换个角度来看，为与单纯的MOS器件具有相同功耗而设计的混合结构将具有小得多的面积，结果减小了成本。
现在我们来解释该器件的操作，我们可以使用术语本体、栅极、漏极和源极来表示适当的区域，条件是当将该器件适当偏置时，这些区域是双极晶体管的前述区域的两倍。在操作中，将正电压施加到电极104，分别偏置本体区110和栅极区102。这在这些区域处产生正向偏压，使源极103用作发射极，且本体110用作双极器件的基极。集电极表示为105，该相同的区域用作双极器件的漏极。在适当的电压(基极电流)电平下，MOS器件的栅极上的电压超过阈值电压，使得增加的MOS电流流到双极部件。
该栅极偏压使台式侧壁上的硅反型而形成MOS沟道。电流从源极/发射区102通过基区/本体区110并沿沟槽侧壁112流动。当电流流动时，电流由空穴和电子二者形成，相对于常规单极器件提供了高得多的电流密度并降低了开态电阻。
注意到，邻近于Ndrift区的栅氧化物厚度114比邻近于PI区的栅氧化物厚度115更厚。该更厚的区域114允许器件101在更高的击穿电压下操作。例如，在高达200伏操作时，区域114约厚10,000，而区域115可能仅为380。可选地，如果器件在较低的电压(＜30V)下操作，仅需要一个约380-1000的厚度。单氧化物器件的厚度通常由电压处理、开态电阻和电容的折衷来确定。
注意到，虽然电极103和104并排示出，但它们实际上可以在三维中在纸面里面和外面交错。此外，在不降低功能的情况下，从晶片表面看，沟槽结构可以是条形、正方形、圆形、六边形或任何其他几何形状。
栅极可以在多晶硅或任何淀积金属中制造。可以利用所淀积的栅极的费米电势来调整MOS器件的阈值电压，而与本体(基极)的掺杂水平无关。然而注意到，为了给MOS栅极提供特定的阈值电压，优化PI区域内的掺杂会具有使双极器件的性能退化的效果。为了避免这种问题，并在器件优化中增加额外的自由度，可以期望由任何淀积金属或难熔材料(即，Al、Pt、Pd、TiW、包括CoSi2、TiSi2的硅化物，等等)形成栅电极，以便可以优化双极晶体管，而与MOS器件的沟道无关。如此，可以选择基极-本体区的体积浓度来优化基极传输和发射极注入的效率，同时使对MOS沟道的阈值电压和饱和特性的影响最小化。
双金属工艺流程对器件的构造是最好的，以制造基极-栅极和源极-发射极接触区的密集互连；虽然也可以使用单金属工艺流程。
上面描述了本发明的优选实施例，但各种改变和增加对本领域技术人员来说是明显的。

Claims (21)

1、一种混合MOS-双极器件，包括至少具有源极、栅极、漏极和本体区的沟槽MOS器件，该栅极和基极被短接在一起并且相对于漏极被正向偏置。
2、权利要求1的混合MOS-双极器件，其中所述栅极具有小于600的单一氧化物厚度。
3、权利要求1的混合MOS-双极器件，其中所述栅极具有形成栅和场氧化物区域的多个氧化物厚度。
4、权利要求2的混合MOS-双极器件，其具有正方形沟槽几何形状。
5、权利要求2的混合MOS-双极器件，其具有圆形几何形状。
6、一种完成具有源极、本体和栅极的混合MOS-双极器件的方法，包括使沟槽MOS器件的本体和栅极短接在一起并且将连接到该短路的本体和栅极的电极正向偏置。
7、权利要求6的方法，其中栅氧化物的厚度沿其长度变化。
8、权利要求7的方法，其中栅氧化物的厚度的变化为具有两个基本分立水平面的厚度。
9、权利要求8的方法，其中所述器件具有PI区和Ndrift区，且其中第一栅氧化物厚度邻近于所述PI区被形成和更厚的第二栅氧化物厚度邻近于所述Ndrift区被形成。
10、一种混合MOS-双极器件，其包括PI区、Ndrift区、本体、栅极、漏极和源极，所述器件被配置成将其基极和栅极短接在一起，所述器件具有邻近所述PI区的第一值的栅氧化物厚度和邻近所述Ndrift区的第二值的栅氧化物厚度。
11、权利要求10的混合MOS双极器件，其中所述栅极和所述本体被正向偏置。
12、一种制造混合MOS-双极器件的方法，包括掺杂PI区以使所述MOS器件的所述区域最优化，并制造栅电极以使所述混合MOS-双极器件的双极部件最优化。
13、权利要求12的方法，还包括制造沿栅氧化物长度改变的栅氧化物厚度。
14、权利要求13的方法，其中所述栅氧化物在邻近所述PI区的区域中的厚度比在邻近所述Ndrift区的区域中的厚度更大。
15、权利要求14的方法，其中使用双金属工艺流程构造所述器件。
16、一种混合双极-MOS器件，具有用作源极和发射极的第一区域、用作本体和基极的第二区域、和用作栅极和基极和第三区域，该栅极和基极被短接在一起并且被正向偏置。
17、权利要求16的混合双极-MOS器件，具有用作漏极和集电极的第四区域。
18、权利要求17的混合双极-MOS器件，具有大约200伏的击穿电压。
19、权利要求17的混合双极-MOS器件，具有大约380-600埃的单一栅氧化物厚度。
20、权利要求17的混合双极-MOS器件，具有多个栅氧化物厚度。
21、权利要求2的混合MOS-双极器件，具有条形几何形状。
CNA2004800283096A 2003-09-30 2004-09-27 混合双极－mos沟槽栅极半导体器件 Pending CN1860615A (zh)

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CN102138211B (zh) * 2008-08-29 2013-12-18 先进微装置公司 用于包括双沟道晶体管的sram单元的本体触点

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