CN1856875A - Semiconductor device, method of manufacturing same, identification label and information carrier - Google Patents
Semiconductor device, method of manufacturing same, identification label and information carrier Download PDFInfo
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- CN1856875A CN1856875A CNA2004800275808A CN200480027580A CN1856875A CN 1856875 A CN1856875 A CN 1856875A CN A2004800275808 A CNA2004800275808 A CN A2004800275808A CN 200480027580 A CN200480027580 A CN 200480027580A CN 1856875 A CN1856875 A CN 1856875A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The semiconductor device (100) comprises an integrated circuit (20) and a first and a second contact face (31,33). These are connected with vertical interconnects (32,34) to the integrated circuit (20). This integrated circuit (20) is present in a semiconductor layer of a substrate. This substrate is absent in a non-active area (B). This leads to the fact that on the side faces (101) of the device (100) neither conductive material nor parts of the semiconductor substrate are exposed. On lamination of the device between two metallized foils into an identification label, the risk of short-circuitry due to undesired contact at the side face (101) of the device (100), is prevented thereby.
Description
The present invention relates to a kind of have first with second relative semiconductor device, comprising:
Substrate, it comprises semiconductor layer and electric insulation layer, and is positioned on first of this device;
Integrated circuit is provided with a plurality of semiconductor elements, and these semiconductor elements are limited in the semiconductor layer or on the semiconductor layer, and utilize interconnection structure to interconnect according to desirable pattern;
Be positioned at first contact-making surface on first of this device, and
Be positioned at second second contact-making surface of going up and being connected to interconnection structure of this device.
The invention still further relates to the method for making this semiconductor device.
The invention still further relates to the identification label and the information carrier that comprise this semiconductor device.
Can from WO-A 02/075647, know this semiconductor device.Known device is the integrated circuit that is provided with conductive contact surfaces on its opposite face.This integrated circuit-, on the surface of described layer-of-substrate silicon, have electric insulation layer according to routine techniques-be limited in the layer-of-substrate silicon.This insulating barrier generally is a thermal oxide layer.The advantage that this structure has is to have simplified the assembling in the identification label: first and second can be exchanged.
The shortcoming of known device is not too to be suitable for being assembled in the metal tape.This metal tape is one of first of covering device and second not only, but also cover any side.For the semiconductor device in the substrate, this may cause leakage current and ghost effect, particularly under higher frequency.
Therefore first purpose of the present invention provides the semiconductor device of the described type of a kind of introductory song, and this semiconductor device is not too responsive to ghost effect during in being assembled in metal tape.
This purpose realizes by following means:
Have the electric insulation supporting layer, it covers integrated circuit on second, and horizontal expansion around integrated circuit in non-active area, passes this supporting layer and has perpendicular interconnection, so that second contact-making surface is connected with interconnection structure;
Laterally part is removed semiconductor layer, so that in non-active area, do not exist, and
First contact-making surface is connected to interconnection structure by perpendicular interconnection.
Integrated circuit in the device of the present invention is actually the island in the encapsulation, and except perpendicular interconnection, it is an electric insulation for bigger part at least.Because this island structure and perpendicular interconnection, the therefore risk that does not exist any interconnection on Semiconductor substrate or the side surface to contact with any metal forming.So can prevent to cause function reduction or even any non-controlled and undesired effect generation that produces fault in this way.
The non-active area of device is laterally to be positioned at active area zone on every side, defines integrated circuit in described active area.Non-active area and active area can be complementary, so that fill the whole surf zone of device.Yet, be not precluded between active area and the non-active area and have zone line.Non-active area then is the marginal zone.So far, realized during carrying out lamination, preventing the purpose of the present invention of any short circuit.
The advantage of device of the present invention is: the thickness that can reduce substrate under the situation of not damaging device stability.In fact, supporting layer replacement Semiconductor substrate plays support.Owing to can freely select supporting layer, thus this to allow device be flexible or or even full flexible as a whole.
Another advantage is: because attenuate, device can be complete or most of transparent.In view of possible safety function, this feature is favourable.
Another advantage that the semiconductor layer of substrate is limited on some island is that independent device can be separated from each other at an easy rate: needn't exist and want any ceramic material or the metal that must cut off.
In suitable embodiment, be arranged in non-active area to the perpendicular interconnection of first contact-making surface, first contact-making surface is limited in the conductive layer.First contact-making surface is arranged in separating layer, rather than as the high-doped zone on second of substrate, this has reduced the resistance from this contact-making surface to side circuit.And, also reduced the undesirable interactions risk has taken place between the perpendicular interconnection that passes substrate and the adjacent semiconductor element.
In a preferred embodiment, electric insulation layer is laterally continuous basically, so that be arranged in non-active area.Particularly, this insulating barrier passes entire device and extends to relative side from a side.This continuous existence not only helps the stability of device, and during handling the still etching stopping layer of effective barrier layer-particularly.Validity is very big, is can so use it during first and second processing.In addition, preferably as or the insulating barrier that comprises oxide allow to set up enough bonding with organic layer.
Can provide semiconductor device of the present invention with at least two kinds of technology.In first kind of technology, use single crystal semiconductor substrate, on its second, limit element, and thermal oxide layer is provided.When making the substrate attenuation, be not subjected to the influence of etching mode (wet method or dry method) by the active area of hard mask protection semiconductor element.As a result, this device is provided with mesa structure (mesa) on its first.
In second kind of technology, use substrate with buried oxide layer.The known example of this substrate is silicon-on-insulator (SOI) substrate.It is flexible to use the SOI substrate to allow resulting device to be not only, and is full flexible.This is particularly advantageous for identification label, wherein preferably makes the existence of integrated circuit keep concealed.In this case, electric insulation layer is positioned on second of substrate, and perpendicular interconnection extends through it.Replace the electric insulation layer of oxide or except that it, can have passivation layer, nitride for example, the nitride that particularly utilizes LPCVD to provide.This layer will prevent from removing impurity after the substrate, comprise water, be diffused into the device from environment.Because the basalis of this SOI substrate only means support, therefore it will be evident to one skilled in the art that to be removed so that desirable flexibility is provided.
In a preferred embodiment, interconnection structure is provided with first and second via pad, and they are arranged in non-active area, and has first and second perpendicular interconnections respectively on described pad.Owing to provide perpendicular interconnection in the active area outside of semiconductor element, therefore can prevent or on sizable degree, reduce at least the electric reciprocation of chemical contamination and parasitism.And, if perpendicular interconnection is configured in the outside of active area, then easier preventing because any breaking that pressure differential or thermal expansion difference cause, described active area is actually the multilayer laminated of a large amount of thin and flimsy layer.Particularly, compare with other patterns in the integrated circuit, second via pad has the size of vast scale.As the thickness of supporting layer with run through the result of the etching step (etching step) of this supporting layer, described second via pad for example can be taken advantage of 10 microns or bigger for about 10.
It is highly preferred that: via pad is positioned on the electric insulation layer as a substrate part.This has and is beneficial to stability.In another embodiment, via pad and perpendicular interconnection comprise ductile material, for example Al.Electric insulation layer preferably includes oxide skin(coating).
Supporting layer preferably includes organic material.It is photosensitive that this material can be selected.In addition, it can also have big thickness, for example in from 5 to 20 microns scope, so that required support is provided, but does not damage flexibility.It can also have low dielectric constant.This has limited the parasitic capacitance between first and second contact-making surfaces.Perhaps, dielectric constant can change and be increased to desirable value (increase to desire).The parasitic capacitance that produces can be used as tuning capacitor, and it is particularly suitable for making up with dipole antenna.
In another preferred embodiment, supporting layer also is positioned on first of device.So device is encapsulated in this supporting layer on its two sides.In view of flexural property, this has sizable advantage.The device proof is more responsive to compression stress comparison elastic stress.Compression stress may cause the micro-crack in semiconductor layer and/or the interconnection structure.By on first, providing support layer equally, compression stress can be discharged on this supporting layer.Very clear, the supporting layer on it has sufficient elasticity.
Device of the present invention can suitably be integrated in the identification label, and this identification label also comprises the antenna that is used for wireless transmission.As the subsequent product of the identification label that is used for logistics support or product safety, this identification label can be safety paper and the file that combines this paper, for example banknote, passport and other ticket.As known in the art, seem preferably the integrated circuit in the banknote to be attached to the safety line (security thread) that is arranged in banknote.Safety line can be as the dipole antenna with any required modification.In view of easy assembling and its flexibility, device of the present invention is very suitable for this purpose.In addition, the capacitor parasitics between first and second contact-making surfaces can be designed to the tuning capacitor that acts on desirable frequency.
Perhaps, device of the present invention can be integrated in other devices, comprises information carrier, for example DVD or CD, perhaps even smart card.
Coupling between device of the present invention and the antenna can be used as DC and is coupled and realizes, for example adopts anisotropy conductiving glue, but also can be capacitive, because contact-making surface forms electrode for capacitors with antenna.Advantageously, semiconductor device is provided with glue before assembling.Specially suitable glue is such glue: adhesion strength increases when heating.
Second purpose of the present invention provides a kind of method of making semiconductor device of the present invention in durable mode.This purpose is to realize by the method that may further comprise the steps:
Substrate with semiconductor layer and electric insulation layer is provided, is provided with the integrated circuit that is limited to a plurality of semiconductor elements in the active area, semiconductor element utilizes interconnection structure to interconnect each other according to desirable pattern, this interconnection structure comprises first and second via pad, and described via pad is arranged in the zone of substantial lateral ground in the active area outside;
On second, apply the supporting layer of electrical insulating material, and the contact window of corresponding second via pad is provided in supporting layer;
On second, apply electric conducting material, and second contact-making surface and second perpendicular interconnection between the described contact-making surface and second via pad are provided thus with desirable pattern;
Utilize removable attachment device that substrate is attached on the carrier on its second;
From first attenuate substrate, make laterally be arranged in the insulating barrier that active area some non-active areas outside and expose substrate on every side at least;
First contact-making surface is provided on first, and it is connected to first via pad by first perpendicular interconnection, and insulating barrier is passed in described first perpendicular interconnection extension at least; And
Remove the semiconductor device of acquisition like this from carrier.
This method according to the present invention obtains and the similar semiconductor device of semiconductor device known from EP-A 1256983, but it has on bottom surface and end face the obvious advantage that contacts is all arranged.
The particularly preferred SOI type substrate that is to use.In this case, insulating barrier is buried in the substrate.Substrate also comprises basalis and semiconductor layer, removes this basalis in the attenuate step, and limits semiconductor element thereon in the neutralization of the surface of this semiconductor layer.
Can be used as the part of integrated circuit or after reduction process finishes, provide first perpendicular interconnection.Preferably before handling,, provide this first perpendicular interconnection for example as the part of integrated circuit.This advantage that has is that neither one needs high-resolution in the step of said method.
This low resolution composition can carry out in assembly plant, this with in semiconductor wafer factories, use compare more cheap.If necessary, also can before being transferred to assembly plant, device provide patterned supporting layer.
Additional advantage is that a plurality of semiconductor device are provided in once-through operation, as known in the art.To remove device in order improving, preferably to change at the edge of wafer and remove supporting layer, and apply adhesive from carrier.
These and other aspects to method of the present invention, semiconductor device and identification label are further detailed with reference to the accompanying drawings, wherein:
Fig. 1 to 7 illustrates the profile of the several steps among first embodiment of this method;
Fig. 8 illustrates the constructed profile of the semiconductor device among first embodiment;
Fig. 9-14 illustrates the profile of the several steps among second embodiment of this method;
Figure 15 illustrates the constructed profile of the semiconductor device among second embodiment;
Figure 16 illustrates the details of Figure 15; And
Figure 17 illustrates semiconductor device and is integrated in constructed profile in the identification label.
Accompanying drawing does not draw in proportion and identical reference number is represented same or analogous parts.
Fig. 1 to 7 relates to first embodiment of the manufacture method of semiconductor device according to the invention.The device that obtains is presented among Fig. 8.
In first method of the present invention, use the substrate 10 of wherein having buried insulating barrier 11.Buried layer 11 is oxide skin(coating) normally, but preferably includes the chemoprotectant nitride layer that is used to improve integrated circuit 20, and the semiconductor layer that described integrated circuit 20 is arranged on common epitaxially grown semi-conducting material neutralizes on it.On the opposite face of buried layer 11, there is basalis.The basalis in the substrate 10 and the semi-conducting material of semiconductor layer are silicon in this case.Integrated circuit 20 is included in a plurality of semiconductor element (not shown) among the active area A.These elements utilize interconnection structure (not specifically illustrating) to interconnect each other according to desirable pattern.This structure comprises first via pad 21 and second via pad 22, and described pad 21,22 is arranged in the area B that substantial lateral ground is positioned at active area A outside.Via pad preferably is arranged in the aluminium lamination in view of its ductility.Yet, perhaps can adopt Cu, Ni, Ag or conductive paste.
Fig. 2 illustrates supporting layer 12 with the electrical insulating material result after being applied on second 2.In this case, using common thickness is the polyimides of 10 to 20 μ m.Before for example applying polyimides, cleaned the surface, and provided initial bed (primer layer) in order to improve cementability by spin coating.After applying polyimides, at first be heated 125 ℃, be heated to 200 ℃ afterwards.Apply photoresist then, be exposed under the suitable irradiation source and development.Developing comprises the structure of polyimide layer, so that produce the contact window 13 that exposes second via pad 22.Equally at substrate, be generally 6 " wafer, fringe region C remove the supporting layer 12 of polyimides.Remove 12 pairs of output of supporting layer among the edge region C and have useful effect.
Result after Fig. 3 illustrates on second 2 that conductive layer is arranged on substrate 10.Apply conductive layer with the pattern that comprises second contact-making surface 31 and second perpendicular interconnection 32 between this contact-making surface 31 and second via pad 22.Preferably, conductive layer comprises Al.This with use Al to be used for second via pad 22 to combine, good electrical connection is provided and has needed flexibility with any bending of bearing paper tinsel and any power during device is stacked to label.
Fig. 4 illustrates and utilizes removable attachment device 41 that substrate 10 is attached to carrier 40 substrate 10 afterwards.This device 41 is adhesive phase in this case, and it is releasable when utilizing the UV-radioactive ray to shine.To this, carrier 40 is transparent, and is glassy layer in this example.Preferably in supporting layer and second contact-making surface 31 and interconnection 32, apply oxide skin(coating).Its advantage is to have improved output once more.If necessary, this layer can be provided with according to desirable pattern.Afterwards, give marginal zone C primer (primer).Consequently adhesive 41 among the C of marginal zone and the good bonding between the supporting layer 12, and cementability is very weak basically in other zones.
Fig. 5 illustrates the result after first attenuate substrate 10.Usually by grinding and utilizing KOH to continue etching and realize this attenuate.Attenuate is proceeded, till the basalis of removing substrate 10.Buried layer 11 is here as etching stopping layer.
Fig. 6 illustrates and buried layer is carried out composition so that produce the composition result afterwards of contact window 14.
Fig. 7 illustrates and applies another metal level result afterwards, produces first perpendicular interconnection 34 and first contact-making surface 33 by described another metal level.Described another metal level for example comprises Al or Cu.Under the situation of Cu, the barrier layer can be applied so that prevent any pollution of semiconductor layer.After removing carrier 40, can separate independent device 100.
Fig. 8 illustrates the device of the present invention 100 of first embodiment.Device 100 comprises first contact-making surface 33 and second contact-making surface 31, and integrated circuit 20.This integrated circuit is provided with the perpendicular interconnection 32,34 of the connection that is used to be established to contact-making surface 31,33.Device 100 is provided with active area A and non-active area B.It is supported by supporting layer 12.The semiconductor layer of substrate 10 only is arranged in active area A.In this case, having only the left-hand component of substrate is epitaxially grown semiconductor layer and electric insulation layer 11 in the active area.Owing in non-active area B, there is not any part of semiconductor layer and basalis, prevent from therefore that side 101 by device 100 from forming anyly undesirablely to electrically contact.Here supporting layer 12 has the typical thickness of about 5-15 μ m, is preferably about 10 μ m, and contact-making surface 31,33 has the thickness of about 0.2-1.5 μ m, is preferably about 1.0 μ m.
Fig. 9 to 14 illustrates second embodiment of method of the present invention.This method comprises a large amount of steps identical with first method.Yet main difference is substrate 10.In this example, it is without any the monocrystalline of buried oxide layer or the substrate of polysilicon.Oxide skin(coating) 11 is positioned at second gate oxide level that goes up and be used as the semiconductor element of integrated circuit 20 simultaneously of substrate 10.In known manner for example by injecting the dopant of selected materials with desired concn and semiconductor element being limited on the surface of substrate 10.And injection is to pass the part of substrate 10 to first 1 trap that extends.At the top of this trap, oxide skin(coating) 11 has been carried out composition, and formed electrical connection.First perpendicular interconnection 34 that this has just constituted to first contact-making surface provides this first contact-making surface in the subsequent stage of technology.Except interconnecting 34, also limit first via pad 21 and second via pad 22.These via pad 21,22 are positioned at the outside of active area A, needn't still may be positioned partially among the non-active area B.
Figure 10 illustrate with desirable mode apply, curing and composition flexible support layers 13 be so that remove it and produce result after the contact window 13 of second via pad 22 from marginal zone C.
Figure 11 illustrates pattern with hope and electric conducting material is applied on second of supporting layer 12 tops, limits second contact-making surface 31 and the result after the perpendicular interconnection 32 of second contact pad 22 thus.
Figure 12 illustrates and utilizes adhesive 41 that this structure is attached to carrier 40 result afterwards.
Figure 13 illustrates from first 1 attenuate substrate 10 and has applied result after the etching mask 33.This etching mask is made by electric conducting material, and subsequently will be as first contact-making surface.Here, be formed into the contact of first contact pad 21 by the trap that runs through substrate 10, described trap is the part of perpendicular interconnection 34.This is presented among Figure 16 in further detail, and Figure 16 illustrates the element of substrate 10, integrated circuit 20 and by metal trace 34A with run through the formed perpendicular interconnection 34 of trap 34B of substrate 10.
Figure 14 illustrates the result after the first facet etch substrate 10 also produces mesa structure 50 by this way.Mesa structure 50 also limits non-active area B, and this non-active area B is positioned at the outside of mesa structure, and does not wherein have Semiconductor substrate 10.Observe the outside that through hole 34 can be positioned at mesa structure 50.In this case, form through hole 34, because after forming mesa structure, conductive layer is arranged on first 1 of substrate according to desirable pattern.
Figure 15 illustrates last resulting semiconductor device 100, and it has active area A and non-active area B.It should be noted in this case, between non-active area B and active area A, also have a zone.Device 100 comprises first and second contact-making surfaces 31,33 and the perpendicular interconnection 32,34 that is used for face 31,33 is connected to integrated circuit 20.
Figure 17 illustrates semiconductor device 100 of the present invention is integrated into method in the identification label 200.Make label 200 by stacked first paper tinsel 211 and second paper tinsel 212.Described paper tinsel is arranged on the cylinder 300, and by wheel 310 structure lamination process.Paper tinsel 211,212 is provided with a plurality of conductive patterns 201,202 separately, and described conductive pattern can be used as antenna, for example dipole antenna.In this method, semiconductor device 100 is arranged between the described paper tinsel.Adhesive can be positioned on the semiconductor device 100 or paper tinsel 201,202 on so that improve cementability.Semiconductor device 100 is arranged on the described paper tinsel and does not have specific orientation.Owing in non-active area B, do not have Semiconductor substrate 10, therefore the risk that does not exist first contact-making surface and second contact-making surface of one of conductive pattern 201,202 and device all to electrically contact is perhaps owing to exist the risk of sizable parasitic capacitance by the interaction of Semiconductor substrate.Pattern in the paper tinsel 201,202 can also be designed to safety line.
Another advantage of device of the present invention is the influence that its active area of protection does not stress during being stacked to label.Carrying out this when stacked, apply maximum power in metallic region, this metallic region is a perpendicular interconnection.Yet these all are positioned at the outside of active area A, and any power all will further be directed to supporting layer.Because this supporting layer has Free Surface on the side of device, so it can discharge these power.And second perpendicular interconnection of V-arrangement be it seems the negative effect that can reduce the pressure during stacked.
In brief, semiconductor device 100 of the present invention comprises the integrated circuit 20 and first and second contact-making surfaces 31,33.Described first and second contact-making surfaces 31,33 utilize perpendicular interconnection 32,34 to be connected to integrated circuit 20.This integrated circuit 20 is arranged in the semiconductor layer of substrate.This substrate is not arranged in non-active area B.This causes such fact: neither expose the part that electric conducting material does not expose Semiconductor substrate yet on the side 101 of device 100.Device being stacked between two metallized paper tinsels when forming identification label, prevent thus owing to the undesirable contact on the side 101 of device 100 produces short risk.
Claims (12)
1, a kind of have first with second relative semiconductor device, comprising:
Substrate, it comprises semiconductor layer and electric insulation layer, and is positioned on described first of device;
Integrated circuit is provided with a plurality of semiconductor elements, and described semiconductor element is limited in the described semiconductor layer and/or on it, and utilizes interconnection structure to interconnect according to desirable pattern;
Be positioned at first contact-making surface on described first of described device;
Be positioned at described second second contact-making surface of going up and being connected to described interconnection structure of described device;
Wherein:
Have the electric insulation supporting layer, it covers described integrated circuit at described second, and laterally extends around described integrated circuit in non-active area, passes this supporting layer and has perpendicular interconnection, thereby described second contact-making surface is connected with described interconnection structure;
Laterally part is removed the described semiconductor layer of described substrate, so that do not exist in described non-active area; And
Described first contact-making surface is connected to described interconnection structure by perpendicular interconnection.
2, semiconductor device according to claim 1 is characterized in that being arranged in described non-active area to the described perpendicular interconnection of described first contact-making surface, and described first contact-making surface is limited in the conductive layer.
3, semiconductor device according to claim 1 and 2 is characterized in that described electric insulation layer is continuous in the horizontal basically, so that be arranged in described non-active area.
4, semiconductor device according to claim 1 is characterized in that described interconnection structure is provided with first and second via pad, and it is arranged in described non-active area, and has first and second perpendicular interconnections on described pad respectively.
5, semiconductor device according to claim 4 is characterized in that described via pad is positioned on the described electric insulation layer as the part of described substrate.
6,, it is characterized in that described second via pad and described second perpendicular interconnection comprise ductile material according to claim 4 or 5 described semiconductor device.
7, semiconductor device according to claim 1 is characterized in that described supporting layer comprises organic material.
8, a kind of identification label comprises according to any one described semiconductor device in the claim 1 to 7 and the antenna that is used for wireless transmission.
9, a kind of information carrier comprises according to any one described semiconductor device in the claim 1 to 7.
10, a kind of manufacture method of semiconductor device may further comprise the steps:
Substrate with semiconductor layer and electric insulation layer is provided, is provided with the integrated circuit that is limited to a plurality of semiconductor elements in the active area, described semiconductor element utilizes interconnection structure to interconnect according to desirable figure, this interconnection structure comprises first and second via pad, and described via pad is arranged in the zone that substantial lateral ground is positioned at described active area outside;
On described second, apply the supporting layer of electrical insulating material, and the contact window corresponding to described second via pad is provided in described supporting layer;
On described second, apply electric conducting material, second perpendicular interconnection between second contact-making surface and described contact-making surface and second via pad is provided thus with desirable pattern;
Utilize removable attachment device that described substrate is attached on the carrier on its second;
From described first described substrate of attenuate, thereby laterally be arranged in the described insulating barrier that described active area some non-active areas outside and expose described substrate on every side at least;
Provide first contact-making surface on described first, this first contact-making surface is connected to described first via pad by first perpendicular interconnection, and described insulating barrier is passed in described first perpendicular interconnection extension at least; And
Remove the semiconductor device that so obtains from described carrier.
11, method according to claim 10, wherein oxide skin(coating) is buried in the inside of described Semiconductor substrate, this substrate also comprises basalis and active layer, removes this basalis in the attenuate step, and limits described semiconductor element on the surface of this active layer.
12, method according to claim 10, wherein described first perpendicular interconnection is set to the part of described integrated circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP03103525 | 2003-09-24 | ||
| EP03103525.6 | 2003-09-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1856875A true CN1856875A (en) | 2006-11-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004800275808A Pending CN1856875A (en) | 2003-09-24 | 2004-09-02 | Semiconductor device, method of manufacturing same, identification label and information carrier |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1668694A1 (en) |
| JP (1) | JP2007507101A (en) |
| KR (1) | KR20060098432A (en) |
| CN (1) | CN1856875A (en) |
| WO (1) | WO2005029578A1 (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008502151A (en) | 2004-06-04 | 2008-01-24 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Method and device for manufacturing and assembling printable semiconductor elements |
| US7521292B2 (en) | 2004-06-04 | 2009-04-21 | The Board Of Trustees Of The University Of Illinois | Stretchable form of single crystal silicon for high performance electronics on rubber substrates |
| US8217381B2 (en) | 2004-06-04 | 2012-07-10 | The Board Of Trustees Of The University Of Illinois | Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics |
| JP2008091639A (en) | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | Electronic equipment, and manufacturing method thereof |
| JP2008091638A (en) | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | Electronic equipment, and manufacturing method thereof |
| JP4956128B2 (en) | 2006-10-02 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | Manufacturing method of electronic device |
| CN105826345B (en) | 2007-01-17 | 2018-07-31 | 伊利诺伊大学评议会 | Pass through the optical system of the assembly based on printing |
| EP2349440B1 (en) | 2008-10-07 | 2019-08-21 | Mc10, Inc. | Catheter balloon having stretchable integrated circuitry and sensor array |
| US8097926B2 (en) | 2008-10-07 | 2012-01-17 | Mc10, Inc. | Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy |
| US8389862B2 (en) | 2008-10-07 | 2013-03-05 | Mc10, Inc. | Extremely stretchable electronics |
| US8372726B2 (en) | 2008-10-07 | 2013-02-12 | Mc10, Inc. | Methods and applications of non-planar imaging arrays |
| US8886334B2 (en) | 2008-10-07 | 2014-11-11 | Mc10, Inc. | Systems, methods, and devices using stretchable or flexible electronics for medical applications |
| EP2430652B1 (en) | 2009-05-12 | 2019-11-20 | The Board of Trustees of the University of Illionis | Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays |
| US9723122B2 (en) | 2009-10-01 | 2017-08-01 | Mc10, Inc. | Protective cases with integrated electronics |
| US10441185B2 (en) | 2009-12-16 | 2019-10-15 | The Board Of Trustees Of The University Of Illinois | Flexible and stretchable electronic systems for epidermal electronics |
| US9936574B2 (en) | 2009-12-16 | 2018-04-03 | The Board Of Trustees Of The University Of Illinois | Waterproof stretchable optoelectronics |
| US10918298B2 (en) | 2009-12-16 | 2021-02-16 | The Board Of Trustees Of The University Of Illinois | High-speed, high-resolution electrophysiology in-vivo using conformal electronics |
| EP2974673B1 (en) | 2010-03-17 | 2017-03-22 | The Board of Trustees of the University of Illionis | Implantable biomedical devices on bioresorbable substrates |
| US9442285B2 (en) | 2011-01-14 | 2016-09-13 | The Board Of Trustees Of The University Of Illinois | Optical component array having adjustable curvature |
| WO2012158709A1 (en) | 2011-05-16 | 2012-11-22 | The Board Of Trustees Of The University Of Illinois | Thermally managed led arrays assembled by printing |
| US9159635B2 (en) | 2011-05-27 | 2015-10-13 | Mc10, Inc. | Flexible electronic structure |
| EP2713863B1 (en) | 2011-06-03 | 2020-01-15 | The Board of Trustees of the University of Illionis | Conformable actively multiplexed high-density surface electrode array for brain interfacing |
| US9691873B2 (en) | 2011-12-01 | 2017-06-27 | The Board Of Trustees Of The University Of Illinois | Transient devices designed to undergo programmable transformations |
| US9554484B2 (en) | 2012-03-30 | 2017-01-24 | The Board Of Trustees Of The University Of Illinois | Appendage mountable electronic devices conformable to surfaces |
| US9171794B2 (en) | 2012-10-09 | 2015-10-27 | Mc10, Inc. | Embedding thin chips in polymer |
| EP3304130B1 (en) | 2015-06-01 | 2021-10-06 | The Board of Trustees of the University of Illinois | Alternative approach to uv sensing |
| US10677647B2 (en) | 2015-06-01 | 2020-06-09 | The Board Of Trustees Of The University Of Illinois | Miniaturized electronic systems with wireless power and near-field communication capabilities |
| US10925543B2 (en) | 2015-11-11 | 2021-02-23 | The Board Of Trustees Of The University Of Illinois | Bioresorbable silicon electronics for transient implants |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5256562A (en) * | 1990-12-31 | 1993-10-26 | Kopin Corporation | Method for manufacturing a semiconductor device using a circuit transfer film |
| US5689136A (en) * | 1993-08-04 | 1997-11-18 | Hitachi, Ltd. | Semiconductor device and fabrication method |
| JP3462166B2 (en) * | 2000-09-08 | 2003-11-05 | 富士通カンタムデバイス株式会社 | Compound semiconductor device |
-
2004
- 2004-09-02 CN CNA2004800275808A patent/CN1856875A/en active Pending
- 2004-09-02 KR KR1020067005866A patent/KR20060098432A/en not_active Application Discontinuation
- 2004-09-02 WO PCT/IB2004/051676 patent/WO2005029578A1/en not_active Application Discontinuation
- 2004-09-02 JP JP2006527520A patent/JP2007507101A/en not_active Withdrawn
- 2004-09-02 EP EP04769931A patent/EP1668694A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP1668694A1 (en) | 2006-06-14 |
| KR20060098432A (en) | 2006-09-18 |
| JP2007507101A (en) | 2007-03-22 |
| WO2005029578A1 (en) | 2005-03-31 |
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