CN1845234A - Driving circuit for liquid crystal display device, liquid crystal display device, method of driving liquid crystal display device, and electronic apparatus - Google Patents

Driving circuit for liquid crystal display device, liquid crystal display device, method of driving liquid crystal display device, and electronic apparatus Download PDF

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CN1845234A
CN1845234A CN 200610072766 CN200610072766A CN1845234A CN 1845234 A CN1845234 A CN 1845234A CN 200610072766 CN200610072766 CN 200610072766 CN 200610072766 A CN200610072766 A CN 200610072766A CN 1845234 A CN1845234 A CN 1845234A
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mentioned
current potential
liquid crystal
potential
sweep trace
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CN100481203C (en
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藤田伸
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Japan Display West Inc
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Sanyo Epson Imaging Devices Corp
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Abstract

A driving circuit includes a scanning-line driving circuit applying an on potential to sequentially drive scanning-lines, a data-line driving circuit that, when the on potential is applied to each scanning-line, turns each data-line potential to a potential difference corresponding to a density based on a counter electrode potential and a potential corresponding to the same writing polarity among the scanning-lines, and a storage capacitor driving circuit which, when the on potential is applied to the scanning-lines and the data-line potential corresponds to positive polarity writing, shifts the other storage capacitor electrode potential in each storage capacitor to a high level after an off potential is applied to the scanning-lines, and, when the on potential is applied to the scanning-lines and the data-line potential corresponds to negative polarity writing, shifts the other storage capacitor electrode potential to a low level after the off potential is applied to the scanning-lines.

Description

Liquid crystal indicator, its driving circuit, driving method and electronic equipment
Technical field
The present invention relates to seek LCD drive circuits, liquid crystal indicator, driving method and the electronic equipment of low-power consumption.
Background technology
In recent years, liquid crystal indicator is the display device of cathode ray tube (CRT) instead, is widely used in the electronic equipment of various messaging devices, wall hanging TV set etc.Such liquid crystal indicator can be divided into all kinds according to type of drive etc., but is following such structure by the active array type LCD that on-off element drives pixel.Promptly, active array type LCD is made of device substrate, subtend substrate and liquid crystal, the on-off element be rectangular pixel electrodes arranged, be connected with this pixel electrode etc. is set on this device substrate, form the counter electrode of facing with pixel electrode on this subtend substrate, this liquid crystal is held between these two substrates.
In such structure, if sweep trace is the conducting current potential, then the on-off element that is connected with this sweep trace is in conducting state.When this conducting state, if by data line,, add and gray scale (concentration) corresponding voltage signal pixel electrode, holding liquid crystal and in the liquid crystal capacitance that constitutes between this pixel electrode and counter electrode then, storage and the corresponding electric charge of this voltage signal.In addition, after charge storage, be stopping potential even make sweep trace, on-off element is under the situation of cut-off state, still the storage that keeps the electric charge of this liquid crystal capacitance according to the capacitive character of liquid crystal capacitance itself, with itself and the memory capacitance of establishing etc.Like this, if drive each on-off element, corresponding to gray scale, and control stored charge amount, because the variation of the state of orientation of liquid crystal, so for each pixel, concentration change can be carried out gray scale and be shown.
But in liquid crystal indicator, according to factors such as the characteristic of the electronic equipment that is adopted, speciality, purposes, people require low-power consumption consumingly.On the other hand, because in the liquid crystal indicator, data line is according to higher frequency drives, and in addition, the driving of liquid crystal capacitance requires 10 volts or above higher voltage amplitude usually, so general logarithm adds the higher voltage amplitude according to line.
Here, provide and reduce the outer voltage amplitude that is added on the voltage signal on the data line, seek low-power consumption liquid crystal indicator (such as, with reference to patent documentation 1).
Patent documentation 1:JP spy opens the 2002-196358 communique
But, in the scheme of patent documentation 1, though the voltage amplitude reduction,, the frequency of driving data lines does not change, and people require further to reduce power consumption.
Summary of the invention
The present invention be directed to above-mentioned situation and propose, the object of the present invention is to provide and seek LCD drive circuits, liquid crystal indicator, driving method and the electronic equipment that power consumption further reduces.
Driving LCD drive circuits of the present invention relates to the following LCD drive circuits of driving, this liquid crystal indicator comprises scanline groups, data line, the liquid crystal capacitance that is formed by adjacent multi-strip scanning line, this liquid crystal capacitance is provided with corresponding to the infall of each bar in the above-mentioned multi-strip scanning line and above-mentioned data line, and by counter electrode and pixel electrode, holding liquid crystal; On-off element, this on-off element when above-mentioned sweep trace is the conducting current potential, are realized conducting between above-mentioned data line and pixel electrode, on the other hand, when this sweep trace is stopping potential, realize ending; Memory capacitance, this memory capacitance comprises a side and the storage capacitor electrode of pixel electrodes connection and the storage capacitor electrode of the opposing party and the relative configuration of above-mentioned side's storage capacitor electrode, it is characterized in that comprising:, drive the scan line drive circuit of each bar sweep trace of above-mentioned multi-strip scanning line successively according to the conducting current potential; Data line drive circuit, in this data line drive circuit, by above-mentioned scan line drive circuit, when the respective scan line of above-mentioned multi-strip scanning line is the conducting current potential, make the current potential of the current potential of above-mentioned data line for above-mentioned relatively counter electrode, corresponding to the potential difference (PD) of concentration, and for being the identical corresponding current potential of polarity that writes with the sweep trace that belongs to above-mentioned scanline groups; The memory capacitance driving circuit, wherein, if when above-mentioned sweep trace is the conducting current potential, the current potential of above-mentioned sweep trace writes corresponding with positive polarity, then after above-mentioned sweep trace is displaced to stopping potential, with the potential shift of above-mentioned the opposing party's storage capacitor electrode of above-mentioned memory capacitance to high-order side, on the other hand, if the current potential of the above-mentioned data line of above-mentioned conducting current potential writes corresponding with negative polarity, then after above-mentioned sweep trace is displaced to stopping potential, with the potential shift of above-mentioned the opposing party's storage capacitor electrode of above-mentioned memory capacitance to the low level side.
According to this scheme, shift amount corresponding to the opposing party's storage capacitor electrode current potential, improve (or reduction) from data line, supply with the wherein current potential of side's storage capacitor electrode in liquid crystal capacitance and the storage capacitor electrode, according to low-voltage, carry out the driving of data line, and data line drive circuit is corresponding to by conducting the sweep trace that current potential drives, when current potential is supplied with data line, make the scanline groups that forms by adjacent multi-strip scanning line to write polarity identical.Thus, for adjacent multi-strip scanning line, the polarity of the current potential of driving data lines is nonreversible.So, can seek the reduction of power consumption according to the low voltage drive data line, reduce the frequency of inversion driving data line, seek the further reduction of power consumption.
Here, best, above-mentioned memory capacitance driving circuit carries out and the displacement that belongs to the corresponding above-mentioned current potential of multi-strip scanning line of above-mentioned scanline groups simultaneously in above-mentioned driving circuit.
According to such scheme, the timing of the displacement of the current potential of the opposing party's storage capacitor electrode of memory capacitance driving circuit is simultaneously for the sweep trace that belongs to scanline groups.Not only the displacement of current potential write polarity, and the timing of displacement all is common, thus, corresponding to the multi-strip scanning line that belongs to a scanline groups, shared 1 memory capacitance driving circuit simultaneously.So, can seek driving circuit overall dimensions reduce, realize integrated etc.
Here, best, the adjacent sweep trace that belongs to above-mentioned scanline groups is 2, and above-mentioned data line drive circuit carries out inversion driving by per 2 horizontal scan period to the polarity that writes of above-mentioned data line.
According to this scheme, and by per 1 horizontal scan period, compare when carrying out inversion driving, the frequency that data line is carried out inversion driving is reduced about half, can seek the further reduction of power consumption.
Here, best, in above-mentioned driving circuit, above-mentioned data line drive circuit make above-mentioned data line for the opposite corresponding current potential of polarity that writes in adjacent above-mentioned sweep trace.
In liquid crystal indicator,, cause the clutter (noise) that on picture, shows striated because the unevenness of making etc. in the current potential of pixel electrode, produce the difference of every data line.According to above-mentioned invention and since current potential write polarity for adjacent scanline groups, reverse, so the polarity of the current potential of pixel electrode for each scanline groups, is opposite.So, can be by adjacent scanline groups, offset and reduce the change in display brightness that the difference of current potential causes.
In addition, liquid crystal indicator of the present invention can according to the low voltage drive data line, be sought the reduction of power consumption by above-mentioned driving circuit is set.In addition, electronic equipment of the present invention can be sought the reduction of power consumption by above-mentioned liquid crystal indicator is set.
In addition, the driving method of liquid crystal indicator of the present invention relates to the driving method that drives following liquid crystal indicator, wherein, this liquid crystal indicator comprises scanline groups, data line, the liquid crystal capacitance that is formed by adjacent multi-strip scanning line, this liquid crystal capacitance is provided with corresponding to the infall of each bar sweep trace in the above-mentioned multi-strip scanning line and above-mentioned data line, and by counter electrode and pixel electrode, holding liquid crystal; On-off element, this on-off element when above-mentioned sweep trace is the conducting current potential, are realized conducting between above-mentioned data line and pixel electrode, on the other hand, when this sweep trace is stopping potential, realize ending; Memory capacitance, this memory capacitance comprises a side and the storage capacitor electrode of pixel electrodes connection and the storage capacitor electrode of the opposing party and the relative configuration of above-mentioned side's storage capacitor electrode, it is characterized in that making each the bar sweep trace in the above-mentioned multi-strip scanning line successively is the conducting current potential when driving this liquid crystal indicator; When each the bar sweep trace in above-mentioned multi-strip scanning line is the conducting current potential, the current potential of above-mentioned data line is the current potential of above-mentioned relatively counter electrode, potential difference (PD) corresponding to concentration, and with the sweep trace that belongs to above-mentioned scanline groups is the identical corresponding current potential of polarity that writes, if when above-mentioned sweep trace is the conducting current potential, the current potential of above-mentioned data line writes corresponding with positive pole, after above-mentioned sweep trace is displaced to stopping potential, make the potential shift of the opposing party's storage capacitor electrode of above-mentioned memory capacitance arrive high-order side, on the other hand, if when above-mentioned sweep trace is the conducting current potential, the current potential of above-mentioned data line writes corresponding with negative polarity, then after above-mentioned sweep trace was displaced to stopping potential, the potential shift of the opposing party's storage capacitor electrode of above-mentioned memory capacitance was to the low level side.
Description of drawings:
Fig. 1 is the skeleton view of the surface structure of the liquid crystal indicator of expression the 1st embodiment of the present invention;
Fig. 2 is the cut-open view along the A-A ' line among Fig. 1;
Fig. 3 is the block diagram of the electric structure of the above-mentioned liquid crystal indicator of expression;
Fig. 4 is the block scheme of the electric structure of the electric capacity line drive circuit of the above-mentioned liquid crystal indicator of expression;
Fig. 5 is the sequential chart of work that is used to illustrate the Y side of above-mentioned liquid crystal indicator;
Fig. 6 is the sequential chart of work that is used to illustrate the X side of above-mentioned liquid crystal indicator;
Fig. 7 (a) and (b), (c) are respectively the figure of the work that writes of the pixel that is used for illustrating above-mentioned liquid crystal indicator;
Fig. 8 (a) is the figure of the voltage waveform of expression sweep signal of above-mentioned liquid crystal indicator and electric capacity swinging signal, and Fig. 8 (b) is added on the figure of the voltage waveform on the pixel electrode outward for being illustrated in the above-mentioned liquid crystal indicator;
Fig. 9 is the block scheme of the circuit structure of the liquid crystal indicator of expression the 2nd embodiment of the present invention;
Figure 10 is the block scheme of the circuit structure of the liquid crystal indicator of expression the 3rd embodiment of the present invention;
Figure 11 is the sequential chart of work that is used to illustrate the Y side of above-mentioned liquid crystal indicator;
Figure 12 is the circuit diagram of the distortion example of the electric capacity line drive circuit of the above-mentioned liquid crystal indicator of expression;
Figure 13 is the skeleton view of the structure of the portable telephone of an example of the electronic equipment of the liquid crystal indicator of expression employing embodiment.
The explanation of label:
Label 100 expression liquid crystal indicators;
Label 105 expression liquid crystal;
Label 108 expression counter electrodes;
Label 112 expression sweep traces;
Label 113 expression electric capacity lines;
Label 114 expression data lines;
Label 115a, 115b represent scanline groups;
Symbol 116 expression TFF (on-off element);
Label 118 remarked pixel electrodes;
Label 119 expression memory capacitance;
Label 130 expression shift registers (scan line drive circuit);
Label 150 expression shift registers;
Label 152,156 expression sampling switches;
Label 154,158 expression latch circuits;
Label 160 expression D/A converters (, forming data line drive circuit) by 150,154,156,158,160;
Label 171 expression electric capacity line drive circuits (memory capacitance driving circuit);
Label 3000 expression portable telephones.
With reference to the accompanying drawings, embodiments of the invention are described.
(1: the 1 embodiment)
At first, the liquid crystal indicator to the 1st embodiment of the present invention is described.Fig. 1 is the skeleton view of the surface structure of this liquid crystal indicator of expression, and Fig. 2 is the cut-open view along the A-A ' line among Fig. 1.Shown in these figure, liquid crystal indicator 100 is a following structures, wherein, be formed with various elements, pixel electrode 118 etc. device substrate 101, be formed with the seal 104 of subtend substrate 102 by having distance piece 103 of counter electrode 108 etc., keep certain clearance, fit according to the mode that electrode forming surface is relative, and in this gap, be sealed with such as, the liquid crystal 105 of TN (TwitedNematic reverses) pattern, vertical alignment mode, lateral electric field mode etc.
In addition, when present embodiment, device substrate 101 adopts glass, semiconductor, quartz etc., but also can adopt opaque substrate.But when device substrate 101 adopted nontransparent substrate, must be used as was not the reflection-type of transmission-type.In addition, seal 104 forms along the periphery of subtend substrate 102, but for encapsulated liquid crystals 105, a part of opening.Thus, after the sealing of liquid crystal 105, this opening portion seals by seal 106.
In addition, on the opposite face of device substrate 101, be positioned on the regional 105a on one side in the outside of seal 104, be formed for the circuit (particular content will be described later) of driving data lines.In addition, form following structures, wherein,, form a plurality of mounting terminal 107,, import various signals from external circuit at its outer peripheral portion on one side.In addition, the circuit that is used for driving data lines is not limited to the outside of seal 104, also can be arranged at the zone that is formed with seal 104.
Also have, form following structures, in this structure, on the regional 103a that is positioned at two limits adjacent with this limit, be formed for the circuit (particular content will be explained hereinafter) of driven sweep line, electric capacity line etc. respectively,, drive from the both sides of row (X) direction.On a remaining limit, in the circuit that is formed at 2 regional 130a, shared wiring (diagram is omitted) etc. is set.In addition, also form following structures, wherein, postpone not throw into question if follow the direction signal supplied, the circuit of then exporting these signals only is formed at 1 regional 130a of a side.The circuit that is used for driven sweep line, electric capacity line etc. also can be arranged at the outside of seal 104, be formed with the zone of seal 104.
On the other hand, the counter electrode 108 that is arranged on the subtend substrate 102 is following structures, wherein, it is by being arranged in 4 bights with the fitting part of device substrate 101, the conduction element of the silver paste at least 1 position etc., mounting terminal 107 conductings with being formed on the device substrate 101 remain on the common potential LCcom as the subtend current potential of pixel electrode 118.In addition, on subtend substrate 102, particularly unshowned in the drawings, the zone relative with pixel electrode 118 as required, is provided with dyed layer (color filter).But,, when being used for the purposes of coloured light modulation, needn't on subtend substrate 102, form dyed layer as projector described later.In addition, in order no matter whether dyed layer to be set, all prevent the reduction of contrast of the leakage of light, the part outside the zone relative with pixel electrode 118 is provided with photomask (diagram is omitted).
Have again, each opposite face at pixel substrate 101 and subtend substrate 102, alignment films is set, this alignment films is according at the TN pattern, the long axis direction of the molecule of liquid crystal 105 is between two substrates, and about 90 modes of spending of reversing are continuously carried out milled processed and formed, on the other hand, in each rear side, be provided with respectively along the polarizer of the direction setting absorption axes of direction of orientation.Thus, form following structures, wherein, if the actual effective value of voltage that is applied on liquid crystal capacitance (between pixel electrode 118 and counter electrode 108, holding liquid crystal 105 and the electric capacity that constitutes) is zero, transmissivity maximum then, on the other hand, follow the increase of the actual effective value of voltage, transmissivity reduces at leisure, then, transmissivity reaches minimum.That is, in the present embodiment, form the structure of normal white mode.
In addition, for alignment films, polarizer etc., because it does not have direct relation with the application, so it illustrates omission.In addition, in Fig. 2, counter electrode 108, pixel electrode 118, mounting terminal 107 etc. have thickness, and still, it is the measure easily that is used to represent the position relation, in fact, and the thinner thickness of substrate and arrive beyond all recognition degree.
(1-1: electric structure)
Electric structure to the liquid crystal indicator 100 of present embodiment is described below.Fig. 3 is the block scheme of this electricity structure of expression.Shown in this figure, the electric capacity line 113 of the opposing party's storage capacitor electrode of multi-strip scanning line 112 and formation memory capacitance forms according to the mode of extending along X (OK) direction respectively, on the other hand, data line 114 forms according to the mode of extending along Y (row) direction, corresponding with their infall, form pixel 120.In this sweep trace 112, respectively by 2 adjacent sweep traces 112, formation scanline groups 115a, 115b ... (115).Scanline groups 115a is made of 2 sweep traces 112 of the 1st row and the 2nd row, and scanline groups 115b is made of 2 sweep traces 112 of the 3rd row and the 4th row.Here, if for convenience of explanation, the bar number of sweep trace 112 (electric capacity line 113) is " m ", and the bar number of data line 114 is " n ", and then pixel 120 is arranged according to the matrix shape of the capable n row of m.In addition, in the present embodiment, aspect the record of accompanying drawing, m, n are even number, but are not limited thereto.
Here, if be conceived to 1 pixel 120, then the grid of the thin film transistor (TFT) of N channel-type (ThinFilm Transistor: be called " TFT " below) 116 is connected with sweep trace 112, its source electrode is connected with data line 114, in addition, its drain electrode is connected with the capacitance electrode that conduct constitutes the pixel current potential side of pixel electrode 118 and memory capacitance 119.As described above, pixel electrode 118 is relative with counter electrode 108, and in addition, between two electrodes, holding liquid crystal 105 constitutes liquid crystal capacitance.That is, liquid crystal capacitance is that an end is a pixel electrode 118, and the other end is a counter electrode 108, the structure of holding liquid crystal 105.In this structure, be noble potential if supply with the sweep signal of sweep trace 112 as the conducting current potential, then TFT116 conducting, with the corresponding charge storage of the current potential of data line 114 in liquid crystal capacitance and memory capacitance 119.In addition, when present embodiment, another capacitance electrode that constitutes memory capacitance 119 jointly is connected with electric capacity line 113 at every row.
In addition, if be conceived to the Y side, then shown in shift register 130 (scan line drive circuit) image pattern 4 like that, the beginning pulsed D Y that passes on of the initial supply of (1F) changes successively according to the rising of clock signal C LY and the mode of decline during 1 vertical scan line, with sweep signal Ys1, Ys2, Ys3 ..., Ysm supply with respectively the 1st the row, the 2nd the row, the 3rd the row ..., sweep trace 112 that m is capable.Here, sweep trace Ys1, Ys2, Ys3 ..., shown in the Ysm image pattern 5 like that, according to mutual unduplicated mode,, become significant level (H level, high level) by per 1 horizontal scan period (1H).Like this, shift register 130 drives corresponding sweep trace 112 successively according to the conducting current potential.
In liquid crystal indicator 100,, electric capacity line drive circuit 171 (memory capacitance driving circuit) is set also at every row.Here, generally, to with i (i is for satisfying the integer of 1≤i≤m) the corresponding electric capacity line drive circuit 171 of row, supply with and the capable corresponding sweep signal Ysi of i, in addition, also supply with the capacitance control signal CSL that controls the timing of exporting, the polarity control signal POL (with reference to Fig. 5) that presses the reversal of poles of per 2 horizontal scan period (2H) supply logic level.Here, capacitance control signal CSL has 1 high level by per 2 horizontal scan period (2H).
The logic level of polarity control signal POL when electric capacity line drive circuit 171 keeps the logic level of sweep signal Ysi to be high level, if the logic level that is kept is a high level, then select input end A, otherwise, if be low level, then select input end B, form electric capacity swinging signal VMOSi, at capacitance control signal CSL is the timing of high level, and VMOSi feeds to the capable electric capacity line 113 of i with this electric capacity swinging signal.
Fig. 4 is the circuit diagram of the circuit structure of expression electric capacity line drive circuit 171.Electric capacity line drive circuit 171 comprises latch unit 172, the logic level of the polarity control signal POL when this latch unit 172 keeps sweep signal Ysi logic level to be high level; Latch unit 173, this latch unit 173 is the timing of high level at capacitance control signal CSL, will export as selection control signal Cs by the level that latch unit 172 keeps; Selector switch 174, this selector switch 174 is corresponding to the level of selecting control signal Cs, and to the current potential of input end A, any person in the current potential of input end B selects, and it as electric capacity swinging signal VMOS, is supplied with electric capacity line 113; Logical OR non-(NOR) gate circuit 175, this circuit 175 with the logic of the reverse signal of capacitance control signal CSL and sweep signal Ysi and reverse signal supply with latch unit 173.Form following scheme, wherein, by the output signal of logical OR not circuit 175, when sweep signal Ysi was high level, even be under the situation of high level at capacitance control signal CSL, latch unit 173 was not still exported the level that keeps by latch unit 172.
When the non-high level of sweep signal Ysi, do not supply with the high level signal of capacitance control signal CSL, can not adopt OR-NOT circuit 175 directly capacitance control signal CSL to be supplied with latch unit 173 yet.Through adopting OR-NOT circuit 175, can irrespectively supply with capacitance control signal CSL with the current potential of sweep signal Ysi.Sweep signal Ysi is that high level still can be supplied with capacitance control signal CSL as high level thus.
, turn back to Fig. 3 here, the current potential of the input end A of the electric capacity line drive circuit 171 of odd-numbered line is the electric capacity current potential VMOSH of high-order side, and the current potential of its input end B is the electric capacity current potential VMOSL of low level side.On the other hand, the current potential of the input end A of the capacity line drive circuit 171 of even number line is the electric capacity current potential VMOSL of low level side, and the current potential of its input end B is the capacity current potential VMOSH of high-order side.That is, in the electric capacity line drive circuit 171 of the electric capacity line drive circuit 171 of odd-numbered line, even number line, the electric capacity current potential of input end A, B is in the relation that every row exchanges.Here, polarity control signal POL for the current potential of selecting input end A or input end B, according to per 2 horizontal scan period (2H), logic level counter-rotating (with reference to Fig. 5), select and the corresponding sweep trace of counter-rotating between, alternately offset, thus, from corresponding electric capacity line drive circuit 171, the electric capacity current potential corresponding to each scanline groups 115a, 115b ..., exchange and export.
Be conceived to the X side below, shown in shift register 150 image patterns 6 like that, change passing on beginning pulsed D X successively according to the mode of the rising of clock signal C LS and decline, according to exclusive mode mutually export respectively the sampling control signal Xs1, the Xs2 that constitute significant level (high level) ..., Xsn.Here, sampling control signal Xs1, Xs2 ..., Xsn is according to mutual unduplicated mode, forms significant level (high level) successively.
In addition, at the outgoing side of shift register 150,, the 1st sampling switch the 152, the 1st latch circuit the 154, the 2nd sampling switch the 156, the 2nd latch circuit 158 and D/A converter 160 is set respectively at every row of data line 114.Wherein, general, with corresponding the 1st sampling switch 152 of j (j is the integer of 1≤j≤n) row when sampling control signal Xsj is significant level, realize conducting, to the gradation data Data processing of taking a sample.
Here, gradation data Data is the numerical data of 4 bits of the gray scale (concentration) of indication pixel 120.Thus, in the liquid crystal indicator of present embodiment, pixel 120 is carried out the demonstration of 16 (=24) gray scale according to the gradation data Data of 4 bits.In addition, by mounting terminal 107 (with reference to Fig. 1), from not shown external circuit, the mode of supplying with predetermined timing constitutes according to gradation data Data.
Then, being listed as 154 pairs of corresponding the 1st latch circuits with j carries out breech lock and handles by being listed as the take a sample gradation data Data that handles of corresponding the 1st sampling switch 152 with this j.Then, be listed as corresponding the 2nd sampling switch 156 when latch pulse LP is significant level (high level), to carrying out gradation data Data that breech lock the handles processing of taking a sample by being listed as corresponding the 1st latch circuit 154 with j with j.In addition, being listed as 158 pairs of corresponding the 2nd latch circuits with j carries out breech lock and handles by being listed as gradation data Data that corresponding the 2nd sampling switch 156 takes a sample with j.
Then, the D/A converter 160 of j row will be converted to the simulating signal that writes the corresponding polarity side of logic level of indicator signal PS with polarity by being listed as the gradation data Data that corresponding the 2nd latch circuit 158 breech locks handle with j, export as data-signal Sj, thus, make the current potential of data line 114 be the potential difference (PD) corresponding with gray scale.Here, when this logic level was high level, polarity write the signal that indicator signal PS writes for the positive polarity of indicating pixel 120, and on the other hand, when this logic was low level, polarity write the signal that indicator signal PS writes for the negative polarity of indicating pixel 120.When present embodiment, polarity write indicator signal PS be shown in the image pattern 6 like that, by polarity control signal POL, postpone 1 horizontal period, with scanline groups 115a, 115b ... corresponding, according to per 2 horizontal scan period (2H), the signal of logic level counter-rotating (2H inversion driving).Thus, the current potential of data line 114 for belong to corresponding scanline groups 115a, 115b ... sweep trace to each other, with identical to write polarity corresponding, for adjacent scanline groups to each other, with opposite to write polarity corresponding.In addition, polarity writes the logic level of indicator signal PS only at same horizontal scan period the time, and also according to per 1 vertical scanning period, (with reference to the bracket among Fig. 5) reverses.
In addition, shift register 150, sampling switch 152,156, latch circuit 154,158 are corresponding with data line drive circuit of the present invention with D/A converter 160.In addition, not only this data line drive circuit, and shift register 130 and corresponding with LCD drive circuits of the present invention as the electric capacity line drive circuit 171 of memory capacitance driving circuit.
In the present embodiment, write indicator signal PS, capacitance control signal CSL, polarity control signal POL and electric capacity current potential VMOSH, VMOSL by mounting terminal 107 (with reference to Fig. 1) according to passing on beginning pulsed D X, DY, clock signal C LX, CLY, latch pulse LP, polarity, from not shown external circuit, the mode that timing is according to the rules supplied with constitutes, but, also can be according in liquid crystal indicator, all or part of the mode of signal generating circuit that these signals of output are set constitutes.
In addition, in the present embodiment, the reversal of poles of pixel 120 or liquid crystal capacitance refers to that the current potential with the counter electrode 108 of the other end of liquid crystal capacitance is a benchmark, and this voltage level is exchanged counter-rotating.In addition, in Fig. 3, the arrange regional of shift register 130, electric capacity line drive circuit 171 relative pixels 120, both sides about branch and arranging, but in fact, also can according to from about any side, the mode of driven sweep line and electric capacity line constitutes.
(work of 1-2:Y side)
Below the Y side work in the work of the liquid crystal indicator of such scheme is described.Here, Fig. 5 is the sequential chart of work that is used to illustrate the Y side of this liquid crystal indicator.
Shown in this figure, passing on of initial supply in vertical scanning period begins pulsed D Y by shift register 130 (with reference to Fig. 3), the rising of accompanying clock signal CLY and decline and change, by per 1 horizontal scan period 1H, successively exclusively as sweep signal Ys1, Ys2, the Ys3 of high level ..., Ysm and exporting.
Here, in initial 1 vertical scanning period (1F), when sweep signal Ys1 was high level, it was high level (be positioned at the pixel 120 of the sweep trace 112 of the 1st row relatively, indication positive polarity writes) that polarity writes indicator signal PS.In addition, polarity control signal POL is a high level, with latch unit 172 these logic levels of maintenance of the corresponding electric capacity line drive circuit 171 of the 1st row.Descend at sweep signal Ys1, after the TFT116 of pixel 120 that is positioned at the 1st row ends, if capacitance control signal CSL is a high level, the level of the polarity control signal POL that has then kept is as signal Cs1, from latch unit 173 outputs, consequently, because electric capacity line drive circuit 171 is selected the current potential VMOSH of input end A, so electric capacity swinging signal VMOS1 displacement is the electric capacity current potential VMOSH of high-order side.
Then, when sweep signal Ys2 was high level, polarity write indicator signal PS and keeps high level (to the pixel 120 that is positioned at the 2nd horizontal scanning line 112, indication positive polarity writes).At this moment, polarity control signal POL is displaced to low level, with latch unit 172 these logic levels of maintenance of the corresponding electric capacity line drive circuit 171 of the 2nd row.Descend at sweep signal Ys2, after the TFT116 of pixel 120 that is positioned at the 2nd row ends, if capacitance control signal CSL is a high level, the level of the polarity control signal POL that has then kept is as signal Cs2, from latch unit 173 outputs, consequently, electric capacity line drive circuit 171 is selected the current potential of input end B.Here, because VMOSH supplies with input end B, so electric capacity swinging signal VMOS2 is also identical with VMOS1, being shifted is the electric capacity current potential VMOSH of high-order side.
Here, the high impulse of capacitance control signal CSL is supplied with 1 time in 2 horizontal scan period (2H), this is not regularly after the firm decline of sweep signal Ys1, and after the firm decline of sweep signal Ys2, thus, the 1st row and the 2nd capable electric capacity line drive circuit 171 be in the timing of the high level of capacitance control signal CSL, electric capacity swinging signal VMOS1 and VMOS2 is displaced to the electric capacity current potential VMOSH of high-order side.
Then, when sweep signal Ys3 was high level, polarity write indicator signal PS and is displaced to low level (to being positioned at the pixel 120 of the 3rd sweep trace 112 of going, the indication negative polarity writes).At this moment, polarity control signal POL keeps low level, with latch unit 172 these logic levels of maintenance of the corresponding electric capacity line drive circuit 171 of the 3rd row.Descend at sweep signal Ys3, after the TFT116 of pixel 120 that is positioned at the 3rd row ends, if capacitance control signal CSL is a high level, the level of the polarity control signal POL that has then kept is as signal Cs3, from latch unit 173 outputs, consequently, electric capacity line drive circuit 171 is selected the current potential of input end B.Here, because VMOSL supplies with input end B, so electric capacity swinging signal VMOS3 displacement is the electric capacity current potential VMOSL of low level side.
Then, when sweep signal Ys4 was high level, polarity write indicator signal PS and keeps low level (to being positioned at the pixel 120 of the 4th sweep trace 12 of going, the indication negative polarity writes).At this moment, polarity control signal POL is displaced to high level, with latch unit 172 these logic levels of maintenance of the corresponding electric capacity line drive circuit 171 of the 4th row.Descend at sweep signal Ys4, after the TFT116 of pixel 120 that is positioned at the 4th row ends, if capacitance control signal CSL is a high level, the level of the polarity control signal POL that has then kept is as signal Cs4, from latch unit 173 outputs, consequently, electric capacity line drive circuit 171 is selected the current potential of input end A.Here, because VMOSL supplies with input end A, so electric capacity swinging signal VMOS4 displacement is the electric capacity current potential VMOSL of low level side.
Here, because the timing of the high level pulse of capacitance control signal CSL is not after the firm decline of sweep signal Ys3, and after the firm decline of sweep signal Ys4, so the 3rd row and the 4th electric capacity line drive circuit 171 of going be in the timing of the high level pulse of capacitance control signal CSL, electric capacity swinging signal VMOS3 and VMOS4 are displaced to the electric capacity current potential VMOSL of low level side.Like this, electric capacity line drive circuit 171 simultaneously to belong to scanline groups 115a, 115b ... sweep trace 112 carry out the displacement of the current potential of memory capacitance 119 each other.
Here, between the electric capacity line drive circuit 171 of the electric capacity line drive circuit 171 of even number line and odd-numbered line, the electric capacity current potential of supplying with input end A, B replaces (with reference to Fig. 3) mutually, is used to select the signal POL of input end to reverse by per 2 horizontal scan period (2H).Such as, constitute in the following manner, promptly, supply with electric capacity swinging signal VMOS1, the electric capacity current potential VMOSH that VMOS2 all is displaced to high-order side with the electric capacity line 113 of corresponding the 1st row of initial scanline groups 115a and the 2nd row, supply with and go with following scanning line set 115b the corresponding the 3rd and electric capacity swinging signal VMOS1, the electric capacity current potential VMOSL that VMOS2 all is displaced to the low level side of the 4th electric capacity line 113 of going.
Below identical be operated in the 5th row, the 6th row, the 7th row ..., carry out repeatedly in the capable electric capacity line drive circuit 171 of m.Displacement as the current potential of the displacement of electric capacity current potential is carried out each other at the sweep trace that belongs to 1 scanline groups simultaneously.Promptly, scanline groups is formed by 2 sweep traces, but, be respectively high level if supply with the sweep signal Ysi and the Ysi+1 of the sweep trace 112 that i is capable and i+1 is capable of the scanline groups 115 that belongs to odd number, then to sweep trace 112, indication positive polarity writes, after this sweep trace Ysi, Ysi+1 drop to low level, if capacitance control signal CSL is a high level, then supply with electric capacity swinging signal VMOSi, the VMOSi+1 of the capable electric capacity line 113 of i electric capacity current potential VMOSL, be displaced to the electric capacity current potential VMOSH of high-order side from the low level side.On the other hand, be respectively high level if supply with sweep signal Ysi, the Ysi+1 of the sweep trace 112 that belongs to odd number scanline groups 115, then indicate negative polarity to write, then, after this sweep signal Ysi, Ysi+1 drop to low level, if capacitance control signal CSL is a high level, then electric capacity swinging signal VMOSi, VMOSi+1 are displaced to the electric capacity current potential VMOSL of low level side simultaneously from the electric capacity current potential VMOSH of high-order side.
In addition, polarity control signal POL is last relatively vertical scanning period in next vertical scanning period (1F), the signal of level counter-rotating.Thus, if supplying with sweep signal Ysi, the Ysi+1 of the sweep trace 112 that constitutes odd number scanline groups 115 is high level, then indicate negative polarity to write, then, after this sweep signal Ysi drops to low level, if capacitance control signal CSL is a high level, then electric capacity swinging signal VMOSi, VMOSi+1 are displaced to the electric capacity current potential VMOSL of low level side from the electric capacity current potential VMOSH of high-order side.On the other hand, if supplying with sweep signal Ysi, the Ysi+1 of the sweep trace 112 of the scanline groups 115 that constitutes odd number is high level, then to sweep trace 112, indication positive polarity writes, then, after this sweep signal Ysi drops to low level, if capacitance control signal CSL is a high level, then supply with electric capacity swinging signal VMOSi, the VMOSi+1 of the capable electric capacity line 113 of i electric capacity current potential VMOSL, be displaced to the electric capacity current potential VMOSH of high-order side simultaneously from low potential side.
(work of 1-3:X side)
Below in the work of liquid crystal indicator, X side job description.Here, Fig. 6 is the sequential chart of work that is used to illustrate the X side of this liquid crystal indicator.
At first, in Fig. 6, if 1 horizontal scan period that is conceived to supply with the sweep signal Ys1 of the sweep trace 112 of the 1st row and is high level (in the drawings, during shown in (1)), then before this period, supply with successively with 1 row, 1 row, 1 row, 2 row ... the corresponding gradation data Data of pixel of 1 row n row.Wherein, in the timing of supplying with the corresponding gradation data Data of pixel that is listed as with 1 row 1, if from the sampling control signal Xs1 of shift register 150 outputs is high level, then by with the 1st row the ending of corresponding the 1st sampling switch 152, above-mentioned gradation data is handled by carrying out breech lock with corresponding the 1st latch circuit 154 of the 1st row.
Then, in the timing of supplying with the corresponding gradation data Data of point that is listed as with 1 row 2, if sampling control signal Xs2 is a high level, then by with the 2nd row corresponding the 1st sampling switch 152 conducting, this gradation data is handled by carrying out breech lock with corresponding the 1st sampling latch circuit 154 of the 2nd row respectively, below in an identical manner, the corresponding gradation data Data of point with 1 row n row carries out the breech lock processing by being listed as corresponding the 1st latch circuit 154 with n respectively.Thus, with the corresponding gradation data Data of n pixel that is positioned at the 1st row respectively by be listed as with the 1st row, the 2nd ..., n is listed as corresponding the 1st latch circuit 154 and carries out breech lock and handle.
Then, if output latch pulse LP (if its logic level is a high level), then by respectively with the 1st row, the 2nd row ..., the n gradation data Data conducting by the 2nd sampling switch 156 respectively that is listed as corresponding the 1st latch circuit 154 breech locks, carry out breech lock by the 2nd latch circuit 158 of corresponding respectively row together and handle.
Afterwards, respectively by with the 1st row, the 2nd row ..., n is listed as gradation data Data that corresponding the 2nd latch circuit 158 breech locks the handle D/A converter 160 by corresponding respectively row, be converted to the simulating signal that writes the corresponding polarity side of logic level of indicator signal PS with polarity, as data-signal S1, S2 ..., Sn current potential and export.At this moment, if it is high level that polarity writes indicator signal PS, then data-signal S1, S2 ..., Sn writes corresponding with positive polarity, specifically, from with the corresponding current potential Vwt of the white level of side of the positive electrode (+), to with the scope of the corresponding current potential Vbk of the black level of side of the positive electrode (+), Data is corresponding with gradation data.
Then, if the sweep signal Ys2 that is conceived to supply with the sweep trace 112 of the 2nd row is 1 horizontal scan period of high level (during (2) among figure expression), then before this period, carry out and with 2 row 1 row, 2 row, 2 row ..., 2 row n row the corresponding gradation data Data of pixel supply with successively, carry out with sweep signal Ys1 be high level during identical work.Consequently, as data-signal S1, S2 ..., Sn, output is converted to the signal of simulating signal that writes the corresponding polarity side of logic level of indicator signal PS with polarity.
Here, because by during shown in (1) among the figure and by during shown in (2), the logic level that polarity writes indicator signal PS keeps identical high level, so data-signal S1, S2 ..., Sn output polarity all identical.
Because polarity writes the logic level of indicator signal PS by per 2 horizontal scan period counter-rotating, so the sweep signal Ys3 that supplies with the 3rd sweep trace 112 of going is displaced to the L level becoming 1 horizontal scan period of high level (during (3) among figure expression).So, if be conceived to by during shown in (3), then before this period, carry out with supply with successively and 2 row, 1 row, 2 row 2 are listed as ..., 2 row n row the corresponding gradation data Data of pixel, sweep signal Ys2 be high level during identical work, still, the logic level that polarity writes indicator signal PS is a low level, consequently, as data-signal S2 ..., Sn, output be converted to sweep signal Ys1, Ys2 be high level during the signal of simulating signal of opposite polarity.
Then, whenever sweep signal Ys4, Ys5 ... when Ysm is high level, carry out identical work repeatedly.Promptly, before the sweep signal Ysi that supplies with the capable sweep trace 112 of i is 1 horizontal scan period of high level, supply with capable 1 row successively with i, capable 2 row of i, the corresponding gradation data Data of pixel of the capable n row of i, respectively by with the 1st row, the 2nd row, n is listed as corresponding the 1st latch circuit 154 and carries out the breech lock processing, then, output by latch pulse LP, the 2nd latch circuit 158 by corresponding row carries out the breech lock processing together, D/A converter 160 by corresponding respectively row, be converted to the simulating signal that writes the corresponding polarity side of logic level of indicator signal PS with polarity, as data-signal S1, S2, Sn and exporting.
At this moment, during corresponding with the sweep trace 112 that belongs to odd number scanline groups 115, because it is high level that polarity writes indicator signal PS, so data-signal S1, S2 ..., Sn current potential and positive polarity write corresponding, on the other hand, during corresponding with the sweep trace 112 of the scanline groups 115 that belongs to even number, be low level because polarity writes indicator signal PS, so data-signal S1, S2 ..., Sn current potential and negative polarity write corresponding.That is, belong to corresponding scanline groups 115a, 115b ... sweep trace 112 in, with same to write polarity corresponding, do not carry out reversal of poles.
In addition, in next vertical scanning period, carry out identical work, but because when same horizontal scan period, polarity writes indicator signal PS by per 1 vertical scanning period counter-rotating, thus data-signal S1, S2 ..., Sn current potential during corresponding with the sweep trace 112 of the scanline groups 115 that belongs to odd number, write corresponding with negative polarity, on the other hand, during corresponding, write corresponding with positive polarity with the sweep trace 112 that belongs to even number scanline groups 115.
Result as above-mentioned work, in electric capacity line drive circuit 171, when if sweep trace 112 is high level (the conducting current potential of TFT116), the current potential of data line 114 writes corresponding with positive polarity, then be displaced to low level (stopping potential of TFT116) afterwards at sweep trace 112, with the potential shift of the opposing party's storage capacitor electrode of memory capacitance 119 to high-order side, on the other hand, if the current potential of data line 114 writes corresponding with negative polarity, then sweep trace 112 is displaced to after the low level, with the potential shift of the opposing party's storage capacitor electrode of memory capacitance 119 to the low level side.
(1-4: the work of memory capacitance and liquid crystal capacitance)
To when carrying out the work of Y side as described above and X side, the work of memory capacitance and liquid crystal capacitance is described below.Fig. 7 (a), figure (7) (b) and the corresponding figures of Fig. 7 (c) be to be used for the figure that the storage work to the electric charge of these electric capacity describes.
Here, for convenience of explanation, to write fashionable be example and the pixel 120 that is positioned at the capable j of i row is carried out concise and to the point description to carry out positive pole.The electric capacity current potential VMOSL of low level side, the current potential LCcom of counter electrode 108 are actually different as aftermentioned, still, here, for the purpose of simplifying the description, treat according to the mode that mutual current potential equates.
At first, if sweep signal Ysi is high level (a conducting current potential) because the TFT116 conducting of this pixel, shown in the image pattern 7 (a) like that, so at the memory capacitance C of this pixel StgWith liquid crystal capacitance C LCIn, the corresponding electric charge of current potential of storage and data line Sj.At this moment, will be at memory capacitance C StgWith liquid crystal capacitance C LCIn the charging write voltage as V 0
Then, if signal Vsi be low level (cut-off level) afterwards, capacitance control signal CSL is a high level, then the TFT116 of this pixel ends, and in positive polarity writes, supply with the capable electric capacity line 113 of i electric capacity swinging signal VMOSi current potential as described above, from the electric capacity current potential VMOSL of low level side, be displaced to the electric capacity current potential VMOSH of high-order side.Thus, shown in the image pattern 7 (b) like that, memory capacitance C StgCharging voltage according to as the voltage V1 of shift amount and rise.Here, V1=(VMOSH-VMOSL).
Wherein, because memory capacitance C StgAn end be connected with pixel electrode 118, so shown in the image pattern 7 (c) like that, the memory capacitance C that electric charge is risen from voltage Stg, be displaced to liquid crystal capacitance C LCIn.In addition, if two electric capacity do not have potential difference (PD), because the end-of-shift of electric charge, so the charging voltage of two electric capacity finally is voltage V 2This voltage V 2For TFT116 by the time almost whole during, the outer continuously liquid crystal capacitance C that is added on LCOn, so can be considered in fact, during from the conducting of TFT116, at liquid crystal capacitance C LCLast impressed voltage V 2
Adopting memory capacitance C here, StgWith liquid crystal capacitance C LCThe time, voltage V 2Can as following formula (1), represent.
V 2＝V 0+V 1·C stg/(C stg+C LC) ……(1)
In addition, if memory capacitance C StgFully greater than liquid crystal capacitance C LC, then to be approximately following formula (2) such for formula (1).
V 2＝V 0+V 1 ……(2)
That is, will the final outer liquid crystal capacitance C that is added on LCOn voltage V 2Be reduced to from initially writing voltage V 0Beginning is only according to the ascending amount V of electric capacity swinging signal VMOSi 1, be displaced to the voltage of high-order side.
In addition, here, for simplicity, the work to Fig. 7 (b) and Fig. 7 (c) is described respectively, and still, in fact, both work is carried out simultaneously concurrently.In addition,, write fashionable being described here to carrying out positive polarity, but write in negative polarity fashionable, if memory capacitance C StgFully greater than liquid crystal capacitance C LC, the then final outer liquid crystal capacitance C that is added on LCOn voltage V 2From initially writing voltage V 0, only according to the shift amount V of electric capacity swinging signal VMOSi 1, be displaced to the low level side.
Also have, at the pixel 120 that is positioned at the capable j of i row, in fact carrying out positive polarity writes fashionable, as described above, when the TFT116 of this pixel conducting, be added on the current potential of the electric capacity swinging signal VMOSi on the capable electric capacity line 113 of i outward, promptly, the current potential of the opposing party's storage capacitor electrode of the memory capacitance Cstg of this pixel (119) is the electric capacity current potential VMOSL of low level side, in addition, and as liquid crystal capacitance C LCThe current potential of counter electrode 108 of the other end be certain LCcom (with reference to Fig. 8 (a)).That is memory capacitance C, StgThe reference potential and the liquid crystal capacitance C of charging voltage LCThe reference potential difference of charging voltage.
But, shown in the image pattern 8 (b) like that, current potential Pix (the i of the pixel electrode 118 of the pixel 120 of the capable j row of i, j) aspect following, almost do not change with the explanation of Fig. 7 (a), Fig. 7 (b) and Fig. 7 (c), this following aspect refers to: the 1st, when the TFT116 conducting, once forming the current potential of the data-signal Sj of the data line 114 of supplying with the j row; The 2nd, after the ending of TFT116, when CSLi is high level, if for positive polarity writes, then electric capacity swinging signal VMOSi is from the electric capacity current potential VMOSL of low level side, be displaced to the electric capacity current potential VMOSH of high-order side, thus, be displaced to high-order side, on the other hand, if for negative polarity writes, then electric capacity swinging signal VMOSi is displaced to the electric capacity current potential VMOSL of low level side, thus from the electric capacity current potential VMOSH of high-order side, be displaced to the low level side, and this shift amount and data-signal Sj write current potential, memory capacitance Cstg and liquid crystal capacitance C LCRatio corresponding.
In addition, Fig. 8 (b) has represented 4 following aspects, promptly, current potential Pix (i at the pixel electrode 118 of the pixel 120 of the capable j of i row, j) when the TFT116 conducting, during for the corresponding current potential Vwt of white level (+) that writes with positive polarity, after TFT116 ends, according to this current potential Vwt (+), memory capacitance C StgWith liquid crystal capacitance C LCThe corresponding component Δ of ratio Vwt, be displaced to high-order side; The current potential Pix of pixel electrode 118 (i, j) when the TFT116 conducting, during for the corresponding current potential Vbk of black level (+) that writes with positive polarity, after TFT116 ends, according to current potential Vbk (+), memory capacitance C StgWith liquid crystal capacitance C LCThe corresponding component Δ of ratio Vbk, be displaced to high-order side; The current potential Pix of pixel electrode 118 (i, j) when the TFT116 conducting, during for the corresponding current potential Vwt of white level (-) that writes with negative polarity, after TFT116 ends, according to current potential Vwt (-), memory capacitance C StgWith liquid crystal capacitance C LCThe corresponding component Δ of ratio Vwt, be displaced to the low level side; The current potential Pix of pixel electrode 118 (i, j) when the TFT116 conducting, during for the corresponding current potential Vbk of black level (-) that writes with negative polarity, after TFT116 ends, according to current potential Vbk (-), memory capacitance C StgWith liquid crystal capacitance C LCThe corresponding component Δ of ratio Vbk, be displaced to the low level side.
According to present embodiment, shift amount corresponding to electric capacity swinging signal VMOS, make from data line 114, data-signal S1, the S2 of supply pixel electrode 118 ..., Sn current potential rise (or decline), with low-voltage, carry out the driving of data line 114, in addition, when current potential is supplied with data line 114, for belong to scanline groups 115a, 115b ... adjacent multi-strip scanning line, it is identical to write polarity, does not change.That is, data line 114 write polarity with belong to scanline groups 115a, 115b ... in the adjacent sweep trace 112 of each scanline groups corresponding, identical 2 horizontal scan period.So, and by per 1 horizontal scan period, compare when carrying out inversion driving, can make the frequency of inversion driving data line reduce approximately half, seek the further reduction of power consumption.
In addition, with regard to adjacent scanline groups 115a, 115b, the current potential of data line 114 to write polarity opposite each other.So, even in unevenness by liquid crystal indicator 100, current potential at pixel electrode, under the situation of the deviation that every data line produces, the current potential of pixel electrode 118 at scanline groups 115a, 115b ... in each, be opposite polarity, thus, the variation of the brightness of the demonstration that the deviation of elimination current potential causes.Consequently, can reduce the situation of the clutter (noise) that shows strip corresponding to liquid crystal indicator 100, data line.
(2: the 2 embodiment)
In above-mentioned the 1st embodiment, data line 114 write polarity corresponding to belong to scanline groups 115a, 115b ... in the adjacent scanning lines 112 of respective scan line group, identical 2 horizontal scan period.That is, in the electric capacity line drive circuit 171 of the 1st row and the 2nd row, electric capacity swinging signal VMOS1 and VMOS2 are displaced to the same potential side.In addition, according to same timing, displacement electric capacity swinging signal VMOS1 and VMOS2.To adopting this scheme, the 2nd embodiment that improves circuit area is described.
Fig. 9 is the block scheme of the circuit structure of the liquid crystal indicator 200 of expression the 2nd embodiment of the present invention.
In the 2nd embodiment, at the corresponding scanline groups 115a, the 115b that constitute the opposing party's storage capacitor electrode in the memory capacitance ..., 1 electric capacity line drive circuit 171 is set.That is, be that with the 1st embodiment difference 1 electric capacity line drive circuit 171 drives many electric capacity lines 113 that belong to scanline groups 115a.Because the 1st embodiment for other structure of the liquid crystal indicator of the 2nd embodiment and Fig. 1～shown in Figure 3 is identical, the Therefore, omited is to its description.
Shown in this figure, in the 2nd embodiment, belong to scanline groups 115a, 115b ... adjacent electric capacity line 113 with belong to scanline groups 115a, 115b ... in the adjacent sweep trace 112 of respective scan line group corresponding.Because electric capacity line drive circuit 171 in same timing, is changed electric capacity swinging signal VMOS1 and VMOS2, so each electric capacity line group 115a, 115b ... shared 1 electric capacity line drive circuit 171 makes the quantity of electric capacity line drive circuit 171 reduce half simultaneously.Thus, the area of electric capacity line drive circuit 171 can be reduced, the area and the power consumption of circuit integral body can be reduced.
(3: the 3 embodiment)
In above-mentioned the 1st embodiment, be followed successively by the timing of conducting current potential at sweep trace, data line for and write the corresponding current potential of polarity, on the other hand, simultaneously to each other, carry out the displacement of current potential of the other end of memory capacitance at the sweep trace that belongs to 1 scanline groups.Thus, from the current potential of data line for regulation, to time that the displacement of the current potential of the opposing party's storage capacitor electrode of memory capacitance begins for the sweep trace that belongs to 1 scanline groups, be mutual different.Below to eliminating respectively because this time poor, in each sweep trace, the 3rd different embodiment of the electrode voltage of the shift result of current potential is described.
Figure 10 is the block scheme of the circuit structure of the liquid crystal indicator of expression the present invention the 3rd embodiment.
Shown in the image pattern 10 like that, in the electric capacity line drive circuit 171 that is provided with at every row, with the corresponding electric capacity line drive circuit 171 of odd-numbered line, supply with capacitance control signal CSLo, to with the corresponding electric capacity line drive circuit 171 of even number line, supply with capacitance control signal CSL.Here, shown in the image pattern 11 like that, capacitance control signal CSL is the signal of the content identical with the 1st embodiment, capacitance control signal CSLo is relative capacitance control signal CSL, the signal of the waveform of 1 horizontal scan period that moves ahead.
In addition, the 1st embodiment of other structure of the liquid crystal indicator of the 3rd embodiment and Fig. 1～shown in Figure 3 is identical, and the Therefore, omited is to its description.
Figure 11 is the sequential chart of the work usefulness of the Y side of the liquid crystal indicator of explanation the 3rd embodiment.
Here, in initial 1 vertical scanning period (1F), when sweep signal Ys1 was high level, polarity control signal POL was a high level, with latch unit 172 these logic levels of maintenance of the corresponding electric capacity line drive circuit 171 of the 1st row.If descend at sweep signal Ys1, after the TFT116 that is positioned at the pixel 120 of the 1st row ended, capacitance control signal CSLo was a high level, and the level of the polarity control signal POL that has then kept is as signal Cs1, from latch unit 173 outputs.
Then, when sweep signal Ys2 was high level, polarity write indicator signal PS and keeps high level.At this moment, polarity control signal POL is displaced to low level, with the latch unit 172 maintenance logic levels of the corresponding electric capacity line drive circuit 171 of the 2nd row.If descend at sweep signal Ys2, after the TFT116 that is positioned at the pixel 120 of the 2nd row ended, capacitance control signal CSL was a high level, and the level of the polarity control signal POL that has then kept is exported from latch unit 173 as signal Cs2.
Here, the high level pulse of capacitance control signal CSLo is supplied with 1 time by per 2 horizontal scan period (2H), and this is regularly after the decline of scanning Ys1.In addition, the high level pulse of capacitance control signal CSL is also supplied with 1 time by per 2 horizontal scan period (2H), and still, this is regularly after the decline of sweep signal Ys2.
(4: the summary of liquid crystal indicator)
Like this, in the present embodiment, be followed successively by the timing of conducting current potential at sweep trace, data line for and write the corresponding current potential of polarity, the displacement of the current potential of the other end of memory capacitance is carried out after corresponding sweep trace is stopping potential respectively.Thus, from the current potential of data line for regulation, the time that begins to the displacement of the current potential of the opposing party's storage capacitor electrode of memory capacitance equates in whole sweep traces.Thus, the voltage of the shift result of current potential is different at every sweep trace, thus, can reduce voltage unbalanced of pixel electrode.
In addition, for sweep trace 112, at every in 2 adjacent sweep traces 112, constitute scanline groups 115 (115a, 115b) time to be described, still, the present invention is not limited to this.Scanline groups also can by such as, adjacent 3 or constitute more than 3 sweep trace.
In addition, driving circuit of the present invention is not limited to foregoing circuit, can adopt various structures.Such as, as the electric capacity line drive circuit of another embodiment, shown in the image pattern 12 like that, but also following structures, it comprises latch unit 472, and when the logic level of sweep signal Ysi or capacitance control signal CSL was high level, this latch unit 472 kept the logic level of sweep signal Ysi; Latch unit 473 when the logic level of sweep signal Ysi is high level, keeps the logic level of polarity control signal POL; Circuit for reversing 474, this circuit for reversing 474 will reverse by the level that latch unit 472 keeps corresponding to the level that keeps by latch unit 473, export as selecting control signal Cs; Selector switch 475, this selector switch 475 are corresponding to the level of selecting control signal Cs, and from the current potential of input end A, any person in the current potential of input end B selects to supply with electric capacity line 113 as electric capacity swinging signal VMOS.
In addition, in above-mentioned the 1st embodiment, to the current potential among the input end A, the B that are input to electric capacity line drive circuit 171 in odd-numbered line and even number line, be described when replacing mutually, still, the present invention is not limited to this, such as, can replace according to the unit of 2 scanline groups of going.In this occasion, not according to per 2 horizontal scan period, make polarity control signal POL counter-rotating, only by be input to current potential among input end A, the B alternately, can make the data line counter-rotating by per 2 horizontal period.In addition, be input in the scheme that the current potential of input end A, B replaces in odd-numbered line and even number line mutually,, keep easily, carry out the interchangeability of driving circuit of the counter-rotating of data line by per 1 horizontal scan period corresponding to the fineness of shown image.
Promptly, if adopt the scheme that the current potential among input end A, the B replaces mutually that is input in odd-numbered line and even number line, the high level pulse of capacitance control signal CSL is in each horizontal scan period, supply with 1 time, polarity control signal POL and polarity write indicator signal PS and are the signal in each vertical scanning period counter-rotating, thus, can be in each horizontal scan period, the driving of the counter-rotating of data line is carried out in realization.Thus, because the unevenness of the manufacturing of liquid crystal indicator etc., when the difference of every the data line that produces in the current potential of pixel electrode can not be ignored, can be at 1 adjacent sweep trace, the brightness of offsetting and reducing by the difference generation changes, and is converted to the inversion driving of each horizontal scan period.
In addition, in above-mentioned the 1st, the 2nd and the 3rd embodiment, adopt the gradation data Data of 4 bits, carry out 16 gray scales and show that still, the present invention is not limited to this.Such as, also can increase bit number, form more gray scale, also can pass through 3 pixels of R (red), G (green), B (indigo plant), constitute 1 point, thus, carry out colour and show.In addition, in an embodiment, at the non-state that adds of the voltage of liquid crystal capacitance, for the normal white mode of maximum transmission rate is described, but also can be in equal state, is the normal black pattern of minimum transmittance.
In addition, in an embodiment, device substrate 101 adopts glass substrate, but, also can adopt the technology of SOI (Silicon On Insulator), on the insulativity substrate of sapphire, quartz, glass etc., form silicon single-crystal film,, also can make various elements here, form device substrate 101.In addition, also can form like this, that is, device substrate 101 adopts silicon substrate etc., and, forms various elements here.When such, because on-off element can adopt FET at a high speed, so realize that easily its speed is higher than the work of TFT.But, when device substrate 101 does not have the transparency, must form pixel electrode 118 by by aluminium, form the measure in reflection horizon etc. in addition, as reflection-type.In addition, in an embodiment, adopt three such terminal type elements of TFT, still, also can adopt TFD (Thin FilmDiode: such two-terminal type element thin film diode) by the on-off element between data line 114 and pixel electrode 118.
Also have, in the above-described embodiments, liquid crystal adopts the TN type, but, also can adopt BTN (Bi-stable Twisted Nematic) the strong dielectric type of type etc. the bistability with storage property, high-molecular dispersed, (visitor: it is (main: as host), to arrange the liquid crystal of GH (guest host) type etc. of dye molecule according to the mode parallel with liquid crystal molecule guest) to be dissolved in the liquid crystal of certain molecules align to have anisotropic dyestuff in the absorption of the long axis direction of molecule and short-axis direction visible light.In addition, also can be when impressed voltage not relative two substrates of liquid crystal molecule, arrange along vertical direction, on the other hand, when impressed voltage, relative two substrates of liquid crystal molecule, the vertical orientated structure that along continuous straight runs is arranged also can be the added-time outside voltage is non-, relative two substrates of liquid crystal molecule, along continuous straight runs is arranged, on the other hand, and the added-time outside voltage, relative two substrates of liquid crystal molecule, the structure of parallel (level) orientation of vertically arranging.Like this, according to the present invention, liquid crystal, aligned adopt various.
(5. electronic equipment)
Electronic equipment to the liquid crystal indicator 100 that adopts the above embodiments is described below.
Figure 13 represents to adopt the structure of the portable telephone of liquid crystal indicator 100.This portable telephone 3000 comprises a plurality of action buttons 3001 and scroll button 3002, as the liquid crystal indicator 100 of display module.By this scroll button 3002 being operated the picture of roll display in liquid crystal indicator 100.
In addition, for electronic equipment, describing except reference Figure 13, also enumerate and comprise projector, personal computer, liquid crystal TV set, the digital data recorder of the type monitor direct viewing type of finding a view, on-vehicle navigation apparatus, pager, electronic memo, electronic calculator, word processor, workstation, videophone, POS terminal, digital camera, possess the equipment of contact type panel etc.In addition, obviously, the various electronic equipments in these can adopt the liquid crystal indicator of embodiment, application, distortion example.

Claims (7)

1. LCD drive circuits, wherein this liquid crystal indicator comprises: the scanline groups that is made of adjacent multi-strip scanning line; Data line; Liquid crystal capacitance, this liquid crystal capacitance be corresponding to the infall of each bar of above-mentioned multi-strip scanning line and above-mentioned data line and be provided with, and by counter electrode and pixel electrode holding liquid crystal; On-off element, this on-off element between above-mentioned data line and pixel electrodes, when above-mentioned sweep trace is the conducting current potential, its conducting, on the other hand, when this sweep trace was stopping potential, it ended; And memory capacitance, this memory capacitance comprises storage capacitor electrode, and the side in this storage capacitor electrode is connected with pixel electrodes, and the opposing party in this storage capacitor electrode and above-mentioned side's subtend ground configuration, and this driving circuit is characterised in that:
According to the conducting current potential, drive the scan line drive circuit of each bar of above-mentioned multi-strip scanning line successively;
Data line drive circuit, when passing through above-mentioned scan line drive circuit, when making each bar of above-mentioned multi-strip scanning line be the conducting current potential, make the current potential of the above-mentioned relatively counter electrode of current potential of above-mentioned data line, for with the corresponding potential difference (PD) of concentration, and be corresponding to the identical current potential that writes polarity for the sweep trace that belongs to above-mentioned scanline groups to each other; And
The memory capacitance driving circuit, wherein, when above-mentioned sweep trace is the conducting current potential, when the current potential of above-mentioned data line writes corresponding with positive polarity, then after above-mentioned sweep trace is displaced to stopping potential, with the potential shift of above-mentioned the opposing party's storage capacitor electrode of above-mentioned memory capacitance to high-order side, on the other hand, when the current potential of the above-mentioned data line in the above-mentioned conducting current potential and negative polarity write when corresponding, then after above-mentioned sweep trace is displaced to stopping potential, with the potential shift of above-mentioned the opposing party's storage capacitor electrode of above-mentioned memory capacitance to the low level side.
2. LCD drive circuits according to claim 1 is characterized in that above-mentioned memory capacitance driving circuit carries out and the displacement that belongs to the corresponding above-mentioned current potential of multi-strip scanning line of above-mentioned scanline groups simultaneously.
3. LCD drive circuits according to claim 1, the adjacent sweep trace that it is characterized in that belonging to above-mentioned scanline groups is 2;
Above-mentioned data line drive circuit carries out inversion driving by per 2 horizontal scan period to the polarity that writes of above-mentioned data line.
4. according to any one the described LCD drive circuits in the claim 1～3, it is characterized in that above-mentioned data line drive circuit makes above-mentioned data line in adjacent above-mentioned scanline groups to each other, for corresponding to the opposite current potential that writes polarity.
5. a liquid crystal indicator is characterized in that this liquid crystal indicator comprises any one the described LCD drive circuits in the claim 1～4.
6. an electronic equipment is characterized in that comprising the described liquid crystal indicator of claim 5.
7. the driving method of a liquid crystal indicator, wherein this liquid crystal indicator comprises: the scanline groups that is made of adjacent multi-strip scanning line; Data line; Liquid crystal capacitance, this liquid crystal capacitance be corresponding to the infall of each bar of above-mentioned multi-strip scanning line and above-mentioned data line and be provided with, and by counter electrode and pixel electrode holding liquid crystal; On-off element, this on-off element between above-mentioned data line and pixel electrodes, when above-mentioned sweep trace is the conducting current potential, its conducting, on the other hand, when this sweep trace was stopping potential, it ended; And memory capacitance, this memory capacitance comprises storage capacitor electrode, the side in this storage capacitor electrode is connected with pixel electrodes, and the opposing party in this storage capacitor electrode and above-mentioned side's subtend ground configuration, the method is characterized in that,
When driving liquid crystal indicator,
Making each the bar sweep trace in the above-mentioned multi-strip scanning line successively is the conducting current potential;
When each the bar sweep trace in above-mentioned multi-strip scanning line is the conducting current potential, make the current potential of the above-mentioned relatively counter electrode of current potential of above-mentioned data line, for with the corresponding potential difference (PD) of concentration, and for the sweep trace that belongs to above-mentioned scanline groups to each other, be corresponding to the identical current potential that writes polarity;
When above-mentioned sweep trace is the conducting current potential, when current potential that makes above-mentioned data line and positive polarity write corresponding, then after above-mentioned sweep trace is displaced to stopping potential, make the potential shift of the opposing party's storage capacitor electrode of above-mentioned memory capacitance arrive high-order side, on the other hand, when above-mentioned sweep trace is the conducting current potential, when current potential that makes above-mentioned data line and negative polarity write corresponding, then after above-mentioned sweep trace is displaced to stopping potential, the potential shift of the opposing party's storage capacitor electrode that makes above-mentioned memory capacitance is to the low level side.
CNB2006100727666A 2005-04-07 2006-04-07 Liquid crystal display device and driving circuit and driving method thereof, and electronic apparatus Expired - Fee Related CN100481203C (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196632B (en) * 2006-12-07 2010-09-22 索尼公司 Electro-optical device, scan line driving circuit, and electronic apparatus
CN101965607A (en) * 2007-12-28 2011-02-02 夏普株式会社 Auxiliary capacity wiring driving circuit and display device
CN101271660B (en) * 2007-03-20 2011-03-16 爱普生映像元器件有限公司 Electro-optical device, driving circuit and electronic apparatus
CN101236734B (en) * 2007-02-01 2011-07-13 奇美电子股份有限公司 Driving method for liquid crystal display device and liquid crystal display device
CN101577081B (en) * 2008-05-07 2012-01-25 索尼公司 Electro-optical device
CN103871384A (en) * 2013-12-24 2014-06-18 中国科学院微电子研究所 Liquid crystal material alternating current driving control signal generating structure
CN113971941A (en) * 2020-07-24 2022-01-25 虹曜电纸技术股份有限公司 Driving module for active matrix driving cholesterol liquid crystal display device and driving method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196632B (en) * 2006-12-07 2010-09-22 索尼公司 Electro-optical device, scan line driving circuit, and electronic apparatus
CN101236734B (en) * 2007-02-01 2011-07-13 奇美电子股份有限公司 Driving method for liquid crystal display device and liquid crystal display device
CN101271660B (en) * 2007-03-20 2011-03-16 爱普生映像元器件有限公司 Electro-optical device, driving circuit and electronic apparatus
CN101965607A (en) * 2007-12-28 2011-02-02 夏普株式会社 Auxiliary capacity wiring driving circuit and display device
CN101577081B (en) * 2008-05-07 2012-01-25 索尼公司 Electro-optical device
CN103871384A (en) * 2013-12-24 2014-06-18 中国科学院微电子研究所 Liquid crystal material alternating current driving control signal generating structure
CN103871384B (en) * 2013-12-24 2016-03-30 北京燕东微电子有限公司 A kind of liquid crystal material exchanges drive control signal generating structure
CN113971941A (en) * 2020-07-24 2022-01-25 虹曜电纸技术股份有限公司 Driving module for active matrix driving cholesterol liquid crystal display device and driving method thereof

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