CN1842763A - Method for switching between at least two operating modes of a processor unit and corresponding processor unit - Google Patents
Method for switching between at least two operating modes of a processor unit and corresponding processor unit Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
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- G06F11/16—Error detection or correction of the data by redundancy in hardware
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Abstract
The invention relates to a method for switching between at least two operating modes of a processor unit comprising at least two execution units. Said method is characterised in that a switch from a first operating mode to a second operating mode is triggered when the processor unit accesses a predefined memory address.
Description
Technical field
The present invention is from corresponding processor unit preamble, that be used for the method for switching and have at least two integrated performance elements between at least two kinds of operational modes of processor unit according to independent claims.
Background technology
This processor unit with at least two integrated performance elements also is as dual core or many kernels architecture and disclosed.According to current prior art, mainly former thereby propose this dual core or many kernels architecture for two kinds:
Can therefore come on the one hand implementation efficiency to improve, be that performance improves in the following manner, be about to two performance elements or kernel and treat as two computing units on the semiconductor subassembly and handle.In this configuration, two performance elements or different program or the tasks of kernel processes.Therefore can improve by implementation efficiency, thereby this configuration is called as efficiency mode or performance mode.
Second reason that realizes dual core or many kernels architecture is that security improves, and its mode is that two performance elements are carried out identical program redundantly.To two performance elements or CPU, be that the result of kernel compares, and under more conforming situation, can identify mistake.Below this configuration be called as safe mode.
Generally, described two kinds of configurations exclusively are comprised on dual core or the many kernels architecture, and the computing machine that promptly has at least two performance elements in principle only operates in a kind of pattern, is under performance mode or the safe mode.
Summary of the invention
Task of the present invention is, can realize the operation of this dual core or the multi-core processor unit combination with regard at least two kinds of methods of operation, and in the case especially in the switching strategy that is used for the safe mode that security improves and is used for realizing between the efficiency mode that efficient improves optimizing.
On the one hand wish redundant ground executive routine or task,, when carrying out the not high function of security requirement, be ready to redundant hardware and be unworthy pursuing on the other hand for the cost reason for safety reasons.According to the present invention, the switching by the optimization between at least two kinds of operational modes of processor unit solves this goal conflict.Therefore starting point of the present invention is a kind of method and corresponding processor unit of switching of being used between at least two kinds of operational modes of the processor unit with at least two performance elements.
Advantageously, realize the switching of from first to second operational mode by visiting the storage address that works as handover trigger given in advance.Promptly introduce nextport hardware component NextPort and corresponding method as switching device shifter (mode selector) or comparison means, for example be in operation and between the not high program of the security requirement of carrying out on two performance elements, switch independently of each other in the program of the security requirement height of just in safe mode, carrying out (sicherheitskritisch) redundantly with in efficiency mode best.
At this, program identical in first operational mode is synchronously carried out by at least two performance elements, and by set comparison means as the check of getting off, i.e. the state consistency of the performance element that when carrying out same program, is produced.About this point when inconsistent, then it is contemplated that, by emergency operating show fault, until the different faults reaction of turn-offing out of order unit.
In a kind of special form of implementation, safe mode is equivalent to first operational mode, and efficiency mode is equivalent to second operational mode.In the case, eligibly realize, especially trigger switching from second operational mode to first operational mode by interrupting device by interrupt request, wherein this interrupt request can trigger by time conditions on the one hand, perhaps also can trigger by status condition, just corresponding in two performance elements at least one definite state or also corresponding to the appearance of determining incident.
Advantageously realize being divided into specially the memory block of at least three separation, wherein performance element depends on operational mode separately and visits first memory block or second memory block, or is in this memory block and is connected.In the case, eligibly in a kind of special form of implementation, give each first memory block on distribution processor unit respectively at least two performance elements, wherein these performance elements first operational mode, promptly especially in the safe mode with this first memory block be in be connected in or visit this first memory block.In second operational mode, two performance elements are only visited second memory block of distributing to two performance elements or are in this second memory block and are connected.
Eligibly, supervising device, especially switching device shifter itself is set so now, makes and monitor, in corresponding operational mode, only visiting corresponding memory block, or have the corresponding connection of leading to the memory block.That is to say in second operational mode, analytical equipment is only visited second memory block, and do not visit first memory block, and only in first operational mode, realize to corresponding first memory block rather than to the visit of second memory block, this is checked by above-mentioned supervising device, and with may corresponding fault reaction, such as fault-signal, emergency operating or disconnect and approving.
In the case, in the memory module of separating, be provided with in described three memory blocks each, i.e. at least two first memory blocks and second memory block, make that at least three memory modules are arranged is available on processor unit.At this, eligibly that security requirement is high program leaves in first memory block respectively, and the program that security requirement is not high leaves in second memory block, and the storage address given in advance that wherein has the relevant described triggering function of switching eligibly is comprised in second memory block.
If processor unit is provided with clear and definite comparison means in order to compare the state of performance element in first operational mode, and this comparison means only works in first operational mode, and it is inoperative when carrying out the transition to second operational mode, make and do not compare and therefore do not realize the fault reaction that may bring out then to produce another advantage not high in service of nonredundant security requirement.
Draw other advantage and favourable expansion scheme by the feature of claim and the content of instructions and accompanying drawing.
Description of drawings
Below set forth the present invention in more detail by the figure shown in the accompanying drawings.Wherein:
Fig. 1 has showed the processor unit of the present invention with at least two performance elements and nextport hardware component NextPort of the present invention,
Fig. 2 has disclosed the switching from the safe mode to the efficiency mode, and
Fig. 3 shows the switching from the efficiency mode to the safe mode.
Embodiment
In control is used, especially such as engine control, braking control or even turn in the field of automobile control with transmission or the like, but equally in the picture commercial Application of robotization, or in machine tool field, the general existence for security reasons requires redundant software task or the program of carrying out, so that the appearance of identification mistake.But the high application of this security requirement also has even allows the software ingredient or the program of mistake except the high program of these security requirements, because they are optional or therefore do not comprised for the providing of the high function itself of security requirement, but additional function, especially comfortable function only are provided.For security reasons wish redundant execution, be unworthy pursuing the hardware of preparing redundancy for the cost reason.According to the present invention, the switching by the optimization between at least two kinds of operational modes of processor unit solves this problem, as illustrated aspect the advantage, and following will the elaboration in more detail.
Therefore, below illustrate the present invention the high system of security requirement, for example such as brake, turn to, application in the system that the vehicle of transmission or engine is intrinsic.At this, the processor unit of the present invention of system is made up of the processor unit 100 that according to the dual core architecture of Fig. 1, promptly has two performance elements 101 and 102 (CPU1 and CPU2) at least.In this example, give respectively two performance elements 101 and 102, be that CPU1 and CPU2 have distributed the working storage 110 or 111 that is also referred to as RAM1 and RAM2.Two performance elements 101 with 102 with comparison means, be that comparer 170 is connected.Each performance element have in addition lead to switching device shifter, be the connection of mode selector 130 or 131, comparison module, be that comparison means 170 also has and being connected of this mode selector 130 or 131.Each volatibility working storage 110 or 111 and switching device shifter 130 or 131 be connected with each one first memory storage 150 or 151 and second memory storage 180 by bus 140 or 141 respectively.
Adopt two operating systems in this embodiment, one is used for high program of security requirement or task, and one is used for not high program of security requirement or task.For example OSEKtimeOS is used as the operating system of the high program of security requirement, and for example with the operating system of OSEK OS as the not high task of security requirement.
As already mentioned, application software is divided into high program of security requirement and the not high program of security requirement.Being classified as all not high programs of security requirement or task allows to lose efficacy, mistake is arranged be performed or be not performed fully.Not entail dangers to total system or environment thus.Only just can move total system safely by being classified as high program of security requirement or task.But have following possibility, promptly as long as only carry out operation by security requirement high task or program, this operation will cause the mass loss of whole functional, but that described whole functional has been classified as in tolerance that can be given in advance is tolerable.
Two performance elements 101 and 102, just two CPU, be CPU1 with CPU2 on carry out redundantly security relevant, be high task of security requirement or program.At this, in first operating system, here be these programs of carrying out under the control of OSEKtime OS.Be two parts with nonvolatile storage shown in Fig. 1 150 or 151 multiplications for this reason, make to have two first memory blocks 150 and 151 corresponding to two performance elements.Program that security requirement is high or task doubly, be to be arranged in these first memory blocks redundantly.Be that in the high task of security requirement each is positioned in the memory block 150 on the one hand, and be positioned on the other hand in the memory block 151.In the case, it is high especially first operating system itself can be categorized as security requirement, and therefore leaves in equally in two memory blocks.Promptly in our example, operating system OSEKtime OS leaves in the memory block 150 respectively on the one hand, and leaves on the other hand in the memory block 151.In the case, in a kind of special embodiment, these two first memory blocks are implemented as independently non-volatile memory module ROM1 or ROM2 respectively, and these memory modules ROM1 or ROM2 also may be implemented as ROM, PROM, EPROM, EEPROM, flash EPROM or the like.
At this, not forcibly to require dual high program of security requirement or the task deposited.Also can ensure program or the task that these security requirements are high by adopting ECC sign indicating number (error recovery sign indicating number).This method that is used in storer identification mistake is diversified, wherein basic premise be utilize fault identification sign indicating number or error recovery sign indicating number, promptly signature (Signatur) ensures.Under the simplest situation, this signature can only be made up of signature bit, for example parity bit.On the other hand, also can be or also can ensure by realizing such as the more complicated ECC sign indicating number of Hamming code or the like by the more complicated ED sign indicating number (error detection occurs) of picture Berger sign indicating number or Bose-Lin sign indicating number or the like, so that can realize more reliable fault identification by corresponding figure place.But also can be for example with (permanent wiring or form of software) generator form as code generator, so that distribute the desirable code pattern of random length for the input pattern of determining of the position in the address realm.Therefore, especially can guarantee data security in the storer, and avoid dual and deposit by calibration function.Still in two performance elements, realize the execution of the redundancy of the program that security requirement is high, disclose kernel, be the mistake in the performance element by comparing consistance according to the present invention thus, wherein, opposite with Fig. 1 for this situation of the present invention, only need one first memory block.
In order to raise the efficiency, non-safety program relevant or that security requirement is high or task at two performance elements, be to calculate dispersedly on the CPU, and in corresponding child-operation system, promptly here implement under the control of OSEK subsystem.Therefore especially move independently operating system on each in two performance elements, be independent O SEK system here.Not high second memory block 180 that program or task were positioned at of security requirement exists singlely.It is used by two performance elements 101 or 102, or visits it by two performance elements 101 or 102.In a kind of special form of implementation, this second memory block also can be constructed to independently non-volatile memory module ROM3, and is arranged to ROM, PROM, EPROM, EEPROM, flash EPROM or the like.
At this, can construct memory block, i.e. first memory block and second memory block like this, make and for example constructing these first memory blocks or this first memory block (under the situation that ECC ensures) between O that relates to the address and the X, and construct second memory block by the X+1 to Y that relates to the address equally.In addition, from the first dual memory block, wherein as former the elaboration, also only unique first memory block that is ensured can obtain to use.So such as already explained, first memory block of O to X just in time exists in one first memory block respectively doubly.At this, each first memory block is distributed to a performance element particularly.
In first operational mode, be here in this example in safe mode, on two performance elements, i.e. redundant ground and especially synchronously carry out high program of security requirement or task on two CPU 101 and 102.At comparison means, be in the comparer 170, mutual CPU state more separately.At this, can give the program phase of determining with the state assignment of determining, wherein as long as these states of determining by temporary, and for example can be assigned with by sign clearly, these states of determining just can be in the not high mode of time requirement, promptly in that the moment is being compared arbitrarily.But in the preferred case, not only redundant ground but also synchronously carry out high program of security requirement or task, making is in operation can directly carry out the comparison of the state separately of performance element.So correspondingly from first memory block of being distributed separately 150 or 151, load and carry out new instruction and/or data.In comparer 170, check the consistance of CPU state, wherein when the state that should meet is inconsistent, identify mistake.React as mistake, can carry out mistake demonstration on the one hand about the corresponding system that uses processor unit, and the mistake that can look like emergency operating is on the other hand reacted, and just for example utilizes special program and/or the data that for this reason are provided with to move the system that comprises processor unit in the emergency operating that is ensured.At this, also can in the error analysis of proceeding, for example carry out m and get n test (n-aus m-Test), wherein n and m are natural numbers, and n 〉=2, and m＞n＞m/2, and perhaps k gets 1 code, and wherein k is corresponding to＞1 natural number.If for example clearly performance element has been identified as mistake by such test, then also can carry out the shutoff of this performance element and the emergency operating of remaining unit as other mistake reaction, maybe will there be the performance element of mistake to switch in the emergency operating.
In safe mode or usually in first operational mode, allow performance element only to visit address or data in first memory block.Be that corresponding performance element only allows visit especially to distribute to its first memory block in first operational mode.This by supervising device, especially switching device shifter or mode selector 130 131 or mode selector 130 and 131 in supervising device check.If go wrong in the case, then it is contemplated that and can stipulate aforesaid, about the comparable mistake reaction of the comparison mistake when the CPU state consistency.That is to say, but also it is contemplated that and can stipulate, this situation at first operational mode, switching device shifter, promptly be the connection in first memory block 150 or 151 of mode selector 130 or 131 under being established to respectively via bus 140 or 141 here, or monitor corresponding access violations.
In second operational mode of this embodiment, carry out not high program or the task of security requirement.At two performance elements, be that CPU 1 and 2 (101,102) goes up the different not high program of security requirement of operation.For example be used for second operational mode operating system itself, be that the OSEK subsystem also belongs to this.Therefore two performance elements or CPU share non-volatile second memory block that can construct like that as mentioned previously.But give each CPU distributing independent volatibility working storage RAM1 and RAM2, promptly 110 or 111.Because the not high program of corresponding this security requirement is not or not all by dual enforcement, so exist two performance elements at least in theory because of the release of the waiting for resource possibility of blocking-up mutually.Resist this situation on performance element 101 and 102 by suitably, for example task or program being assigned to according to scheduler program.At this, other measure, also be possible such as the visit that replaces or visit of being assigned with priority according to corresponding program or the like.In this second operational mode, promptly in the efficiency mode of embodiment according to us, do not allow to visit the address in first memory block.
Here, perhaps verifying attachment is separately implemented in mode selector also by verifying attachment, especially test by switching device shifter, mode selector.Here, be to identify in second operational mode under the situation of visit of mistake, also can introduce corresponding mistake reaction.At this, it is contemplated that on the one hand also can the mistake reaction corresponding to first operational mode given in advance.Perhaps even the demanding memory block of access security especially therefore this be suitable, because under the situation of the visit that mistake is arranged.This can realize in the following manner on the one hand, promptly only in second operational mode, set up the connection of leading to second memory block, and break the connection of leading to first memory block in this operational mode, or stop visit first memory block separately and only allow to enter second memory block.
Now in Fig. 2 and 3, at length set forth the switching between the operational mode once more.
For from first operational mode, promptly the safe mode here enters second operational mode, i.e. here efficiency mode or performance mode, needs visit address given in advance or that indicated, realizes being converted to second operational mode thus.In the case, this address of indicating may occur in first memory block or correspondingly carry from the outside when program is carried out.Promptly in first operational mode or safe mode, allow only to visit address or program in first memory block; If then there is the mistake of the corresponding mistake reaction with possibility as mentioned above in visit another address in second memory block for example in this safe mode.This is illustrated in Fig. 2 once more.In square frame 200, two performance elements 101 and 102 are in first operational mode, are in the safe mode.To inquire 210 checks, whether the address of next instruction equals the trigger address of the switching address indicated accordingly.If situation is not that so two processing units keep in first operational mode, and therefore visits first memory block 150,151 respectively.Yet, if the address of next instruction and/or data corresponding to the trigger address, is implemented to second operational mode in square frame 220, be switching or the conversion in efficient or the performance mode.In addition, each performance element obtains the address in second memory block at this moment, in the execution that should continue on this address in second operational mode.Turn-off comparing unit or comparison means 170 in the case, also promptly make it inoperative (forbidding).Therefore, first processing unit 101 is in second operational mode in square frame 230, and second processing unit 102 is in second operational mode equally, is in the performance mode in square frame 231.That is to say that in this concrete example, the unique possibility in from the safe mode to the performance mode for example is to call special OSEKtime task T
Trigger, such as the ttidle task of OSEKtime operating system or be included in wherein the address that is marked as the trigger address, especially this program part or the start address of this task.Especially when two performance elements are synchronously worked, be necessary in two CPU, to realize simultaneously that this calls.At this, the T as ttidle just now
TriggerTask for example is the calling of OSEK scheduler program that is arranged in second memory block 180.For example at switching device, be in the mode selector 130,131, should be adjusted into the trigger address in corresponding address, so that be transformed in the efficiency mode.As described, this in square frame 210, promptly just at mode selector, be to be examined in the switching device shifter.Therefore just till being transformed in the safe mode again, following address visit only still allows in ROM district 180, is to carry out in non-volatile second memory block.
In Fig. 3, show from efficiency mode now, be that performance mode especially turns back to first operational mode, is switching or the conversion the safe mode.In square frame 300 performance element 101, be that CPU1 is in second operational mode, is in the performance mode.Similarly, in square frame 310, second performance element 102 just is in this efficiency mode, promptly in second operational mode of this embodiment.In square frame 320 or square frame 321, be that now each performance element triggers interrupt request, promptly interrupts, by these two performance elements 101 of interruptions realization and 102 in square frame 330 to first operational mode, be the switching in the safe mode.Reclose comparison means this moment, be comparer 170, and subsequently in square frame 340 two performance elements rerun in safe mode, promptly in first operational mode.In the case, interrupt request can be on the one hand by time conditions, be that timer interrupts triggering, or trigger by status condition or event condition.This means,, generate the interrupt request of the first operating system OSEKtime in order to be transformed into the safe mode from efficiency mode.In two CPU, this timer interruption of the OSEKtime operating system higher with respect to OSEK operating system priority is programmed in the same manner, because on two CPU, move identical OSEKtime system.Especially under the situation of synchronous operation OSEKtime system, interrupt, be that interrupt request arrives two CPU simultaneously.As described, the OSEKtime scheduler program interrupts therefore having according to the rules very high, especially the highest priority.Under synchronous situation, correspondingly carry out two interrupt request therewith simultaneously.Such as already mentioned, along with the execution of these interrupt request, comparison means 170 works too again, promptly switch to first running status, be in the safe mode, and especially performance element moves again redundantly.
Except the timer of having mentioned interrupts, also can adopt state interrupt or event interrupt, so that realize the described operational mode conversion from second to first operational mode.In the case, definite state of performance element for example can trigger the interruption of high priority, so this interruption has validity for two performance elements.This for example can be the state that the program owing to carrying out among the ROM 180 among the CPU generates, and this CPU triggers the interrupt request of this high priority, and this interrupt request also is applicable to the 2nd CPU.Incident, the incident of especially importing from the outside of processor unit equally also can trigger this interruption and therefore trigger the operational mode conversion.Preferably have first flexible program that timer interrupts, but it is contemplated that equally and so such as described state interrupt or event interrupt of demonstration.
Therefore be illustrated in the switching of optimizing between two kinds of operational modes of the processor unit with two integrated performance elements according to the present invention according to this task, wherein in view of the basic thought of theme of the present invention, specific embodiment can play nonrestrictive effect.
Claims (28)
1. processor unit with at least two performance elements, wherein include switching device shifter, can between at least two kinds of operational modes of described processor unit, switch by this switching device shifter, it is characterized in that, construct described switching device shifter like this, the feasible conversion that triggers in the following manner from first operational mode to second operational mode is promptly by described processor unit visit storage address given in advance.
2. according to the processor unit of claim 1, it is characterized in that, described first operational mode is equivalent to safe mode, carry out identical program at two performance elements described in this safe mode, and be provided with comparison means, the consistance of the state that the more described performance element of this comparison means is produced when carrying out identical program.
3. according to the processor unit of claim 2, it is characterized in that, construct described performance element like this, make these performance elements in described first operational mode, synchronously carry out identical program.
4. according to the processor unit of claim 1, have the memory block of at least three separation, wherein each performance element is in first memory block that is assigned to each performance element respectively and is connected in described first operational mode.
5. according to the processor unit of claim 1, have the memory block of at least two separation, wherein two performance elements only are in second memory block that is assigned to two performance elements and are connected in described second operational mode.
6. according to the processor unit of claim 1 and 5, it is characterized in that, should accessed storage address described given in advance be positioned in described second memory block.
7. according to the processor unit of claim 1, have the memory block of at least two separation, wherein two performance elements only are in first memory block that is assigned to two performance elements and are connected in described first operational mode.
8. according to the processor unit of claim 1 and 7, it is characterized in that described storage address given in advance is comprised in described first memory block as the trigger address, and should be comprised in described second memory block accessed back to back address.
9. according to the processor unit of claim 1 and 5, it is characterized in that, be provided with supervising device, especially switching device shifter, it is configured to monitoring like this, makes analytical equipment only be in described second memory block in described second operational mode and is connected.
10. according to the processor unit of claim 1 and 4, it is characterized in that, be provided with supervising device, especially switching device shifter, it is configured to monitoring like this, makes analytical equipment only be in described first memory block respectively in described first operational mode and is connected.
11. the processor unit according to claim 4 or 5 is characterized in that, each in the described memory block is set in the memory module of separation.
12. the processor unit according to claim 2 is characterized in that, makes described comparison means inoperative in the time of in carrying out the transition to described second operational mode that is equivalent to efficiency mode, and only carries out the comparison of described state in described first operational mode.
13. the processor unit according to claim 1 is characterized in that, includes interrupting device, constructs this interrupting device like this, makes this interrupting device can realize turning back in described first operational mode by interrupt request.
14. the processor unit according to claim 13 is characterized in that, triggers described interrupt request by time conditions.
15. the processor unit according to claim 13 is characterized in that, triggers described interrupt request by status condition.
16. be used for the method between at least two kinds of operational modes of processor unit, switched with at least two performance elements, it is characterized in that, trigger conversion in the following manner, promptly by described processor unit visit storage address given in advance from first operational mode to second operational mode.
17. the method according to claim 16 is characterized in that, described performance element is synchronously carried out identical program in described first operational mode.
18. method according to claim 16, it is characterized in that, in two kinds of operational modes, carry out different programs, wherein in described first operational mode, carry out the high program of security requirement redundantly, and in described second operational mode, carry out the not high program of security requirement by two performance elements.
19. the method according to claim 18 is characterized in that, the high program of described security requirement is left in first memory block that is assigned to described performance element respectively redundantly.
20. the method according to claim 18 is characterized in that, the not high program of described security requirement is stored in the second unique memory block, and two performance elements are only visited described second memory block in described second operational mode.
21. the method according to claim 16 is characterized in that, carries out the high program of security requirement in described first operational mode, and the consistance of the state that is relatively produced this moment redundantly.
22. the method according to claim 16 is characterized in that, only visits first memory block that is assigned to each performance element respectively at performance element described in described first operational mode.
23. according to the method for claim 16, have the memory block of at least two separation, wherein two performance elements are only visited first memory block that is assigned to two performance elements in described first operational mode.
24. the method according to claim 16 and 23 is characterized in that, described storage address given in advance is comprised in described first memory block as the trigger address, and should be comprised in described second memory block accessed back to back address.
25. the method according to claim 16 is characterized in that, two performance elements are only visited second memory block that is assigned to two performance elements in described second operational mode.
26. the method according to claim 16 and 25 is characterized in that, monitoring: analytical equipment is only visited described second memory block in described second operational mode.
27. the method according to claim 16 and 22 or 23 is characterized in that, monitoring: analytical equipment is only visited described first memory block in described first operational mode.
28. the method according to claim 16 is characterized in that, realizes switching from described second operational mode to described first operational mode wherein triggering described interrupt request by time conditions or status condition by interrupt request.
Applications Claiming Priority (3)
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| DE10328208 | 2003-06-24 | ||
| DE10328208.4 | 2003-06-24 | ||
| DE10332700.2 | 2003-07-18 |
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| CN1842763A true CN1842763A (en) | 2006-10-04 |
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| CNA2004800178282A Pending CN1842763A (en) | 2003-06-24 | 2004-06-22 | Method for switching between at least two operating modes of a processor unit and corresponding processor unit |
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| CN (1) | CN1842763A (en) |
| DE (1) | DE10332700A1 (en) |
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| CN101383689B (en) * | 2007-09-05 | 2013-03-13 | 西门子公司 | High availability communications system |
| CN103500316A (en) * | 2012-05-14 | 2014-01-08 | 英飞凌科技奥地利有限公司 | System and method for processing device with differentiated execution modes |
| CN105555638A (en) * | 2013-09-19 | 2016-05-04 | 西门子公司 | Software updating of non-critical components in dual safety-critical distributed systems |
| CN107944298A (en) * | 2012-08-21 | 2018-04-20 | 联想(北京)有限公司 | A kind of electronic equipment and the mode switching method applied to electronic equipment |
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| DE102005037233A1 (en) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Method and device for data processing |
| DE102005037244A1 (en) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Method and device for controlling a computer system having at least two execution units and at least two groups of internal states |
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| DE102005037219A1 (en) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Apparatus and method for storing data and / or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and / or instructions |
| DE102005053681A1 (en) * | 2005-11-10 | 2007-05-16 | Bosch Gmbh Robert | Method of using a memory |
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2003
- 2003-07-18 DE DE10332700A patent/DE10332700A1/en not_active Withdrawn
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2004
- 2004-06-22 CN CNA2004800178282A patent/CN1842763A/en active Pending
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| DE10332700A1 (en) | 2005-01-13 |
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