CN1841753A - Single layer polysilicon EEPROM - Google Patents

Single layer polysilicon EEPROM Download PDF

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Publication number
CN1841753A
CN1841753A CN 200510059536 CN200510059536A CN1841753A CN 1841753 A CN1841753 A CN 1841753A CN 200510059536 CN200510059536 CN 200510059536 CN 200510059536 A CN200510059536 A CN 200510059536A CN 1841753 A CN1841753 A CN 1841753A
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type
floating grid
pmos transistor
eeprom
voltage
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CN 200510059536
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CN100514656C (en
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彭迺真
黄水钦
李自强
王泉富
林松斌
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

The invention comprises a first PMOS transistor and a second PMOS transistor which form on a N-type trap of the P-type base, wherein the PMOS transistor comprises a float grid, a first P+ leakage electrode doping area and a first P+ source electrode doping area; the PMOS transistor comprises a grid and a second P+ source electrode doping area; the first P+ source electrode doping area is used as a leakage electrode of the second PMOS transistor. It also comprises a diode on the P-type base which comprises a P-type trop and a N+ type doping area; the floating grid is covered on the N-type trop and along to the upper side of the N+ type doping area; the connecting area of the floating grid covered P- type trop and the N+ type doping area is used as a snowslide decanting point.

Description

The single level polysilicon EEPROM (Electrically Erasable Programmable Read Only Memo)
Technical field
The present invention relates to a kind of single level polysilicon (single-poly) EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read Only Memory, be designated hereinafter simply as EEPROM), especially in regard to a kind of single level polysilicon EEPROM that improves electric erasing speed.
Background technology
EEPROM or quickflashing EEPROM (flash EEPROM) belong to nonvolatile memory, and it has to cut off the electricity supply still can possess the advantage of memory content, and has the function that repeatable read is gone into data, add transmission fast, so application is very extensive.In many information, communication and consumption electronic products, all nonvolatile memory is treated as necessary assembly.And along with small size portable electronic product personal digital assistant (personal digital assistant for example, PDA) or the demand of mobile phone increase day by day, (system on a chip, demand SOC) also promotes thereupon to include the embedded chip (embedded chip) of EEPROM and logical circuit or system combination chip simultaneously.For this reason, EEPROM certainly will write efficient, low cost and highdensity direction towards CMOS processing procedure compatibility, low power consumption, height in the future to be developed, and just can meet the demand of product in the future.
Fig. 1 is the generalized section of existing EEPROM unit 10.As shown in Figure 1, existing EEPROM unit 10 includes a NMOS structure 28 and a PMOS structure 30, and both separate by an insulation field oxide 24.NMOS structure 28 is formed in the P type substrate 12, includes one first floating grid (floating gate), 32, one N +A source doping region 14 and a N +Drain doping region 16.PMOS structure 30 is formed on the N type ion trap 18, includes one second floating grid 34, a P +A source doping region 2O and a P +Drain doping region 22.In addition, at next-door neighbour P +Source doping region 20 1 sides are implanted a heavy doping (heavily doped) N type passage Resistance (channel stop region) 38, and this N type passage Resistance 38 is positioned at the below of second floating grid 34.First floating grid 32 and second floating grid 34 also are connected by a floating grid lead 36, make first floating grid 32 and second floating grid 34 keep same potential.When first floating grid 32 produces corresponding current potential corresponding to a control-grid voltage, second floating grid 34 will have the current potential identical with first floating grid 32 owing to the connection of floating grid lead 36, and use attraction via P +The accelerated electron that exhaustion region produced of source doping region 20 and N type passage Resistance 38 and electronics is bound in second floating grid 34.
Existing EEPROM unit 10 has following shortcoming.At first, existing EEPROM unit 10 is made of a PMOS transistor 30 and a nmos pass transistor 28, and shared chip unit are is bigger; Secondly, existing EEPROM unit 10 needs extra N type passage Resistance 38; Moreover existing EEPROM unit 10 must be electrically connected first floating grid 32 and second floating grid 34 with floating grid lead 36; In addition, needing field oxide 24 between NMOS structure 28 and PMOS structure 30 isolates.As from the foregoing, it is excessive that existing EEPROM unit 10 consumes chip area, adds complex structure, increases processing procedure cost and degree of difficulty.
Summary of the invention
Main purpose of the present invention is to provide a kind of single level polysilicon EEPROM, and single level polysilicon EEPROM of the present invention has high electric erasing speed, simultaneously its manufacture method can with traditional cmos processing procedure compatibility.
For achieving the above object, in preferred embodiment of the present invention, disclose a kind of single level polysilicon EEPROM, included one the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor.Wherein a PMOS transistor and the 2nd PMOS transistor are formed at a N of a P type substrate -On the type trap, and a PMOS transistor includes a floating grid, one the one P +Drain doping region and one the one P +Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P +Source doping region, and the transistorized P of a PMOS +Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously.This single level polysilicon EEPROM also comprises a diode and is arranged in the substrate of P type, and wherein diode includes a P -Type trap and one is arranged at P -N in the type trap +The type doped region, and floating grid system is covered in N -On the type trap and extend to N +Type doped region top, the wherein P that floating grid covered -Type trap and N +The join domain of type doped region is as a snowslide decanting point (avalanche injection point).
According to another preferred embodiment of the present invention, disclosed a kind of single level polysilicon EEPROM, include one the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor.Wherein a PMOS transistor and the 2nd PMOS transistor are formed at a N of a P type substrate -On the type trap, and a PMOS transistor includes a floating grid, one the one P +Drain doping region and one the one P +Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P +Source doping region, and the transistorized P of a PMOS +Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously.This single level polysilicon EEPROM also comprises a diode and a P +The type retaining ring, wherein diode is arranged in the substrate of P type, includes a P -Type trap and one is arranged at P -N in the type trap +The type doped region, and floating grid system is covered in N -On the type trap and extend to N +Type doped region top, the wherein P that floating grid covered -Type trap and N +The join domain of type doped region is as a snowslide decanting point.P +The type retaining ring is positioned at P -In the type trap, and floating grid pastern branch is covered in P +On the type retaining ring, to produce a P +Interface wherein puts on P in the floating grid below +The voltage of type retaining ring is same as and puts on P -The voltage of type trap.
Because the present invention is the P that utilizes floating grid to cover -Type trap and N +The join domain of type doped region forms avalanche breakdown (avalanche breakdown) and injects floating grid to produce hot hole, and neutralization is trapped in the electronics of floating grid, then utilize Fule nuohan tunnel effect (FN tunneling) that electronics is pulled out floating grid and wipe with execution, therefore single level polysilicon EEPROM of the present invention has the following advantages:
1. the present invention uses low-voltage to carry out erase operation, its manufacture method can with traditional logic (logic) processing procedure compatibility, and do not need extra fabrication steps, reduced cost of manufacture.
2. the present invention utilizes the snowslide hot hole to inject mechanism, and its service speed significantly is better than the Fule nuohan tunnel effect, therefore can reduce the operation cycle of write/erase, and reduces testing cost.
3. the present invention also comprises a P -The type trap is positioned at floating grid below, when carrying out electricity when wiping, can apply a negative electricity and be pressed on P -The type trap is with the increase pressure drop, and then reinforcement snowslide hot hole injects mechanism and Fule nuohan tunnel effect.
4. the present invention also comprises a P +The type retaining ring is positioned at the P of floating grid below -In the type trap, can add the speed that forceful electric power wipes and increase floating grid and P +Pressure drop between the type retaining ring so can increase the allowance of processing procedure.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended graphic only for reference and explanation usefulness is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the generalized section of existing EEPROM unit.
Fig. 2 is the part top view according to the single level polysilicon EEPROM layout of the present invention's first preferred embodiment.
Fig. 3 is along the generalized section of tangent line AA ' among Fig. 2.
Fig. 4 is along the generalized section of tangent line BB ' among Fig. 2.
Fig. 5 is the corresponding circuits figure of single level polysilicon EEPROM unit among Fig. 3.
Fig. 6 represents to write the operational instances schematic diagram of " 1 ".
Fig. 7 is the part top view according to the single level polysilicon EEPROM layout of the present invention's second preferred embodiment.
Fig. 8 is along the generalized section of tangent line CC ' among Fig. 7.
The reference numeral explanation
The 12 P type substrates of 10 single level polysilicon EEPROM unit
14 N +Source doping region 16 N +Drain doping region
18 N type ion traps, 20 P +Source doping region
22 P +Drain doping region 24 insulation field oxides
28 NMOS structures, 30 PMOS structures
32 first floating grids, 34 second floating grids
36 floating grid leads, 38 N type passage Resistance
100 single level polysilicon EEPROM unit 102 a PMOS transistor
The 106 P type substrates of 104 the 2nd PMOS transistors
108 N -Type trap 110 floating grids
112 the one P +Drain doping region 114 P +Source doping region
116 grids 118 the 2nd P +Source doping region
120 contact plungers, 122 source electrode lines
130 single level polysilicon EEPROM unit, 140 diodes
142 P -Type trap 144 N +The type doped region
146 contact plungers, 148 P +The type doped region
150 contact plungers, 152 floating grid oxide layers
154 gate oxides, 156 bit lines
158 dielectric layers 160 the 3rd PMOS transistor
162 floating grids, 164 floating grid oxide layers
166 shallow isolating trough, 168 shallow isolating trough
170 shallow isolating trough, 172 P -Channel region
200 single level polysilicon EEPROM unit 202 a PMOS transistor
The 206 P type substrates of 204 the 2nd PMOS transistors
208 N -Type trap 210 floating grids
212 the one P +Drain doping region 214 P +Source doping region
216 grids 218 the 2nd P +Source doping region
220 contact plungers, 222 source electrode lines
230 diodes, 232 P -The type trap
234 N +Type doped region 236 contact plungers
238 P + Type retaining ring 240 the 3rd PMOS transistor
242 dielectric layers, 244 floating grid oxide layers
246 floating grids, 248 floating grid oxide layers
250 shallow isolating trough, 252 shallow isolating trough
254 shallow isolating trough, 256 shallow isolating trough
258 shallow isolating trough, 260 P -Channel region
Embodiment
Please refer to Fig. 2, Fig. 2 is the part top view according to the single level polysilicon EEPROM layout of the present invention's first preferred embodiment.As shown in Figure 2, according to first preferred embodiment of the present invention, single level polysilicon EEPROM unit 100 includes one the one PMOS transistor 102 and one the 2nd PMOS transistor 104 is serially connected with a PMOS transistor 102, and a PMOS transistor 102 and the 2nd PMOS transistor 104 are formed at a N of a P type substrate 106 respectively -On the type trap 108 (zone shown in dotted line).Wherein, a PMOS transistor 102 includes a floating grid 110, one the one P + Drain doping region 112 and one the one P +Source doping region 114.The 2nd PMOS transistor 104 includes a grid 116 and one the 2nd P + Source doping region 118, and a P of a PMOS transistor 102 +Source doping region 114 is used as the drain electrode of the 2nd PMOS transistor 104 simultaneously.
Floating grid of the present invention 110 is formed by single level polysilicon, and its top there is no and is provided with any control grid (control gate).The one P + Drain doping region 112 is electrically connected the 2nd P via a contact plunger 120 with a bit line (figure does not show) + Source doping region 118 is electrically connected one source pole line (sourceline) 122.In first preferred embodiment of the present invention, source electrode line 122 is a P +Doped region is with the 2nd P + Source doping region 118 forms in same implanting ions step.Also show the single level polysilicon EEPROM unit 130 of a similar among Fig. 2 in single level polysilicon EEPROM unit 100.
Single level polysilicon EEPROM of the present invention unit 100 also includes a diode 140 and is formed in the P type substrate 106, and in abutting connection with floating grid 110.Wherein diode 140 includes a P -Type trap 142 and one is arranged at P -N in the type trap 142 +Type doped region 144.N +Type doped region 144 is via a contact plunger 146 external N +Type doped region voltage (V N +).P -Also comprise a P in the type trap 142 +Type doped region 148 and via a contact plunger 150 external voltages, P simultaneously -Type trap 142 has and P +The voltage that type doped region 148 is identical is Gu this voltage is P in what this claimed -Type trap voltage (P -Well voltage, V PW).
The erase operation of single level polysilicon EEPROM of the present invention unit 100 is to utilize N +The P that is covered by floating grid 110 in edge FN effect between type doped region 144 and the floating grid 122 and the diode 140 - Type trap 142 and N +Avalanche breakdown between the join domain of type doped region 144 (avalanchebreakdown) is carried out, wherein the P that covered of floating grid 110 - Type trap 142 and N +The join domain of type doped region 144 is as a snowslide decanting point (avalanche injection point), and its detailed operation sequence is held the back explanation.Be noted that, in first preferred embodiment of the present invention, N +The implantation of type doped region 144 is to carry out after floating grid 110 definition is finished, therefore, in essence below floating grid 110 can't with N +Type doped region 144 overlaps.If have, also be because N +Type doped region 144 causes because of slight spread that hot processing procedure produces after implantation.Because floating grid 110 must be in abutting connection with N +Type doped region 144, so floating grid 110 needs extension to cover to N +Type doped region 144.In addition, between floating grid 110 and gate pole 116, do not need lead and link to each other, keep same potential.
Please refer to Fig. 3, Fig. 3 is along the generalized section of tangent line AA ' among Fig. 2.As shown in Figure 3, a PMOS transistor 102 is serially connected with the 2nd PMOS transistor 104.Wherein, a PMOS transistor 102 includes floating grid 110, a P + Drain doping region 112, a P +A source doping region 114 and a floating grid oxide layer 152 are located at floating grid 110 belows, and the 2nd PMOS transistor 104 includes grid 116, a gate oxide 154 and the 2nd P + Source doping region 118, and via a P +Source doping region 114 is connected with a PMOS transistor 102.In addition, a P + Drain doping region 112 is electrically connected with a bit line 156 via contact plunger 120, and contact plunger 120 is formed in the dielectric layer 158, for example BPSG, PSG, silicon dioxide or other similar dielectric material, and bit line 156 is formed on the dielectric layer 158.Floating grid oxide layer 152 of the present invention and gate oxide 154 can be identical with the thickness of grid oxide layer in the logical circuit, or optionally increase thickness.Whichsoever, single level polysilicon EEPROM of the present invention all can be compatible with traditional logic (logic) processing procedure.
Please refer to Fig. 4, Fig. 4 is along the generalized section of tangent line BB ' among Fig. 2.As shown in Figure 4, a PMOS transistor 102 and one the 3rd PMOS transistor 160 are arranged in dielectric layer 158, and wherein the 3rd PMOS transistor 160 also includes a floating grid 162 and a floating grid oxide layer 164.Floating grid 110 and 162 all is covered in N -On the type trap 108 and extend to N +Type doped region 144 tops, wherein N +Type doped region 144 is positioned at P -In the type trap 142.Single level polysilicon EEPROM of the present invention also includes a plurality of shallow isolating trough (STI) 166,168 and 170 so that P -Type trap 142 and N +Type doped region 144 not with a P of a PMOS transistor 102 -One P of type channel region 172 and the 3rd PMOS transistor 160 -Type channel region (figure does not show) overlaps mutually.
See also Fig. 5 and Fig. 3, Fig. 5 is the corresponding circuits figure of single level polysilicon EEPROM unit 100 among Fig. 3.As shown in Figure 5, during operation, a P of a PMOS transistor 102 + Drain doping region 112 imposes a bit-line voltage (bit line voltage, V BL), floating grid 110 does not impose any voltage, that is keeps floating state.N -Type trap 108 imposes a N -Type trap voltage (N -Well voltage, V NW).The 2nd PMOS transistor 104 is used as one and is selected transistor when operation, its grid 116, and (select gate SG), imposes one and selects grid voltage (select gate voltage, V maybe can be called the selection grid SG) or word line voltages (word line voltage, V WL), its 2nd P + Source doping region 118 imposes one source pole line voltage (source line voltage, V SL).
According to shown in the table 1, the method for operation of single level polysilicon EEPROM of the present invention is described below.
Operation table V WL V BL V N + V SL V NW V PW/PC
Selected WL Unselected WL Selected BL Unselected BL
Prefaceization 1 0V 5～7V 0V 5～7V 0V 5～7V 5～7V 0V
0 0V 5～7V 5～7V 5～7V 0V 5～7V 5～7V 0V
Read 0V 3.3V 1.8V 3.3V 3.3V 3.3V 3.3V 0V
Wipe (1) 0～2V -4～-7V 4～7V Floating 0V -4～-7V
Wipe (2) -4～-7V 0V～2V -4～-7V 4～7V -4～-7V 0V -4～-7V
Table 1
See Table 1 first row, when carrying out a coding or programming operations (is example to write data " 1 "), word line voltages V WLBe a low level voltage, for example import V WL=0V.Bit-line voltage V BLBe a level and word line voltages V WLIdentical voltage, that is V BL=0V.Non-selected character line then imposes a level and source electrode line voltage V SLIdentical voltage, that is V WL (un-selected)=5～7V.Non-selected bit line then imposes a level and source electrode line voltage V SLIdentical voltage, that is V BL (un-selected)=5～7V.Floating grid 122 keeps suspended state.Source electrode line voltage V SLBe a high level voltage, for example import V SL=5～7V.N -Type trap voltage V NWAlso be the voltage that a level is relatively higher than word line voltages, for example import V NW=5～7V.N +Type doped region voltage V N +With P -Type trap voltage V PWBe a low level voltage, for example import V N +=0V and V PW=0V.See Table 1 secondary series,, choose and the non-selected bit-line voltage V that arrives as if being example to write data " 0 " BLBe all a level and be higher than word line voltages V WLVoltage, for example import V BL=5～7V, other condition is the same.
See also Fig. 6, Fig. 6 represents to write the operational instances schematic diagram of " 1 ".As shown in Figure 6, be example: word line voltages V with following operating condition WL=0V, bit-line voltage V BL=0V, floating grid 110 keeps suspended state, source electrode line voltage V SL=5V, N -Type trap voltage V NW=5V.Under above-mentioned operating condition, because floating grid 110 can obtain one first induced voltage by capacitance coupling effect, this first induced voltage is with respect to N -Type trap voltage V NWFew 1～2V, and with the P of floating grid 110 belows -Type passage 172 is opened, and injects mechanism (channel hot electron injection) by channel hot electron, and hot electron can be via the P that opens -Type passage 172, tunnelling are crossed floating grid oxide layer 152, and are caught to sink in floating grid 110.
See Table 1 the 3rd row, when carrying out a read operation, the word line voltages V that chooses WLBe a low level voltage, for example input voltage is 0V, the non-selected word line voltages V that arrives WLBe a higher level voltage, for example input voltage is 3.3V.The bit-line voltage V that chooses BLBe a low level voltage, for example input voltage is 1.8V, the non-selected bit-line voltage V that arrives BLWith the non-selected word line voltages V that arrives WLBe a higher level voltage, for example input voltage is 3.3V.N +Type doped region voltage V N +, source electrode line voltage V SLAnd N -Type trap voltage V NWAll with the non-selected word line voltages V that arrives WLBe a higher level voltage, for example input voltage is 3.3V.P -Type trap voltage V PWBe a low level voltage, for example input voltage is 0V.
See Table 1 the 4th row, when (Erase) operation is wiped in execution one, word line voltages V WLBe a low level voltage, for example input voltage is 0～2V.Bit-line voltage V BLBe a low level voltage, for example input voltage be-4～-7V.Source electrode line voltage V SLKeep suspended state.N -Type trap voltage V NWBe a low level voltage, for example input voltage is 0V.N +Type doped region voltage V N +Then be a high level voltage, for example input voltage is 4～7V, and P -Type trap voltage V PWIt is a low level voltage, for example input voltage be-4～-7V, therefore bring out an avalanche breakdown (avalanche breakdown) and produce hot hole, and make floating grid 110 obtain negative second induced voltage to attract the hot hole in electric hole and the duplet by a capacitance coupling effect, the electronics that can make floating grid by the tunnelling mode from N +Type doped region 144 is pulled out.P wherein -Type trap voltage V PWCan be different from bit-line voltage V BL, this bit-line voltage V BLPromptly put on a P +The voltage of drain doping region 112.It should be noted that to please refer to table 1 the 5th row, also can when erase operation, apply one source pole line voltage V SLIn the 2nd P +Source doping region 118, for example input voltage be-4～-7V, and open the 2nd PMOS transistor 104 simultaneously, so that a P +Source doping region 114 also has this source electrode line voltage V SL, to strengthen second induced voltage of floating grid, other condition is the same.
Fig. 7 is the part top view according to the single level polysilicon EEPROM layout of the present invention's second preferred embodiment.The place that second preferred embodiment of the present invention is different from first preferred embodiment is, also includes a P in second preferred embodiment + Type retaining ring 238 is positioned at P -In the type trap 232, and floating grid 210 is that part is covered in P +On the type retaining ring 238, to produce a P +Interface wherein puts on P in floating grid 210 belows +The voltage of type retaining ring 238 is same as and puts on P -The voltage of type trap 232.
As shown in Figure 7, according to second preferred embodiment of the present invention, single level polysilicon EEPROM unit 200 includes one the one PMOS transistor 202 and one the 2nd PMOS transistor 204 is serially connected with a PMOS transistor 202.The one PMOS transistor 202 and the 2nd PMOS transistor 204 are formed at a N of a P type substrate 206 -On the type trap 208 (zone shown in dotted line).The one PMOS transistor 202 includes a floating grid 210, one the one P +Drain doping region 212 and one the one P +Source doping region 214.The 2nd PMOS transistor 204 includes a grid 216 and one the 2nd P +Source doping region 218, and a P of a PMOS transistor 202 +Source doping region 214 is used as the drain electrode of the 2nd PMOS transistor 204 simultaneously.Floating grid 210 is formed by single level polysilicon, and its top there is no and is provided with control electrode.The one P +Drain doping region 212 is electrically connected the 2nd P via a contact plunger 220 with a bit line (figure does not show) +Source doping region 218 is electrically connected one source pole line (source line) 222.Source electrode line 222 is a P +Doped region is with the 2nd P +Source doping region 218 forms in same implanting ions step.
The single level polysilicon EEPROM unit 200 of second embodiment of the invention also includes a diode 230 and is formed in the P type substrate 206, and in abutting connection with floating grid 210.Wherein diode 230 includes a P -Type trap 232 and one is arranged at P -N in the type trap 232 +Type doped region 234.N +Type doped region 234 is via a contact plunger 236 external N +Type doped region voltage (V NW), and P -Also comprise a P in the type trap 232 + Type retaining ring 238 and via a contact plunger 240 external P -Type trap voltage (V PW), P-type trap voltage (V PW) and P +Type retaining ring voltage (V PG) identical.
Please refer to Fig. 8, Fig. 8 is along the generalized section of tangent line CC ' among Fig. 7.As shown in Figure 8, the one PMOS transistor 202 and one the 3rd PMOS transistor 240 are arranged in a dielectric layer 242, wherein a PMOS transistor 210 comprises floating grid 210 and a floating grid oxide layer 244, the three PMOS transistors 240 include a floating grid 246 and a floating grid oxide layer 248.Floating grid 210 and 246 all is covered in N -On the type trap 208 and extend to N +Type doped region 234 and P + Type retaining ring 238 tops, wherein N +Type doped region 234 and P + Type retaining ring 238 is to be positioned at P -In the type trap 232, and floating grid 210 and 246 P that covered - Type trap 232 and N +The join domain of type doped region 234 is as a snowslide decanting point.The single level polysilicon EEPROM of second embodiment of the invention also includes a plurality of shallow isolating trough 250,252,254,256 and 258 so that P + Type retaining ring 238, P -Type trap 232 and N +Type doped region 234 not with a P of a PMOS transistor 202 -One P of type channel region 260 and the 3rd PMOS transistor 240 -Type channel region (figure does not show) overlaps mutually.
The operation of the single level polysilicon EEPROM unit 200 of second embodiment is same as the single level polysilicon EEPROM unit 100 of operation first embodiment, does not add to give unnecessary details at this.It should be noted that applying a positive electricity is pressed on N +Type doped region 234 also applies the P that a negative electricity is pressed on floating grid 210 belows simultaneously +Type retaining ring 238 and P -Type trap 232 bringing out an avalanche breakdown, and applies a negative electricity and is pressed on a P +Drain doping region 212 can make floating grid 210 obtain a negative induced voltage of strengthening and increase floating grid 210 and P by a capacitance coupling effect +The pressure drop that the type retaining ring is 238 is injected to attract the hot hole of electric hole and duplet to strengthen the snowslide hot hole, the electronics that can make floating grid 210 by the tunnelling mode from N +Type doped region 234 is pulled out, and so can add the speed that forceful electric power wipes and increase the allowance of processing procedure.Wherein put on P +The negative voltage of type retaining ring 238 can be different from and puts on a P +The negative voltage of drain doping region 212.
Compared to prior art, the present invention is the P that utilizes floating grid to cover -Type trap and N +The join domain of type doped region forms avalanche breakdown (avalanche breakdown) and injects floating grid to produce hot hole, and neutralization is trapped in the electronics of floating grid, then utilize Fule nuohan tunnel effect (FN tunneling) that electronics is pulled out floating grid and wipe with execution, therefore single level polysilicon EEPROM of the present invention has the following advantages:
1. the present invention uses low-voltage to carry out erase operation, its manufacture method can with traditional logic (logic) processing procedure compatibility, and do not need extra fabrication steps, reduced cost of manufacture.
2. the present invention utilizes the snowslide hot hole to inject mechanism, and its service speed significantly is better than the Fule nuohan tunnel effect, therefore can reduce the operation cycle of write/erase, and reduces testing cost.
3. the present invention also comprises a P -The type trap is positioned at floating grid below, when carrying out electricity when wiping, can apply a negative electricity and be pressed on P -The type trap is with the increase pressure drop, and then reinforcement snowslide hot hole injects mechanism and Fule nuohan tunnel effect.
4. the present invention also comprises a P +The type retaining ring is positioned at the P of floating grid below -In the type trap, can add the speed that forceful electric power wipes and increase floating grid and P +Pressure drop between the type retaining ring so can increase the allowance of processing procedure.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (16)

1. single level polysilicon EEPROM (Electrically Erasable Programmable Read Only Memo) includes:
One the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor, wherein a PMOS transistor and the 2nd PMOS transistor are formed at a N of a P type substrate -On the type trap, a PMOS transistor includes a floating grid, one the one P +Drain doping region and one the one P +Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P +Source doping region, and the transistorized P of a PMOS +Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously; And
One diode is arranged in this P type substrate, and wherein this diode includes a P -Type trap and one is arranged at this P -N in the type trap +The type doped region, and this floating grid is covered in this N -On the type trap and extend to this N +Type doped region top, this P that this floating grid covered -Type trap and this N +The join domain of type doped region is as a snowslide decanting point.
2. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 1, wherein this floating grid top there is no a control grid is set.
3. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 1, wherein this P -Type trap and this N +The type doped region not with the transistorized P of a PMOS -The type channel region overlaps mutually.
4. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 3 wherein when this EEPROM (Electrically Erasable Programmable Read Only Memo) of operation, applies a drain voltage in a P +Drain doping region, and open the 2nd PMOS transistor simultaneously so that a P +Source doping region obtains one source pole line voltage, this floating grid can obtain one first induced voltage by a capacitance coupling effect, cause transistorized this P-type passage of a PMOS to be opened, and inject mechanism via channel hot electron, electronics is via grid oxic horizon injection and be stored in this floating grid.
5. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 1 wherein when this EEPROM (Electrically Erasable Programmable Read Only Memo) of operation, applies one first positive electricity and is pressed on this N +Also apply one first negative electricity simultaneously is pressed on this P to the type doped region -The type trap, bringing out an avalanche breakdown, and one second negative voltage puts on a P +Drain doping region makes this floating grid obtain one second induced voltage to attract the hot hole in electric hole and the duplet by a capacitance coupling effect, the electronics that can make this floating grid by the tunnelling mode from this N +The type doped region is pulled out.
6. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 5, wherein this second induced voltage is a negative voltage.
7. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 5 wherein puts on this P -This first negative voltage of type trap can be different from and puts on a P +This of drain doping region second negative voltage.
8. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 5 also comprises and applies one the 3rd negative electricity and be pressed on the 2nd P +Source doping region, and open the 2nd PMOS transistor simultaneously, so that a P +Source doping region also has the 3rd negative voltage, to strengthen this second induced voltage of this floating grid.
9. single level polysilicon EEPROM (Electrically Erasable Programmable Read Only Memo) includes:
One the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor, wherein a PMOS transistor and the 2nd PMOS transistor are formed at a N of a P type substrate -On the type trap, a PMOS transistor includes a floating grid, one the one P +Drain doping region and one the one P +Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P +Source doping region, and the transistorized P of a PMOS +Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously;
One diode is arranged in this P type substrate, and wherein this diode includes a P -Type trap and one is arranged at this P -N in the type trap +The type doped region, and this floating grid system is covered in this N -On the type trap and extend to this N +Type doped region top, this P that this floating grid covered -Type trap and this N +The join domain of type doped region is as a snowslide decanting point; And
One P +The type retaining ring is positioned at this P -In the type trap, and this floating grid pastern branch is covered in this P +On the type retaining ring, to produce a P +Interface wherein puts on this P in this floating grid below +The voltage of type retaining ring is same as and puts on this P -The voltage of type trap.
10. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 9, wherein this floating grid top there is no a control grid is set.
11. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 9, wherein this P -Type trap and this N +The type doped region not with the transistorized P of a PMOS -The type channel region overlaps mutually.
12. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 11 wherein when this EEPROM (Electrically Erasable Programmable Read Only Memo) of operation, applies a drain voltage in a P +Drain doping region, and open the 2nd PMOS transistor simultaneously so that a P +Source doping region obtains one source pole line voltage, and this floating grid can obtain one first induced voltage by a capacitance coupling effect, causes transistorized this P of a PMOS -The type passage is opened, and injects mechanism via channel hot electron, and electronics is via grid oxic horizon injection and be stored in this floating grid.
13. EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 9 wherein when this EEPROM (Electrically Erasable Programmable Read Only Memo) of operation, applies one first positive electricity and is pressed on this N +Also apply one first negative electricity simultaneously is pressed on this P to the type doped region +Type retaining ring and this P -The type trap, bringing out an avalanche breakdown, and one second negative voltage puts on a P +Drain doping region is injected to attract the hot hole of electric hole and duplet to strengthen the snowslide hot hole so that this floating grid obtains second induced voltage of strengthening by a capacitance coupling effect, the electronics that can make this floating grid by the tunnelling mode from this N +The type doped region is pulled out.
14. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 13, wherein this second induced voltage is a negative voltage.
15. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 13 wherein puts on this P +This first negative voltage of type retaining ring can be different from and puts on a P +This of drain doping region second negative voltage.
16. the operation of EEPROM (Electrically Erasable Programmable Read Only Memo) as claimed in claim 13 also comprises and applies one the 3rd negative electricity and be pressed on the 2nd P +Source doping region, and open the 2nd PMOS transistor simultaneously, so that a P +Source doping region also has the 3rd negative voltage, to strengthen this second induced voltage of this floating grid.
CNB2005100595361A 2005-03-29 2005-03-29 Single layer polysilicon EEPROM Active CN100514656C (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101494222B (en) * 2008-01-23 2010-08-25 苏州东微半导体有限公司 Semiconductor memory device, semiconductor memory array and read-in method
CN117320452A (en) * 2023-11-29 2023-12-29 合肥晶合集成电路股份有限公司 Multiple programmable device and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101494222B (en) * 2008-01-23 2010-08-25 苏州东微半导体有限公司 Semiconductor memory device, semiconductor memory array and read-in method
CN117320452A (en) * 2023-11-29 2023-12-29 合肥晶合集成电路股份有限公司 Multiple programmable device and preparation method thereof
CN117320452B (en) * 2023-11-29 2024-04-05 合肥晶合集成电路股份有限公司 Multiple programmable device and preparation method thereof

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