CN1825578B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN1825578B CN1825578B CN2005101289908A CN200510128990A CN1825578B CN 1825578 B CN1825578 B CN 1825578B CN 2005101289908 A CN2005101289908 A CN 2005101289908A CN 200510128990 A CN200510128990 A CN 200510128990A CN 1825578 B CN1825578 B CN 1825578B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0233—Sheets, foils
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- B23K35/262—Sn as the principal constituent
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Abstract
本发明提供一种半导体组件及其制造方法,在将半导体元件(3)和无源元件(4)与印制基板(6a)连接的半导体组件中,半导体元件(3)和无源元件(4)与印制基板(6a)之间的连接部(17),由具有260℃以上的熔点的金属和具有260℃以上的熔点的金属间化合物构成。具体地,通过利用具有熔点为260℃以下的无铅焊锡来连接,可以将便宜、轻量且可降低部件高度的印制基板(6a)应用于组件基板中。
Description
技术领域
本发明涉及半导体器件的制造技术,特别涉及对组件基板使用印制基板,并利用“不含铅(以下称无铅)”的金属间化合物将半导体元件和无源部件与印制基板连接的半导体组件及其制造方法中应用的有效技术。
背景技术
作为本发明人讨论的技术,涉及以往的半导体组件(Module)考虑到如下的技术。
图1和图2表示以往的方式的半导体组件的剖面图。半导体元件3和无源部件4被连接在组件基板6上。使用引线2进行引线接合(wire bonding)后,利用塑封(mold)树脂1或密封用框体10内的惰性气体11密封。半导体组件的焊盘(pad)7通过Sn-Ag-Cu类(系)的中温无铅焊锡8与印制基板9的焊盘7回流焊接。Sn-Ag-Cu类无铅焊锡的熔点高,大约220℃,可以设想回流连接时最高可以加热到260℃。因此,以温度梯度为目的,半导体组件内部的半导体元件3和无源元件4的连接使用具有高于等于290℃的熔点的高铅焊锡。因此,半导体组件的组件基板6使用耐热性高的陶瓷基板(Al2O3、AlN、Si3N4等)和金属基板(Al、Cu、Fe类等)。但是,这些组件基板6成本高,关联到半导体封装的高成本化。此外,由于陶瓷和金属组件基板总的重量大、厚度厚,因此还关联到增大部件的重量和高度。
能够便宜且轻、薄、低高度化的基板,有在用Sn-Ag-Cu类焊锡搭载半导体元件和无源元件时使用的FR-4等印制基板。但是,耐热温度低于等于300℃,所以如果用高铅焊锡、Au-20Sn等高熔点焊锡来连接,则因连接时的加热会对基板造成损伤而被破坏。为了对组件基板使用印制基板,优选由进行二次安装的在260℃以下可以连接的材料进行内部连接。但是,用熔点260℃以下的焊锡来进行内部连接的情况下,在回流焊接时焊锡会再熔化。连接部周围被树脂塑封的情况下,如果内部的焊锡再熔化,则因熔化引起的体积膨胀,如图3所示,称为毛刺(或溢料:flash/フラツシュ),焊锡8有时从塑封树脂1和组件基板6的界面漏出。即使不漏出,有要漏出的作用,其结果凝固后在焊锡之中形成大的气孔(void)12而变成不合格品。
例如,根据非专利文献1(威廉姆斯(Willians W.So)等、在“低温下制造高温接合点(High Temperature Joints Manufacturedat Low Temperature)”、ECTC论文集(Proceeding of ECTC)、1998年、p284)报告了以下内容。将背面实施了Cr:0.03μm/Sn:2.5μm/Cu:0.1μm金属化层的GaAs和实施了Cr:0.03μm/Cu:4.4μm/Au:0.1μm金属化层的基板(Glass),在280℃的条件下连接后保持16~24小时,由此使连接部完全Cu3Sn化从而可以使连接部高熔点化。此外,同样地背面实施了Cr:0.03μm/In:3.0μm/Ag:0.5μm金属化层的Si和实施了Cr:0.03μm/Au:0.05μm/Ag:5.5μm/Au:0.05μm金属化层的Si在160~200℃的条件下连接后,在150℃下进行16~24小时的时效处理,使连接部Ag-rich(富含)合金+Ag3In化从而可以使连接部高熔点化。
此外,非专利文献2(山本等、“有关使用Sn-Ag焊锡的微连接部的金属间化合物化的研究(Sn-Agはんだを用いたマイクロ接続部の金属間化合物化に関する研究)”、MES2003的摘要集、2003年10月、p45)中,报告了以下内容。实施了Sn-3.5Ag:26μm的金属化层的Ni-xCo(x=0.10)、焊锡、及实施了Ni-20Co:5μm/Au:1μm金属化层的科瓦铁镍钴合金(Kovar)在240℃下连接并保持30分钟,由此使连接部全部(Ni,Co)Sn2+(Ni,Co)3Sn4化从而可以高熔点化。在金属化层中使用含Co的Ni-20Co从而可以促进化合物的生长速度。
如果使用这些方法,则可以在260℃以下的温度下连接,一旦连接部完全变成高熔点层,则即使在回流焊接时加热到260℃,连接部也不会再熔融,可以保持连接。
因此,对于如上所述的半导体组件,本发明人考虑到作为连接方法,是否可以应用通过上述非专利文献1、2记载的反应来形成化合物并高熔点化的技术。但是,上述2份非专利文献1、2的技术中,以下方面成为顾虑。
非专利文献1、2的技术只触及所谓GaAs与基板(Glass)、Si和Si、所谓科瓦铁镍钴合金和科瓦铁镍钴合金的、耐热性高的材料间的连接。因此在所谓280℃、240℃的温度下加热30分钟以上进行连接。如果在这些条件下将半导体元件及无源元件与印制基板连接,则考虑到印制基板受到由热引起的损伤而会被破坏。
发明内容
本发明的目的在于,提供一种半导体器件的制造技术,确定适用于连接部的、具有260℃以下的熔点的材料,并且在连接部赋予与260℃以下的无铅焊锡反应而形成熔点为260℃以上的化合物的金属层以增加反应界面,由此可以减少对印制基板的损伤。
本发明的上述及其它目的与新的特征,根据本说明的描述和所附的附图可知。
本申请明公开的发明之中,如下简要说明代表性的摘要。
本发明可应用于半导体器件的制造方法,该制造方法具有如下工序:在印制基板上,将具有半导体元件、无源部件、连接了半导体元件和无源部件的印制基板的半导体器件,半导体元件,以及无件器件,通过金属接合来连接;特别是其中,在半导体元件和无源部件与印制基板的连接部,对具有熔点260℃以下的材料,使用所谓Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类、Bi-In类熔点低于等于200℃的材料;在连接部施以与260℃以下的无铅焊锡反应而形成熔点260℃以上的金属间化合物的、所谓Cu、Ag、Ni、Au金属层,以增加反应界面。
此外,本发明同样适用于具有通过金属接合将具有半导体元件、连接了半导体元件的印制基板的半导体器件和半导体元件,与印制基板连接的工序的半导体器件的制造方法中,只要是至少半导体元件连接在印制基板上的结构即可。
附图说明
图1是表示已有方式的半导体组件的剖面图。
图2是表示已有方式的另外的半导体组件的剖面图。
图3是已有方式的半导体组件中说明由再熔融的焊锡产生的毛刺的剖面图。
图4是本发明的半导体组件中表示连接部的剖面图。
图5是本发明的半导体组件中表示其它连接部的剖面图。
图6是本发明的半导体组件中表示各种材料的杨氏模量(ヤング率)和屈服应力的说明图。
图7是本发明的半导体组件中表示再一其它连接部的剖面图。
图8是表示本发明的实施方式1的半导体组件的剖面图。
图9是本发明的实施方式1的半导体组件中,表示在印制基板上设置高熔点金属和低熔点焊锡各层时的剖面图。
图10是本发明的实施方式1、2及已有方式的半导体组件中,表示内部连接时对是否有印制基板的损伤、回流测试中可否保持连接的研究结果的图。
图11是本发明实施方式1的半导体组件中,表示连接部全部化合物化而形成金属间化合物的状态的剖面照片的图。
图12是本发明的实施方式2的半导体组件中,表示复合箔的剖面图。
图13是本发明的实施方式中,表示应用例的半导体组件的剖面图。
图14是本发明的实施方式中,表示其它应用例的半导体组件的剖面图。
图15是本发明的实施方式中,表示再一其它应用例的半导体组件的剖面图。
具体实施方式
根据图4~图7来说明本发明的半导体器件的概念。本发明是将半导体元件(及无源部件)与印制基板连接的半导体器件,其中,具有以下(1)~(7)所示的特征。此外,本发明是对于在印制基板上通过金属接合连接半导体元件(及无源部件)的半导体器件的制造方法,具有(8)~(15)的特征的方法。
(1)半导体元件(及无源部件)与印制基板的连接部由具有260℃以上(高于等于260℃)的熔点的金属和具有260℃以上的熔点的金属间化合物构成。在连接部如果残留二次安装时具有260℃以下(低于等于260℃)的熔点的低熔点相,则进行二次安装时低熔点相再次熔融,由此产生以上所述的毛刺或再熔融剥离,存在不能保持连接的情形。因此,如上所述,仅用具有260℃的熔点的金属和金属间化合物来形成连接部,可以在二次安装时保持连接。
(2)连接部从半导体元件(及无源部件)侧开始,包括:具有260℃以上的熔点的金属间化合物、具有260℃以上的熔点的金属、具有260℃以上的金属化合物的各层。图4表示半导体元件3和印制基板6a之间的连接部15(金属间化合物13+高熔点(260℃以上的熔点)的金属14)的剖面图。并且,详细地,在印制基板6a的表面上形成有Cu接合区,但图中省略。在金属层使用与260℃以下的无铅焊锡反应而形成金属间化合物的金属的情况下,通过选择反应速度快的金属,可以使连接低温化并缩短时间。此外,在金属层使用柔软的材料或具有半导体元件和印制基板的中间的热膨胀率的金属的情况下,缓和由被连接材料间的热膨胀率差产生的热应力,能够抑制在半导体元件和连接部产生的裂缝。
(3)连接部由具有260℃以上的熔点的金属间化合物和具有260℃以上的熔点的金属分散存在的层构成。图5表示半导体元件3和印制基板6a(省略Cu接合区(Cu land))的连接部15(金属间化合物13+高熔点(260℃以上的熔点)金属14)的剖面图。与上述(2)同样地,对具有260℃以上的熔点的金属,使用与260℃以下的无铅焊锡反应而形成金属间化合物的金属的情况下,通过增加反应界面,可以使连接低温化并缩短时间。此外,应用具有柔软材料或半导体元件与印制基板的中间的热膨胀率的金属的情况下,能够缓冲由被连接材料间的热膨胀率差产生的热应力,能够抑制在半导体元件和连接部产生的裂缝。
(4)具有260℃以上的熔点的金属间化合物,是熔点260℃以下的Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个、与Cu、Ag、Ni、Au之中的至少一个金属,管芯装配连接时反应而形成的。由于是具有印制基板的耐热温度以下的熔点的材料,因此短时间的连接不会破坏印制基板。但是,化合物化花费时间的情况下,在印制基板中有时产生损伤。因此,需要考虑尽可能在低温下连接,短时间内化合物化。如上(2)所述,连接部形成多层结构的情况下,连接部的金属间化合物的厚度需要形成1~20mm。1mm以下的情况下,不能确保连接时连接界面整个区域的浸润,产生连接不良。比20mm厚的情况下,用于使连接部全化合物化需要长时间,对印制基板的损伤成问题。另一方面,如上(3)所述,金属间化合物和金属分散存在的情况下,不需要像多层结构那样规定连接部的厚度,若金属所占的比例为连接部的10vol.%以下时不能充分确保反应界面,难以在短时间内使连接部高熔点化。
(5)具有260℃以上熔点的金属由与熔点260℃以下的Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡反应而形成金属间化合物的、Cu、Ag、Ni、Au之中的至少一个构成。如前所述,将熔点260℃以下的无铅焊锡与形成金属间化合物的金属赋予连接部,由此可以增加反应界面,可以使连接低温化、并缩短时间。
(6)具有260℃以上的熔点的金属是在Al、Zn、Mg、Cu/因瓦(invar)合金/Cu复合材料、Cu/Cu2O复合材料、Cu-Mo合金、Ti、Mo、W之中至少一个上,形成有与熔点260℃以下的Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡反应而形成金属间化合物的、Cu、Ag、Ni、Au之中的至少一个的金属化层(金属镀层:metalize)。图6表示各金属的屈服应力与杨氏模量。Al、Zn、Mg是比较柔软的金属,在产生热应力时,通过这些金属塑性变形来缓冲热应力,由此可以确保连接部的可靠性。该金属的屈服应力的大小最好是小于等于75MPa。屈服应力为大于等于100MPa的情况下,热应力不能充分缓冲,有时在半导体元件和连接部产生裂缝。对材料的杨氏模量依赖性并不大,但越小越好。另一方面,Cu/因瓦合金/Cu复合材料、Cu/Cu2O复合材料,Cu-Mo合金、Ti、Mo、W具有半导体元件和印制基板的中间的热膨胀率,可以缓冲随之产生的热应力。此外,这类金属不与低熔点的无铅焊锡形成金属间化合物的情况下,需要在金属表面设置Cu、Ag、Ni、Au层。
(7)半导体元件(及无源部件)与印制基板的连接部,由具有260℃以上的熔点的金属间化合物构成。图7表示半导体元件3和印制基板6a(省略Cu接合区)的连接部17(金属间化合物13)的剖面图。所谓Sn-Zn、Sn-In、Sn-Bi的无铅焊锡连接温度低至200℃以下。因此,即使不由前述那样的金属相增加反应界面,有时也可以在短时间内能够化合物化。此外,连接后冷却时产生的热应力小,因此不设置前述那样的金属相,有时也具有充分的可靠性。
(8)在将设有熔点260℃以下的金属层的复合箔***设置于半导体元件(及无源部件)和印制基板之间的状态下,加热复合箔来形成金属接合,该熔点260℃以下的金属层通过与熔点260℃以上的金属层的反应来形成熔点260℃以上的金属间化合物。
(9)具有熔点260℃以上的金属层由Cu、Ag、Ni、Au之中的至少一个形成。由反应形成260℃以上的熔点的金属间化合物的、熔点为260℃以下的金属层是Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个。通过反应来形成260℃以上的熔点的金属间化合物的、熔点260℃以上的金属层是Cu、Ag、Ni、Au之中的至少一个金属。无铅焊锡是具有印制基板的耐热温度以下的熔点的材料,因此在短时间的连接中不会破坏印制基板。但是,化合物化花费时间的情况下,有时对印制基板产生损伤。因此,需要考虑尽可能在低温下连接,在短时间内化合物化。
(10)复合箔是在Cu、Ag、Ni、Au之中的至少一个的表面上,通过电镀,形成Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个而得到的。这时,需要使镀层的厚度为1~20mm。1mm以下的情况下不能确保连接时连接界面整个区域的润湿,产生连接不良。比20mm厚的情况下,使连接部全化合物化需要长时间,对印制基板的损伤成为问题。
(11)复合箔是在Cu、Ag、Ni、Au之中的至少一个的表面上,通过浸渍,形成Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个而得到的。与上述(10)同样地,需要使浸渍的厚度为1~20mm。1mm以下的情况下不能确保连接时连接界面整个区域的润湿,产生连接不良。比20mm厚的情况下,使连接部全化合物化需要长时间,对印制基板的损伤成为问题。
(12)在印制基板侧设置通过与260℃以上的熔点的金属层反应来形成260℃以上的熔点的金属间化合物的、熔点为260℃以下的金属层,在将半导体元件(及无源部件)搭载在印制基板上的状态下加热来形成金属接合。
(13)具有260℃以上的熔点的金属层,由Cu、Ag、Ni、Au之中的至少一个来形成。通过反应来形成260℃以上的熔点的金属间化合物的、熔点为260℃以下的金属层,是Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个。通过反应形成熔点260℃以上的金属间化合物的、熔点260℃以上的金属层,是Cu、Ag、Ni、Au之中的至少一个金属。无铅焊锡是具有印制基板的耐热温度以下的熔点的材料,因此短时间的连接中不会破坏印制基板。但是,化合物化花费时间的情况下,有时在印制基板中产生损伤。因此,需要考虑尽可能在低温下连接,短时间内化合物化。
(14)形成在印制基板上的金属层是在Cu、Ag、Ni、Au之中的至少一个的表面上,通过电镀,由Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个来形成。这时,需要使电镀的厚度为1~20mm。1mm以下的情况下不能确保连接时连接界面整个区域的润湿,产生连接不良。比20mm厚的情况下,使连接部全化合物化需要长时间,对印制基板的损伤成为问题。
(15)形成在印制基板上的金属层是在Cu、Ag、Ni、Au之中的至少一个的表面上,通过浸渍,由Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡之中的至少一个来形成。与上述(14)同样地,需要使浸渍的厚度为1~20mm。1mm以下的情况下不能确保连接时连接界面整个区域的润湿,产生连接不良。比20mm厚的情况下,使连接部全化合物化需要长时间,对印制基板的损伤成为问题。
以下,根据附图详细说明依据上述的本发明的概念的、本发明的实施方式。并且,用于说明实施方式的所有图中,也包括图1和图2的以往的方式,原则上相同部件赋予相同符号,省略其反复的说明。
(实施方式1)
图8表示本发明的实施方式1的半导体器件的剖面图。
本实施方式涉及的半导体器件例如应用于功率半导体组件,包括:半导体元件3、无源元件(无源部件)4、连接了半导体元件3和无源元件4的印制基板(组件基板)6a、将半导体元件3的电极和印制基板6a的电极之间引线接合的引线2、以及密封半导体组件的塑封树脂1。该半导体组件安装在印制基板9上与各种装置组装。
该半导体组件的制造工序如下表示。例如,半导体组件的内部连接通过上述的图7的连接部17的结构进行的情况下,在组件基板中使用的印制基板6a的半导体元件3和无源元件4的搭载部上,如图9所示地设置高熔点金属20和具有260℃以下的熔点的无铅焊锡的低熔点焊锡21各层。这些层通过电镀或浸渍等方法形成。
将半导体元件3和无源元件4与该印制基板6a的搭载部,在不对印制基板6造成损伤的温度下连接。这时,使高熔点金属20与低熔点焊锡21反应,使连接部17化合物化而高熔点化。接着,形成在半导体元件3的表面上的电极、和形成在印制基板6a上的电极之间,通过引线2来引线接合。并且利用环氧系树脂等塑封树脂1密封。通过以上的工序能够制造半导体组件。
接着,关于本实施方式的半导体组件,在图10的实施例1~3的条件下制作的半导体组件(各条件20个),进行了是否有内部连接时的对印制基板(FR-4)6a的损伤、最高温度260℃的回流测试中可否保持连接的研究。其结果表示在图10。
将上述的图7的连接部17的结构形成为,Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡、与Cu、Ag、Ni、Au金属的金属间化合物,作为一例,在实施例1中为Sn-In(10μm)+Cu,在实施例2中为Sn-In(10μm)+Ag,在实施例3中为Sn-Zn(10μm)+Ag。
其结果,在实施例1~3全部中,在240℃10min.(分钟)的连接条件下,在印制基板6a中没有确认异常。此外,在所谓240℃10min.的连接条件下,确认如图11所示地连接部17全部化合物化而形成了金属间化合物。并且,对制作的半导体组件进行最高温度260℃的回流实验的结果,在所有半导体组件中,确认了可以抑制伴随焊锡再熔融的毛刺、再熔融剥离并保持连接。
由以上的事实,可知通过上述连接方式可以将印制基板6a适用于组件基板。
因此,能够将便宜、轻且可以降低部件高度的印制基板6a应用于组件基板,并且还也可以抑制对该印制基板6a的损伤。
(实施方式2)
与本发明的实施方式2相关的半导体器件,与上述实施方式1中说明的图8的剖面图相同,不同点在于,对于半导体组件的内部连接应用了上述图4的连接部15的结构。并且,应用上述的图5的连接部16的结构的情况也是同样的。
如下表示该半导体组件的制造工艺。半导体组件的内部连接通过上述图4的连接部15的结构进行的情况下,将图12所示的复合箔30供给到印制基板6a上。在高熔点金属14的层的表面上设置熔点260℃以下的无铅焊锡的低熔点焊锡21的层来制作该复合箔30。此外,在图12的高熔点金属14和低熔点焊锡21不形成化合物的情况下,还有在高熔点金属14和低熔点金属21之间设置与低熔点焊锡21形成化合物的第二高熔点金属的层的情况。这些层通过电镀或浸渍等方法来形成。
并且,在印制基板6a上供给复合箔30后,在其上供给半导体元件3和无源元件4来连接。这时,使高熔点金属14和低熔点焊锡21反应而使连接部15化合物化并高熔点化。接着,通过引线2将形成在半导体元件3的表面上的电极、和形成在印制基板6上的电极之间引线接合。并且,使用环氧树脂系树脂等塑封树脂1来密封。通过以上的工艺可以制造半导体组件。
接着,如上述的图10所示,在本实施方式的半导体组件中,对于实施例4~6的条件下制作的半导体组件(各条件20个),进行了如下的研究:内部连接时是否有印制基板(FR-4)6a的损伤、高温度260℃下的回流实验中的保持连接与否。图10表示其结果。
将上述的图4的连接部15的结构形成为,在Al、Zn、Mg、Cu/因瓦合金/Cu复合材料、Cu/Cu2O复合材料、Cu-Mo合金、Ti、Mo及W上,形成与Sn、In、Sn-Ag类、Sn-Cu类、Sn-Ag-Cu类、Sn-Zn类、Sn-Zn-Bi类、Sn-In类、In-Ag类、In-Cu类、Bi-Sn类和Bi-In类无铅焊锡反应而形成金属间化合物的Cu、Ag、Ni、Au的金属化层,作为一例,在实施例4中,为Sn-In(10μm)+Ag/Al(10μm)/Sn-In(10μm)+Ag,在实施例5中为Sn-In(10μm)/(Cu/因瓦合金/Cu复合材料)(100μm)/Sn-In(10μm),在实施例6中为Sn-Zn(10μm)+Ag/Al(100μm)/Sn-Zn(10μm)+Ag。
其结果,在实施例4~6全部中,在240℃10min的连接条件下,在印制基板6a中没有确认异常。此外,进行最高温度260℃的回流实验的结果,在所有的半导体组件中,确认了可以抑制伴随焊锡再熔融而发生的毛刺和再熔融剥离,并保持连接。特别是,对高熔点金属14应用具有应力缓冲效果的Al或CIC,因此,与上述实施例1~3比较,对热冲击的可靠性也高。
由上述的事情可知,通过上述连接方式可以对组件基板应用的印制基板6a。
因此,可以在组件基板中应用便宜、轻量且可以降低部件高度的印制基板6a,并且还可以抑制对该印制基板6a的损伤。
(本实施方式对以往的方式)
相对于上述的本发明的实施方式1、2,关于以往的方式(图1和图2),如上述的图10所示,使用Pb-5Sn焊锡(比较例1)、Au-20Sn焊锡(比较例2),对印制基板上连接半导体元件而制作的半导体组件(各条件20个),进行了内部连接时是否存在对印制基板6的损伤、最高温度260℃的回流实验中可否保持连接的研究。
其结果,在比较例1、2中,连接温度高达300℃以上,因此与上述实施例1~6比较,连接时间不到1min.,在所有样品中,印制基板6烧焦变色。此外,在一部分印制基板6中,还确认了基板的变形。
由以上的事情可知,在以往的方式中,使用Pb-5Sn、Au-20Sn的高熔点焊锡的情况下,很难将印制基板6作为组件基板使用。
以上,根据实施方式具体地说明了由本发明人完成的发明,但是,本发明不限定于上述实施方式,不用说可以在不脱离其主旨的范围内进行各种变更。
例如,如图13所示,在半导体组件的内部,连接有多个半导体元件3的MCM(Multi Chip Module:多芯片组件),也可以应用与实施例相同的连接方法。
此外,如图14所示,代替引线接合使用了连接条(strap)18的连接中,也能够应用与实施例相同的连接方法。这时,将连接条18的连接部用电镀或浸渍等设置高熔点金属与260℃以下的无铅焊锡层,或者通过使用复合箔30来连接,由此,可以采用与半导体元件3a和印制基板6a之间的连接相同的连接方式。
此外,如图15所示,还可以并用本连接技术与导电粘接剂,即通过本连接技术装载半导体元件3,通过导电粘接剂19来装载无源元件14。
除上述以外,在本发明的应用中,在SAW滤波器及RF组件的密封部的连接中也可以应用本连接方法。
在本申请中描述的发明中,简单说明通过代表性的技术所得到的效果如下。
根据本发明,涉及将半导体元件(及无源元件)连接在印制基板上的半导体器件,在半导体元件(及无源元件)与印制基板的连接部中,确定了适用于连接部的具有260℃以下的熔点的材料,此外,在连接部赋予与260℃以下的无铅焊锡反应而形成熔点260℃以上的化合物的金属层来增加反应界面,由此可以降低对印制基板的损伤。
本发明可以在以半导体组件为代表的半导体器件的、半导体元件和无源元件与印制基板的连接中有效地利用。
Claims (5)
1.一种半导体器件,其特征在于,
具有半导体元件、无源部件、及将上述半导体元件和上述无源部件连接的印制基板,
上述半导体元件和上述无源部件与上述印制基板的连接部,从上述半导体元件和上述无源部件侧向上述印制基板,依次层叠具有260℃以上的熔点的第1金属间化合物、具有260℃以上的熔点的金属、及具有260℃以上的熔点的第2金属间化合物。
2.如权利要求1所述的半导体器件,其特征在于,
上述第1金属间化合物和第2金属间化合物,是熔点260℃以下的Sn、In、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Zn、Sn-Zn-Bi、Sn-In、In-Ag、In-Cu、Bi-Sn和Bi-In无铅焊锡之中至少一个、与Cu、Ag、Ni、Au之中的至少一个金属在连接时反应而形成的。
3.如权利要求1所述的半导体器件,其特征在于,上述具有260℃以上的熔点的金属由与熔点260℃以下的Sn、In、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Zn、Sn-Zn-Bi、Sn-In、In-Ag、In-Cu、Bi-Sn和Bi-In无铅焊锡反应而形成金属间化合物的Cu、Ag、Ni、Au之中的至少一个构成。
4.如权利要求1所述的半导体器件,其特征在于,上述具有260℃以上的熔点的金属,在Al、Zn、Mg、Cu/因瓦合金/Cu复合材料、Cu/Cu2O复合材料、Cu-Mo合金、Ti、Mo、W之中至少一个上,形成有与熔点260℃以下的Sn、In、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Zn、Sn-Zn-Bi、Sn-In、In-Ag、In-Cu、Bi-Sn和Bi-In无铅焊锡反应而形成金属间化合物的Cu、Ag、Ni、Au之中的至少一个的金属化层。
5.一种半导体器件,其特征在于,
具有半导体元件和连接了上述半导体元件的印制基板;
上述半导体元件与上述印制基板的连接部从上述半导体元件侧向上述印制基板,依次层叠具有260℃以上的熔点的第1金属间化合物、具有260℃以上的熔点的金属、及具有260℃以上的熔点的第2金属间化合物。
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JP5093235B2 (ja) * | 2007-06-04 | 2012-12-12 | 株式会社村田製作所 | 電子部品装置およびその製造方法 |
JP2010103206A (ja) * | 2008-10-22 | 2010-05-06 | Panasonic Corp | 半導体装置及びその製造方法 |
TWI401825B (zh) | 2009-11-27 | 2013-07-11 | Ind Tech Res Inst | 發光二極體晶片的固晶方法及固晶完成之發光二極體 |
US8348139B2 (en) * | 2010-03-09 | 2013-01-08 | Indium Corporation | Composite solder alloy preform |
JP5546067B2 (ja) * | 2010-10-22 | 2014-07-09 | パナソニック株式会社 | 半導体接合構造体および半導体接合構造体の製造方法 |
TWI461252B (zh) | 2010-12-24 | 2014-11-21 | Murata Manufacturing Co | A bonding method, a bonding structure, an electronic device, an electronic device manufacturing method, and an electronic component |
JP5724638B2 (ja) * | 2011-05-30 | 2015-05-27 | 日立金属株式会社 | Pbフリーはんだ及びはんだ被覆導体並びにそれを用いた電気部品 |
DE102011083931A1 (de) * | 2011-09-30 | 2013-04-04 | Robert Bosch Gmbh | Schichtverbund aus einem elektronischen Substrat und einer Schichtanordnung umfassend ein Reaktionslot |
US8957521B2 (en) * | 2011-12-27 | 2015-02-17 | Panasonic Intellectual Property Management Co., Ltd. | Mounted structure |
CN104144764B (zh) * | 2012-03-05 | 2016-12-14 | 株式会社村田制作所 | 接合方法、接合结构体及其制造方法 |
JP2014190875A (ja) * | 2013-03-27 | 2014-10-06 | Hitachi Ltd | 力学量測定装置およびその製造方法 |
WO2015040737A1 (ja) * | 2013-09-20 | 2015-03-26 | 株式会社日立製作所 | 半導体素子の接合構造 |
DE102017004626A1 (de) | 2017-05-15 | 2018-11-15 | Pfarr Stanztechnik Gmbh | Bleifreie Lötfolie zum Diffusionslöten |
US10700036B2 (en) * | 2018-10-19 | 2020-06-30 | Toyota Motor Engineering & Manufacturing North America, Inc. | Encapsulated stress mitigation layer and power electronic assemblies incorporating the same |
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US11610861B2 (en) * | 2020-09-14 | 2023-03-21 | Infineon Technologies Austria Ag | Diffusion soldering with contaminant protection |
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