CN1823275B - 用于平整化集成电路中的电流消耗的方法和装置 - Google Patents
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Abstract
本发明包括一种用于平整化一数字逻辑模块中的电流消耗的***。一处理电路经配置以接收一输入并在一处理时间周期期间处理所述输入以产生一输出。一非处理时间周期跟在所述输出的产生之后。所述处理电路进一步经配置以在所述处理时间周期期间得出一电流的运行范围<u>(an active range of current)</u>并在所述非处理时间周期期间得出一电流的非运行范围<u>(an inactive range of current)</u>。所述***包含一平流电路,其耦接到所述处理电路且经配置以使所述处理电路在所述非处理时间周期期间运作。所述平流电路还经配置以使所述处理电路在所述非处理时间周期期间得出一电流的运行范围。
Description
技术领域
本发明涉及平整化数字逻辑模块中的电流消耗,且更特定而言,涉及处理器中的电流整形以使电流分析变得更加复杂。
背景技术
图1是说明现有技术的简化微控制器的示意图。一微控制器一般包括一微处理器、存储器、一提供通信的***模块(例如,通用异步接收器/发射器(UART)、SPI和USB),和一中断控制器。微控制器100包括耦接到存储器104的微处理器102。地址解码器106接收并解码来自微处理器102的地址以用于存储器104和***设备108。地址解码器106和***设备108接收地址总线110上的地址,同时地址解码器106传输存储器选择112和***选择114上的选择信息。在微处理器102、存储器104和***设备108之间在数据总线116上传输数据。在微处理器102和存储器104和***设备108之间在读/写信号117上传输读或写信号。微控制器100接收时钟信号118和重设信号120。输入122包括(例如)定时器触发和UART输入数据,而输入124包括(例如)UART发射器输出数据。中断控制器126收集并处理来自***设备108的沿着中断线(未图示)的中断信号。
***设备108可以是功能逻辑,例如UART、密码处理、数字信号处理(DSP)和数字过滤。
图2说明***设备、密码处理器的一个实例。在具有加密处理器的情况下,如果必须要加密或解密数据缓冲器,软件将缓冲器划分成若干部分。每一部分代表在处理时间周期期间能处理的数据。只要将所述部分输入加密处理器和/或供应起始信号,***设备就开始处理所述部分。一个时钟循环周期后,处理周期结束且加密处理器提供可由软件读回的加密/解密部分。当完成数据处理时,开始非处理时间周期且可声明一中断信号以通知微处理器所述部分正准备读取且解密处理器正准备加密/解密新的部分。一旦将新的部分输入密码处理器和/或供应起始信号,非处理时间周期就结束且开始新的处理时间周期。软件继续读写,直到数据缓冲器的最终部分。
当执行由密码处理器使用的算法时,归因于数字单元切换的电流消耗在处理起始时会增加,且在处理结束后会减少。电流会由于执行算法的数字模块中的组合的(例如AND、OR、反相器、MUX和XOR)单元和连续的单元(例如D触发器或DFF)而增加。在非处理时间周期期间,通常唯一的触发位于DFF的时钟针上。与当处理运行时所消耗的电流相比,这个值和静态泄漏电流并不显着。
用户接口模块200处理***数据(例如地址、数据、读/取和选择信号)以产生命令和数据用于算法模块202。算法模块202根据由用户接口模块200提供的控制命令、数据和加密/解密密钥而执行加密/解密。计数器108从用户接口200接收起始信号且将数据路径组织到算法模块202中。
密码算法可表示成基本的组合功能,其结合数次以获得结果。举例而言,实行一次组合的功能并连接到存储构件(DFF或其它构件)。需要一个多路器来选择算法功能的输入(数据输入或中间结果),其取决于计数器模块n值(n是执行获得结果的反复数,例如在数据加密标准(DES)中是16)。三次数据加密标准(TDES)使用三个16反复周期。
计数器204在起始线206上接收一起始信号。起始信号触发从计数器204到算法模块202中的多路器208的第一循环信号。多路器208接收第一循环信号且从输入数据线210选择输入。输入数据接着到达组合电路212,组合电路与密钥和密码结合,处理输入数据。组合电路212在接收到第一循环信号和输入数据时开始处理,从而开始处理时间周期。组合电路212将经处理的输入数据传输到多路器213。在处理周期期间,多路器213从计数器204接收处理周期信号且因此从组合电路212选择数据。多路器213将经处理的输入数据传输到DFF 214,DFF 214接着将经处理的数据发送到输出端216、多路器208和213。对于随后的反复而言,无第一循环信号被传输到多路器208,所以多路器208从DFF 214选择经处理的输入数据并将其发送到组合电路214,所述组合电路214再次处理输入数据。计数器204保持对每一反复的跟踪,且一直倒计数到最后的反复为止。在最后的反复处,计数器204将末循环信号发送到组合电路212,指示处理时间周期的结束。来自计数器108的处理周期信号触发多路器213以选择来自DFF 214而非来自组合电路212的输入。DFF 214接收循环的数据,其在循环的这个点处是所要的输出数据。从计数器204发送一中断信号,指示输出端216处有效的数据是所要的输出,所以用户接口模块200在适当的时钟循环上从输出端216取回输出数据。
在处理时间周期结束时,计数器204经重设且等待起始一新的序列。图3是说明代表在处理周期期间激发组合电路212的时序图和电流波形的图。
当处理数据缓冲器时,电流消耗可看作一系列脉冲。此波形的低电平周期代表***模块的DFF的时钟树和时钟针的电流消耗。高电平周期代表组合电路212切换电流。通过在脉冲的上升边缘上使外部数字分析器设备同步,可存储电流的数字表示法。此模型可经处理以在不使用侵入攻击(处理模型常被称为非侵入攻击)损坏集成电路的情况下提取算法的“密钥”值。当处理不同的数据时,其基于电流消耗中的差异。
图3说明时钟信号300和输入数据305。输入数据305在输入数据线210(图2)上有效,且代表被划分的输入数据缓冲器的部分。沿着起始线206传输起始信号310,且起始信号310触发处理时间周期315的开始。计数器204倒计时,在此状况下是DES的从15到0,且时间间隔值是320。同时从计数器204传输第一循环信号325和间隔计数器320上的第一计数,且同时从计数器204传输末循环信号330和间隔计数器320上的末计数,且通知处理时间周期315的结束和非处理时间周期335的开始。在处理时间周期315期间使用输入数据来驱动组合电路212,其比非处理时间周期335期间得出更多的电流。
如果时钟周期用于确定数据处理的不同步骤的时间,那么可通过如电流消耗形状分析的非侵入方法来检测或观察处理时间周期315。每个时间数据都被处理,电流增加到电流的运行范围,且接着在非处理时间周期335期间减少到电流的非运行范围。因此,可确定集成电路内所处理的数据。
所需的是一种使电流消耗的分析更加复杂的***和方法。
发明内容
本发明由使用接近处理时间周期期间的电流的值(和形状)的电流值来填充非处理时间周期组成。本发明可用于其中嵌入数字逻辑模块的任何电路中。本发明发生在集成电路的数字部分中。当在数字模块中处理数据时,组合逻辑运作且使功率消耗增加。在仅考虑数字逻辑的情况下,电流上的所述增加主要是由于单元切换。与此切换电流相比,总的单元泄漏电流较低。
所述***和方法使电流消耗整形以使电流分析更加复杂。由在处理时间周期期间产生电流形状的相同数字逻辑在非处理时间周期期间执行电流整形,从而导致不管数据是否经过处理,电流波形都类似。
附图说明
图1是说明简化的微控制器的现有技术示意图。
图2是说明***设备的一个实例的现有技术示意图。
图3是说明对于来自图2的***设备的时序图和电流波形的现有技术图。
图4是说明微控制器中的本发明的一个实施例的示意图。
图5是说明来自图4的本发明的一个实施例的示意图。
图6是说明来自图5的本发明的更加详细的实施例的示意图。
图7是说明用于本发明的一个实施例的时序图和电流波形的图。
图8是说明数字逻辑模块中的平流方法的流程图。
图9是说明数字逻辑模块中的平流方法的流程图。
具体实施方式
图4是说明微控制器的数字逻辑模块或***设备中的本发明的一个实施例的示意图。处理电路400从用户接口402接收沿着输入线404的输入。平流电路406从用户接口402接收沿着起始线408的起始信号。平流电路406将第一循环信号传输到处理电路400,其开始一处理时间周期。在处理时间周期期间,处理电路400处理输入以产生所要的输出,例如输入的加密或解密版本。由于处理,(例如逻辑单元切换),处理电路400在处理时间周期期间得出电流的运行范围。在处理时间周期结束时,平流电路406将末循环信号传输到处理电路400,且经处理的输入在输出端口410处准备作为输出。
处理时间周期的结束是非处理时间周期的开始。平流电路406使处理电路400在非处理时间周期期间运作,从而使得处理电路400在非处理时间周期期间所得出的电流的范围与在处理时间周期期间所得出的电流的范围相同。在一实施例中,处理电路400在非处理时间周期期间的操作不改变输出端口410处有效的输出。
图5是说明来自图4的本发明的更详细的实施例的示意图。图5包括用户接口402,平流电路406和处理电路400。在一实施例中,处理电路400包括耦接到多路器510的组合电路500。多路器510从输入线404接收输入。如果多路器510也从平流电路406接收第一循环信号,那么多路器510从输入线504选择输入,且将其发送到组合电路500。组合电路500处理所述输入并将经处理的输入传递到DFF 520。在一实施例中,组合电路500不接收第一循环信号和/或末循环信号。第一循环信号和末循环信号控制处理时间周期和非处理时间周期期间的数据流。
DFF 520将经处理的输入发送到存储电路530且发送到多路器510。现在处于第二循环过程,多路器510不接收第一循环信号,所以其将经处理的输入从DFF 520传输到组合电路500。平流电路406保持对反复次数的跟踪,其对于输入通过组合电路500而言是必要的。
在每个反复期间,DFF 520将每个循环的经处理的输入传输到存储电路530。在整个处理时间周期中,存储电路530接收并非为所要的输出的中间结果。在处理时间周期结束时,在已充分处理输入以产生所要的输出后,平流电路406将存储信号传输到存储电路530。在存储电路530接收到存储信号后,其存储所要的输出并使其在输出端口410处在整个非处理时间周期中有效。在下一处理时间周期开始时,存储电路530继续使先前所要的输出在输出端口410处有效,直到下一存储信号为止。
在非处理时间周期期间,尽管已产生所要的输出,组合电路500继续处理从多路器510供应的输入。所要的输出被存储在存储电路530中,对输出端口410有效且在非处理时间周期期间不受组合电路500的连续处理的影响。在非处理时间周期结束和下一处理时间周期开始时,平流电路406接收一起始信号并将第一循环信号发送到多路器510,其接着选择输入线404上有效的输入。下一处理时间周期的其余时间如上述进行。
在一实施例中,存储电路530包含多路器540和DFF 550。多路器540在处理时间周期期间接收来自DFF 520的经处理的输入和来自DFF 550的输入。直到多路器540接收来自平流电路406的存储信号,多路器540选择来自DFF 550的输入以输出到DFF550。DFF 550使得来自多路器540的输入对于输出端口410和多路器540有效。相同的值在多路器540与DFF 550之间循环,直到存储信号触发多路器540以选择在处理时间周期结束时有效的所要的输出。
在一实施例中,在非处理时间周期期间移除第一循环信号的声明。DFF 625可输出到接收第一循环信号的AND门(未图示),使得仅当已传输起始信号且并未重设时第一循环信号触发。此实施例可使其更难分析TDES算法,其中在每个DES的第一循环期间执行特殊处理。此特殊处理导致不同的电流值,这是由于其重新产生了第一处理循环和末处理循环期间所出现的消耗中的差异。
图6是说明来自图5的本发明的更加详细的实施例的示意图。平流电路406的一实施例是计数器600。计数器600是经配置以跟踪处理和非处理时间周期的电路的一个实例。所属领域的技术人员将认识到,不同的电路和逻辑可替换计数器600并执行类似的功能。计数器600接收一重设信号并重设其计数,在一实例中计数是DES的16,所以计数器600从15倒计到0。接收器600具有接收起始信号的多路器605,所以在接收到重设和起始信号时,计数器600传输第一循环信号并将DFF 610的计数重设为15。DFF610将计数传输到减法器,或逐个减小计数的递减器(未图示),且多路器605选择递减的计数并将其传输到DFF 610。计数递减到零,其触发末循环信号的传输。
起始信号触发多路器620以选择声明,在此实例中是一高输入值“一”。多路器620将高输入值传输到DFF 625,DFF 625将其传输到AND门和多路器635。多路器635具有来自DFF 625的输入的默认选择,所以多路器635将高值传输到多路器620。在下一时钟循环上,起始信号不再被声明,所以多路器620默认来自多路器635的输入。高值在处理时间周期期间继续循环。
在处理时间周期结束时,末循环信号触发多路器635,促使多路器635选择去除声明,或此实例中的低输入值“零”。多路器620默认选择多路器635的输出且将沿着零而通过。末循环信号在AND门630上为高。DFF 625尚未接收到结果“零”,所以DFF625具有对AND门630的高输出。通过处理时间周期的结束的触发,到AND门630的组合的高信号促使AND门630声明存储信号。
因为计数器600在非处理时间周期期间持续计数,所以计数器600不应发出可在输出端口410处改变存储的输出值的存储信号。由起始信号驱动的多路器620防止在非处理时间周期期间声明存储信号。
图7是说明用于本发明的一个实施例的时序图和电流波形的图。参考图4中的电路而描述图7中的信号和电流。用户接口402、平流电路406和处理电路400中的每一者都接收时钟信号700。处理电路400从用户接口402接收输入数据710,且从平流电路406接收第一循环信号720。已由用户接口402发出起始信号(未图示)且开始处理时间周期730,其在此实例中是16个时钟循环。处理电路400在处理时间周期730期间处理输入并得出电流740。在处理时间周期730结束时,平流电路406传输末循环信号且使所要的输出在输出端口410处有效。尽管输入不再需要被处理以产生所要的输出,但处理电路400在非处理时间周期760期间继续对其进行处理并得出电流740。起始信号(未图示)再次使用第一循环信号780进行触发并开始处理时间周期770。贯穿处理时间周期730和770和非处理时间周期760的电流740仍处于指示运行的处理电路400的范围内,因此使电流消耗的分析更加复杂。内部行为和参数对于非侵入攻击(例如DPA)而言更具有保护性。
图8是说明平整化数字逻辑模块中的电流消耗的方法的流程图,其中所述数字逻辑模块具有耦接到输出端口的处理电路。在方框800中,接收一输入。在方框805中,当输入有效时接收一起始信号。在方框810中,触发处理时间周期的开始。在方框815中,驱动处理电路以在一处理时间周期期间处理所述输入。在方框820中,使用计数器来跟踪所述处理时间周期。在方框825中,从在处理时间周期期间经处理的输入得到一输出。在方框830中,产生一指示所述处理时间周期的结束的末循环信号。在方框835中,将末循环信号和起始信号组合成存储信号。在方框840中,在处理周期的结束时接收存储信号。在方框845中,在接收到存储信号时存储输出。在方框850中,使输出对输出端口有效。在方框855处,当输出有效时传输一中断信号,其中所述中断信号与处理时间周期的结束和非处理时间周期的开始一致。在方框860中,驱动处理电路以在非处理时间周期期间处理所述输入。在方框865中,在非处理时间周期期间接收来自处理电路的中间结果。在方框870中,在非处理时间周期期间维持输出的存储。
图9是一平整化数字逻辑模块中的电流消耗的方法。其中所述数字逻辑模块具有一处理电路,其经配置以接收一输入并在一处理时间周期期间处理所述输入以产生一输出。产生输出后是一非处理时间周期,其中所述处理电路进一步经配置以在处理时间周期期间得出电流的运行范围,并在非处理时间周期期间得出电流的非运行范围。在方框900中,使用一起始信号来触发所述处理周期的开始。在方框910中,跟踪所述处理时间周期。在方框920中,在处理时间周期的结束时产生一末循环信号。在方框930中,在处理时间周期结束时产生一存储信号。在方框940中,在处理时间周期的结束时存储所述输出。在方框950中,在非处理时间周期期间驱动所述处理电路。在方框960中,在非处理时间周期期间产生电流的运行范围。
所属领域的技术人员从上文描述并从图式和权利要求可认识到,在不脱离上文权利要求中所界定的本发明的范畴的情况下可对本发明作修改和改变。
Claims (12)
1.一种用于平整化一数字逻辑模块中的电流消耗的***,其包含:
一处理电路,其经配置以接收一输入并处理所述输入;
一计数器,其耦接到所述处理电路,且经配置以跟踪一处理时间周期,其中在所述处理时间周期期间,所述处理电路处理所述输入以产生一输出;
一输出端口,其耦接到所述处理电路,且经配置以传送所述输出,同时所述处理电路在一非处理时间周期期间继续运作,其中跟在所述处理时间周期之后的是所述非处理时间周期,所述非处理时间周期结束后便开始一新的处理时间周期;
一起始线,其耦接到所述计数器,且经配置以当所述输入对所述处理电路有效时而将一起始信号传送到所述计数器,其中所述起始信号触发所述处理时间周期的开始;
一中断线,其耦接到所述计数器,且经配置以当所述输出在所述输出端口有效时传送一来自所述计数器的中断信号,其中所述中断信号与所述处理时间周期的结束和所述非处理时间周期的开始一致;和
一存储电路,其耦接到所述输出端口,且经配置以在所述非处理时间周期期间存储所述输出并将所述输出传输到所述输出端口。
2.根据权利要求1所述的***,其中所述计数器进一步经配置以产生一指示所述处理时间周期的结束的末循环信号,所述末循环信号和所述起始信号组合形成一存储信号,和
其中所述存储电路经配置以在接收到所述存储信号时存储所述输出,且在所述非处理时间周期期间将所述输出传输到所述输出端口。
3.根据权利要求2所述的***,其中所述存储电路进一步包含:
一触发器,其耦接到所述输出端口,且经配置以在所述非处理时间周期期间将所述输出传输到所述输出端口;和
一多路器,其耦接到所述计数器、所述处理电路和所述触发器,且经配置以将所述输出传输到所述触发器且在接收到所述存储信号时将所述输出重新传输到所述触发器。
4.一种用于平整化一数字逻辑模块中的电流消耗的***,其中所述数字逻辑模块具有一处理电路,其经配置以接收一输入且在一处理时间周期期间处理所述输入以产生一输出,一非处理时间周期跟在所述输出的产生之后,所述处理电路进一步经配置以在所述处理时间周期期间得出一电流的运行范围并在所述非处理时间周期期间得出一电流的非运行范围,所述电流的运行范围不小于所述电流的非运行范围,所述***包含:
一平流电路,其耦接到所述处理电路,且经配置以使所述处理电路在所述非处理时间周期期间运作,且促使所述处理电路在所述非处理时间周期期间得出一电流的所述运行范围;
一计数器,其位于所述平流电路中,所述计数器耦合到所述处理电路并经配置以跟踪所述处理时间周期;
一存储电路,其耦接到所述处理电路,且经配置以在所述非处理时间周期期间存储所述输出;
一起始线,其耦接到所述计数器,且经配置以当所述输入对所述处理电路有效时将一起始信号传送到所述计数器,其中所述起始信号触发所述处理时间周期的开始;和
一中断线,其耦接到所述计数器,且经配置以当所述输出有效时传送一来自所述计数器的中断信号,其中所述中断信号与所述处理时间周期的结束和所述非处理时间周期的开始一致。
5.根据权利要求4所述的***,其中所述计数器进一步经配置以产生一指示所述处理时间周期的结束的末循环信号,所述末循环信号和所述起始信号组合形成一存储信号,和
其中所述存储电路经配置以在所述处理时间周期期间接收一来自所述处理电路的中间结果,接收所述存储信号且存储所述中间结果作为所述输出,其中在所述非处理时间周期期间,所述处理电路继续处理所述输入并产生所述电流的运行范围。
6.根据权利要求5所述的***,其中所述存储电路进一步经配置以在所述非处理时间周期期间接收所述中间结果并维持所述输出的存储。
7.一种平整化一数字逻辑模块中的电流消耗的方法,其中所述数字逻辑模块具有一耦接到一输出端口的处理电路,所述方法包含:
接收一输入;
驱动所述处理电路以在一处理时间周期期间处理所述输入;
从在所述处理时间周期期间经处理的所述输入得到一输出;
使所述输出对所述输出端口有效;
驱动所述处理电路以在一非处理时间周期期间处理所述输入;
使用一计数器来跟踪所述处理时间周期;
当所述输入有效时接收一起始信号;
触发所述处理时间周期的开始;
当所述输出有效时传输一中断信号,其中所述中断信号与所述处理时间周期的结束和所述非处理时间周期的开始一致;
产生一指示所述处理时间周期的结束的末循环信号;
将所述末循环信号和所述起始信号组合成一存储信号;
在所述处理周期结束时接收所述存储信号;
在接收到所述存储信号时存储所述输出。
8.根据权利要求7所述的方法,其进一步包含:
在所述非处理时间周期期间接收一来自所述处理电路的中间结果;和
在所述非处理时间周期期间维持所述输出的存储。
9.一种平整化一数字逻辑模块中的电流消耗的方法,其中所述数字逻辑模块具有一处理电路,其经配置以接收一输入且在一处理时间周期期间处理所述输入以产生一输出,产生所述输出后是一非处理时间周期,其中所述处理电路进一步经配置以在所述处理时间周期期间得出一电流的运行范围,并在一非处理时间周期期间得出一电流的非运行范围,所述方法包含:
在所述非处理时间周期期间驱动所述处理电路;
在所述非处理时间周期期间产生一电流的运行范围;
跟踪所述处理时间周期;
在所述处理时间周期结束时产生一末循环信号;
使用一起始信号来触发所述处理周期的开始;和
在所述处理时间周期结束时产生一存储信号。
10.根据权利要求9所述的方法,其进一步包含:
在所述处理时间周期结束时存储所述输出。
11.根据权利要求9所述的方法,其中在所述非处理时间周期期间驱动所述处理电路进一步包含:
在所述非处理时间周期期间处理所述输入。
12.根据权利要求9所述的方法,其进一步包含:
在所述非处理时间周期期间保存所述输出。
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US10/883,203 US6954866B2 (en) | 2003-07-17 | 2004-06-30 | Method and apparatus for smoothing current consumption in an integrated circuit |
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PCT/US2004/022626 WO2005010939A2 (en) | 2003-07-17 | 2004-07-12 | Method and apparatus for smoothing current consumption in an integrated circuit |
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TW200523750A (en) | 2005-07-16 |
CN1823275A (zh) | 2006-08-23 |
FR2857804B1 (fr) | 2006-05-26 |
US20050027471A1 (en) | 2005-02-03 |
FR2857804A1 (fr) | 2005-01-21 |
US6954866B2 (en) | 2005-10-11 |
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