CN1819579A - Open loop time delivering method - Google Patents

Abstract

The technical scheme is: a unified system is composed of multi time transfer chains; each time transfer chain consists of a master node, several switches and a slave node; SMAC are located in each switch and node; SMAC in master node generates synchronous frame, and broadcasts it to SMAC in slave node through the time transfer chain; the time transfer chain measures path time delay generated from transmission from SMAC in master node to SMAC in slave node; the path time delay is composed of the time delay of each chain and the time delay of each switch; the chain time delay is measured by using a measuring frame to take measurement at time of building a connection between a pair of SMAC; the switch time delay is measured by using a synchronous frame to take real-time measurement; the SMAC in slave node figures out its time warping with master node to implement correction of slave node time.

Description

Open loop time delivering method

Technical field

The present invention relates to have medium access control (MAC, Medium Access Controller) method that the time transmits in the layer network, especially each node time is required high occasion synchronously, as the method for time transmission in the network of industrial test environment and automated system.

Background technology

Network technology based on MAC has obtained develop rapidly and extensive use, for realizing the service application such as synchronism detection of different nodes, needs to realize in time unification between the node, especially with respect to the unification of standard sometime.At present, the time delivering method of network-oriented has occurred much NTP, SynUTC and IEEE 1588 etc. being arranged typically.NTP is the NTP (Network Time Protocol) towards wide area network and local area network (LAN), is operated in the transport layer of network, and generally in millisecond (ms) magnitude, the agreement time overhead is bigger for the time transmitting accuracy; SynUTC is operated in the MAC layer of Ethernet protocol, directly at media independent interface (MII, Medium Independent Interface) locates to realize time mark, best time transmitting accuracy reaches 100ns, attachment device need be installed, and end points need use MII-NTI (network time interface card) on switch; IEEE 1588 is operated in the MAC layer of Ethernet protocol, and the time transmitting accuracy can reach delicate (us) magnitude, need use 1588 boundary clock at the switch end, and end points uses 1588 clock modules.These, transmission method all was closed loop network time, promptly needed one independently to come and go and transmit the unidirectional delivery time delay that packet procedures comes synchronization frame estimated time, simultaneously agreement more complicated all.This has not only increased extra load to network, and because come and go that relays link is asymmetric, the network environment during latency measurement when transmitting with synchronization frame different and protocol overhead shake etc. make that the one-way delay measurement error is bigger, and these time delivering methods all do not provide the clock regeneration function, make to lack the standard time pulse signal as a reference in the synchronism detection of many sites, and then produce difficulty of Synchronous Sampling Pulse.Typical clock regeneration is in the synchronous pulse per second (PPS) clock signal of each node regeneration, i.e. 1PPS clock signal.

Summary of the invention

The technical problem to be solved in the present invention is that to transmit, time big at the time delivering method one-way delay measurement error of present closed loop reciprocal process complicated and can not provide synchronism detection required shortcomings such as clock regeneration function, a kind of independently open loop time delivering method of delivery lag measuring process that need not is proposed, to realize the time unification between each node of network, little to the network building-out load, and have the clock regeneration ability.

Technical scheme of the present invention is: form a timing system by many time transfer chains, article one, the time transfer chain is made up of from node 1 host node, 0 or a plurality of switching equipment and 1, equal configuration synchronization media access controller (SMAC, Synchronization Medium Access Controller) in switching equipment and the node.A node SMAC directly is connected with another node SMAC, or is connected with a SMAC of switching equipment, links to each other by a pair of SMAC between the switching equipment.The external time source of host node SMAC is for the time transfer chain provides the standard time.Host node SMAC produces the synchronization frame that is packaged with the standard time, and passes through the time transfer chain to broadcasting from node SMAC; The time transfer chain measure in real time synchronization frame by host node SMAC to the path delay of time that from node SMAC transmittance process, produces and be encapsulated in the synchronization frame to transmitting from node SMAC; Be made up of the switching delay of each section chain-circuit time delay and each switching equipment the path delay of time that produces in the synchronization frame transmittance process, the time delay that synchronization frame produces when being delivered to next SMAC by a SMAC through transmission line is a chain-circuit time delay, and synchronization frame exchanges the time delay that produces when handling in switching equipment be switching delay; Chain-circuit time delay adopts and measures frame local clock with each SMAC when a pair of SMAC connects is that benchmark is measured, and it is that benchmark is measured in real time with the local clock by switching equipment SMAC that switching delay adopts synchronization frame; Calculate time deviation Δ T with the host node time source standard time and the path delay of time by the synchronization frame transmission from node SMAC, realize correction from node time by this time deviation.

Use four kinds of time frames in the time transfer chain: measure frame, acknowledgement frame, synchronization frame and claim frame, measure frame and be used for the measure link time delay, the acknowledgement frame structure is identical with the measurement frame with type, distinguish by measuring the flag of frame word, be used for measuring replying of frame, synchronization frame is used for passing time, and the claim frame structure is identical with synchronization frame with type, distinguish by the synchronization frame banner word, what be used for the time transfer chain sends the request that produces synchronization frame from node to host node.

Measuring frame is the data transmission unit that meets concrete procotol frame structure, is used between two SMAC of direct interconnection measure link time delay when connecting.Measure frame except comprising the frame head information that meets network protocol standard, also comprise territory with time correlation, mainly contain frame type, measure the flag of frame word, measure frame ID, source node sends time stamp and frame is detained time delay, (frame is measured in difference to the type of frame type field mark present frame, synchronization frame and other frames), measure flag of frame word field mark frame type (frame and acknowledgement frame are measured in difference), measure frame ID territory and write down the sequence number of current measurement frame, source node sends the time stamp territory record time of frame when source node sends, and frame is detained the time delay domain record and enters the time delay that destination node SMAC is experienced from measuring frame when acknowledgement frame leaves.Source node S MAC success and destination node SMAC create and measure frame at the back that connects, and are that benchmark is filled and sent time stamp territory and initialization frame to be detained time delay domain be zero with the source node time when transmit frame.It is that benchmark calculate and fill with its local clock by destination node SMAC when sending the acknowledgement frame of measuring frame that frame is detained time delay domain.

Synchronization frame is the data transmission unit that meets concrete procotol frame structure, is used to transmit standard time information, measures switching delay and bang path time delay information.Synchronization frame also comprises the territory with time correlation except comprising the frame head information that meets network protocol standard, mainly contain frame type, synchronization frame banner word, synchronization frame ID, host node and send time stamp and frame path delay of time.The type of frame type field mark present frame (frame, synchronization frame and other frames are measured in difference), synchronization frame banner word territory is used for marker frame type (difference synchronization frame and claim frame), synchronization frame ID territory record is when the sequence number of preamble frame, host node sends the time stamp territory record time of frame when host node sends, and frame territory in the path delay of time is write down synchronization frame and is delivered to time delay information from node SMAC from host node SMAC.Synchronization frame produces when regularly being produced or being received from the node time synchronization request by host node SMAC, and fill to send the time stamp territory by SMAC and initialization frame territory in the path delay of time is zero when transmit frame; Frame territory in the path delay of time is calculated and is filled by the transmit port SMAC of SMAC switching equipment, is extracted at each receiving port SMAC.

Switching equipment is made up of exchange logic, some SMAC and time variable memory block.Each SMAC is positioned between exchange logic and the physical layer (PHY, Physical Layer), interconnects by bus interface with exchange logic, links to each other by the physical layer digital interface with PHY, and each SMAC also links to each other with the time variable memory block by bus interface simultaneously.Exchange logic achieve frame exchange, the transmitting-receiving of SMAC achieve frame and with the processing and the calculating of time correlation, time variable storage area stores temporal information is also shared between each SMAC.

SMAC is an integrated circuit, form by media access controller, time passing service unit, time mark processing unit, time synchronizing unit, clock regenerating signal unit and local clock processing unit, realize interconnection by bus interface or clock cable between each unit.Except having the medium access controlled function, also realize transmitting and unified relevant time transmission, time detecting and clock regeneration function and operation with the time in the physical layer digital interface.SMAC is upwards by bus interface and upper layer logic interconnection, downwards by physical layer digital interface and PHY interconnection.

Media access controller is the transmission medium access control circuit that meets concrete procotol, carry out media access and control protocol, the transmission of achieve frame and reception, it is by bus interface and upper layer logic and time passing service cell interconnection, by physical layer PHY (Physical Layer) digital interface (as AUI/MII/RMII/GMII etc.) and the interconnection of time mark processing unit.It is on the one hand from upper layer logic and time passing service unit receiving data frames and time frame (comprise and measure frame, acknowledgement frame, claim frame and synchronization frame), frame is carried out verification and calculates and line up processing, when waiting for link idle, pass to the time mark processing unit and carry out the frame transmission, the time of reception mark is handled the frame from PHY of unit forwards on the one hand, and all frames are passed to upper layer logic, time frame is passed to and time passing service unit.

Time passing service unit is a processor, it coordinates and manages the time transmittance process, the time service is provided, generation time transmits required measurement frame and synchronization frame, and calculate chain-circuit time delay and store SMAC status attribute and time variable, be connected with upper layer logic, media access controller, time mark processing unit and local clock processing unit by bus interface, form by frame service module, time service module and SMAC attribute variable district, be connected by bus interface between frame service module and time service module and the SMAC attribute variable district.Frame service module produces and measures frame, acknowledgement frame, synchronization frame and claim frame, and send to media access controller by data/address bus and media access controller interface, measures frame and produces when SMAC connects, and is used for the measure link time delay; Acknowledgement frame is used for the measurement frame that receives is replied; Synchronization frame produces when SMAC can regularly produce or receive claim frame from node during as host node, be used to realize the standard time by host node to measuring from the node transmission and to switching delay; Claim frame can regularly produce as from node the time at SMAC, to realize sending synchronization frame to the host node request.The time service module links to each other with upper layer logic, local clock processing unit, time mark processing unit by bus interface, receives the time service request of upper layer logic, reads the current time from the local clock processing unit and replys; The time stab information that this module is extracted from acknowledgement frame according to the time mark processing unit calculates chain-circuit time delay Δ τ _Link, and store in the SMAC attribute variable district; For the SMAC that is operated in the switching equipment, this module is gone back the time stab information that time of reception mark processing unit extracts simultaneously from synchronization frame, stores into by bus interface in the time variable memory block of switching equipment.SMAC attribute variable district is the register of store configuration information and temporal information, the information of configuration information such as the time interval that memory node role, synchronization frame produce and Link State and chain-circuit time delay and time stab information etc. and time correlation; It by bus interface receive configuration information from upper layer logic, the time stab information that extracts from the time mark processing unit and from the chain-circuit time delay information of time service module, and provide configuration information and temporal information access interface to upper layer logic and frame service module.Transmission time stamp in the time stab information of supposing to extract in the acknowledgement frame and delay time delay are TS _{Send out}With Δ τ _Stay, the reception time stamp that receives acknowledgement frame is TS _Receive, chain-circuit time delay Δ τ then _LinkEqual to come and go half of link propagation delay, that is:

Δ τ _Link=(TS _Receive-TS _{Send out}-Δ τ _Stay)/2.

The time mark processing unit is a processor, it is from the media access controller received frame, detect to measure frame, acknowledgement frame and synchronization frame and mark transmitting-receiving time stamp, extract in the frame time stab information and in frame, insert time stab information, by sending the certification mark module, receiving certification mark module and verification and computing module and form.This unit is on the physical layer digital interface between media access controller and the PHY, be connected with PHY with media access controller by the physical layer digital interface, be connected with time passing service unit, time synchronizing unit and local clock processing unit by bus interface simultaneously.Send the certification mark module from the media access controller received frame, detect and measure frame, acknowledgement frame and synchronization frame, insert the transmission time stamp for measuring the new synchronization frame that produces of frame and current SMAC, calculate and insert the delay time delay for acknowledgement frame, then calculate and insert the path delay of time for the synchronization frame in transmission and the exchange; Verification and computing module to send the certification mark module inserted the frame of time stab information recomputate verification and, send to PHY; Receive the certification mark module and detect measurement frame, acknowledgement frame and the synchronization frame that receives from PHY, the reception time stamp of record frame, extract time stab information in the frame (comprising that the source node of measuring in the frame sends source node in time stamp, the acknowledgement frame and sends time stamp and frame and be detained host node in time delay and the synchronization frame and send time stamp and frame path delay of time), and the time stab information of extraction is passed to time passing service unit and time synchronizing unit by bus interface.The transmitting-receiving time stamp is from time that the local clock processing unit reads by bus interface.The time mark processing unit is directly transmitted Frame and is left intact.

The time synchronizing unit be one by pulse signal producer, pulse register and 2 logical circuits that adder is formed constantly, calculating path time delay and compensation deals time delay, the clock signal of generation and time source time synchronized, it is connected with time mark processing unit, clock regenerating signal unit and local clock processing unit by bus interface.The chain-circuit time delay of storage in the path delay of time and the time passing service cell S MAC attribute variable district in the synchronization frame that first adder time of reception mark processing unit extracts, give pulse signal producer and second adder the path delay of time that calculates the synchronization frame transmission: suppose that chain-circuit time delay is Δ τ _Link, be Δ τ the path delay of time of extraction _Path1, the Δ τ in the path delay of time that calculates of first adder then _Path2Be the path delay of time and the chain-circuit time delay sum of extracting, that is:

Δτ _path2＝Δτ _path1+Δτ _link

Pulse signal producer is a pulse signal generating circuit, is receiving the Δ τ in the path delay of time that first adder calculates _Path2The time produce a pulse signal, this pulse signal is outwards exported to clock regenerating signal unit and local clock processing unit as lock-out pulse, passes to pulse register constantly simultaneously.

Pulse register constantly is a recording impulse rising edge circuit constantly, from pulse signal producer received pulse signal, and from local clock processing unit extraction pulse signal rising edge time information T _NodePass to second adder.

The pulse signal rising edge time information T of second adder received pulse recorder trace constantly _Node, the Δ τ in the path delay of time that calculates of first adder _Path2And the synchronization frame of time mark processing unit mark receives time stamp TS _ReceiveSend time stamp TS with the host node that from synchronization frame, extracts _{The source}, calculate T lock in time _{Synchronously}(sending time stamp, the path delay of time and processing delay sum):

T _{Synchronously}=TS _{The source}+ Δ τ _Path2+ (T _Node-TS _Receive)

Wherein, T _Node-TS _ReceiveFor time mark processing unit mark synchronization frame produces the processing delay that produces during the synchronization pulse to pulse signal producer.

T _{Synchronously}Be the synchronization pulse rising edge moment that is synchronized with the host node time source time, this time information is exported to clock regenerating signal unit and local clock processing unit with lock-out pulse as synchronizing clock signals.

The clock regenerating signal unit is a logical circuit that postpones the output pulse, produces pulse per second (PPS) and strobe pulse signal, synchronizing clock signals by the generation of bus interface time of reception synchronous processing unit, carry out after a whole second delay compensation and an empty second signal fill up, the 1PPS clock signal of regeneration and host node time source time synchronized, filling up module by processor, whole second delay compensation module and an empty second signal forms, it is connected with the time synchronizing unit by bus interface, is connected with the local clock processing unit by clock cable.Processor is the nucleus module of this unit, coordinates a whole second delay compensation module and an empty second signal and fills up that module is finished whole second delay compensation and an empty second signal is filled up, and it receives T lock in time in the synchronizing clock signals by bus interface _{Synchronously}, the clock pulse frequency according to the output of local clock processing unit calculates T _{Synchronously}Give whole second delay compensation module and calculate a whole second pairing whole second comparison value with respect to the whole second pairing time delay comparison value of time difference constantly of the nearest next one and fill up module for an empty second signal; The delay compensation module was a time delay circuit of being made up of counter and comparator in whole second, synchronizing clock signals by the generation of bus interface time of reception synchronous processing unit, non-whole second alignment synchronization pulse carried out delay compensation, produce whole second alignment clock pulse and send to an empty second time signal and fill up module; It is that a local pulse per second (PPS) generation and pulse signal are selected circuit that an empty second signal is filled up module, and the local pps pulse per second signal of regenerating is filled up back output 1PPS clock signal to the pulse per second (PPS) of vacancy.

The local clock processing unit is the circuit of generation time information and clock pulse, is made up of timing module, frequency multiplication module and time correcting module.It is connected with external crystal-controlled oscillation or time source (as GPS) by clock line, is connected with time passing service unit, time synchronizing unit and time mark processing unit by bus interface, is connected with the clock regenerating signal unit by clock cable.Timing module is a timer, its receive external crystal-controlled oscillation after frequency multiplication module frequency multiplication clock pulse or the clock pulse of time source, carry out timing generation time information and export to time mark processing unit and time synchronizing unit.External crystal-controlled oscillation produces clock pulse signal after by frequency multiplication module frequency multiplication and exports to the clock regenerating signal unit; The time correcting module is by the time signal synchronous with time source of bus interface time of reception synchronous processing unit output, calculate the deviation of node with respect to the host node time source time, by the parameter of frequency multiplication module is controlled, realize correction to local zone time.The present node clock equals the time T of time synchronizing unit pulse recorder trace constantly with respect to the deviation delta T of host node time source time _NodeDeduct T lock in time _{Synchronously}, that is:

Δ T=T _Node-T _{Synchronously}

Host node SMAC regularly produces synchronization frame or according to producing at the synchronization frame from node from the request of node SMAC, in the frame transmitting time relevant with temporal information and the path delay of time two territories be both initialized to zero.Then, the time mark processing unit by host node SMAC inserts transmission time stamp TS in the transmitting time territory of synchronization frame _{The source is sent out}, and calculation check and after frame is sent.

The time transfer chain measure in real time synchronization frame by host node SMAC to the path delay of time that from node SMAC transmittance process, produces.

Inlet SMAC chain-circuit time delay and the switching delay of supposing i switching equipment of time transfer chain are Δ τ _{Acceptance, link} ⁱWith Δ τ _Exchange ⁱ, the purpose of time transfer chain is Δ τ from node SMAC chain-circuit time delay _{Purpose, link}, the Δ τ in the path delay of time of the outlet SMAC of the 1st of synchronization frame elapsed time transfer chain the switching equipment then _{Hand over and send out path} ¹Equal this switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ¹With switching delay Δ τ _Exchange ¹Sum, that is:

The Δ τ in the path delay of time of the outlet SMAC of i switching equipment of synchronization frame elapsed time transfer chain _{Hand over and send out path} ⁱEqual the Δ τ in the path delay of time of i-1 switching equipment outlet SMAC _{Acceptance, path} ^I-1, an i switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ⁱWith switching delay Δ τ _Exchange ⁱSum, that is:

Synchronization frame is delivered to the Δ τ in the path delay of time of outlet SMAC of last (N) switching equipment of time transfer chain _{Hand over and send out path} ^NEqual the Δ τ in the path delay of time of N-1 switching equipment outlet SMAC _{Acceptance, path} ^N-1, a N switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ^NWith switching delay Δ τ _Exchange ^NSum, that is:

When then synchronization frame is delivered to from node SMAC, the Δ τ in the path delay of time that is produced _PathEqual the Δ τ in the path delay of time of the outlet SMAC of last (N) switching equipment _{Hand over and send out path} ^NWith from node SMAC chain-circuit time delay Δ τ _{From, link}Sum, that is:

The path delay of time is along with the transmission of synchronization frame in the time transfer chain, adds up piecemeal and calculates in real time, when being delivered to from node, promptly obtaining synchronization frame and is delivered to entire path time delay Δ τ from node SMAC by host node SMAC _Path

Chain-circuit time delay is that benchmark is measured with the local clock of each SMAC when each connects to SMAC.Detailed process is: source node (producing the node of measuring frame) SMAC produces and sends chain-circuit time delay and measures frame, is inserted by the time mark processing unit and sends time stamp TS _{The source is sent out}, and calculation check and this measurement frame of back transmission; After destination node (receiving and reply the node of measuring frame) SMAC detects this measurement frame, be that reference recording receives time stamp TS with the local clock by the time mark processing unit _{Order is received}By directly returning after the head exchange of time passing service unit to the measurement frame, be that reference recording sends time stamp TS with the local clock by the time mark processing unit as acknowledgement frame _{Order is sent out}, and calculate the delay time delay Δ τ of frame in SMAC _Stay, being inserted in the acknowledgement frame, transmit to source node S MAC calculation check and back.Can get the delay time delay Δ τ of frame in destination node SMAC thus _Stay:

Δ τ _Stay=TS _{Order is sent out}-TS _{Order is received}

Source node S MAC receives acknowledgement frame, is that reference recording receives time stamp TS with the local clock by the time mark processing unit _{Receive in the source}, and extract the transmission time stamp TS that writes down in the frame _{The source is sent out}With the delay time delay Δ τ of frame in destination node SMAC _Stay, calculate the chain-circuit time delay Δ τ of source node S MAC to destination node SMAC _LinkBasic parameter as SMAC is stored in the SMAC attribute variable district of time passing service unit by time passing service unit.Chain-circuit time delay Δ τ _LinkFor:

Because come and go the link symmetry, the chain-circuit time delay certainty of measurement can reach the precision same with local clock.

Switching delay is that benchmark is measured in real time with the local clock by switching equipment.Detailed process is: synchronization frame behind the link between the switching equipment that links to each other, enters a certain port SMAC of switching equipment through host node, detects synchronization frame by the time mark processing unit, and is that reference recording receives time stamp TS with the local clock of switching equipment _{Hand over, receive}, extract in the frame Δ τ in the path delay of time _{Acceptance, path}And be stored in chain-circuit time delay Δ τ in the time passing service cell S MAC attribute variable district _{Acceptance, link}, with reception time stamp TS _{Hand over, receive}Store in the time variable memory block of switching equipment by time passing service unit together; When switching equipment has exchanged synchronization frame and leaves a certain port SMAC, detect and the transmission time stamp TS of record synchronization frame by the time mark processing unit _{Hand over, send out}, receive time stamp TS according to the synchronization frame that writes down in the switching equipment time variable memory block again _{Hand over, receive}, the path delay of time Δ τ _{Acceptance, path}Chain-circuit time delay Δ τ with receiving port SMAC _{Acceptance, link}The Δ τ in the path delay of time that calculating makes new advances _{Hand over and send out path}, the path delay of time that is inserted into frame is in the territory, and calculation check and after, continue to transmit synchronization frame.Switching delay Δ τ _ExchangeEqual synchronization frame and send time stamp TS _{Hand over, send out}Deduct synchronization frame and receive time stamp TS _{Hand over, receive}, that is:

Δ τ _Exchange=TS _{Hand over, send out}-TS _{Hand over, receive}

Switching delay is that benchmark is measured in real time with the switching equipment local clock, and its precision can reach the precision same with the switching equipment local clock.

When node SMAC receives synchronization frame, be that the reference recording synchronization frame receives time stamp TS with the local clock by the time mark processing unit _Receive, and from frame, extract the transmission time stamp TS of frame _{The source}With Δ τ in the path delay of time _Path1, calculate time T with the time source time synchronized by the time synchronizing unit _{Synchronously}, the time correcting module of local clock processing unit calculates the deviation delta T with respect to the host node time source time, can realize the time synchronized with host node directly to carrying out time adjustment from node according to this time deviation.

Since synchronization frame by host node to real-time implementation from the node transmittance process measurement in the path delay of time, when receiving synchronization frame, just can proofread and correct the deadline and clock regeneration node, do not need an independently delivery lag measuring process, so be open loop based on the SMAC time delivering method.Adopt this open loop time delivering method, the host node standard time is delivered to all from node, has realized having the time unification that multinode network is the time integrated system.

Because the clock short-term stability is good, the error of measuring intervals of TIME is little, chain-circuit time delay of the present invention and switching delay are based on all that the local clock of node or switching equipment measures, and are far smaller than time delays itself such as path, exchange and delay based on each local clock latency measurement error.

Adopt the present invention can produce following technique effect:

1. adopt the open loop approach realization time to transmit, do not need independent latency measurement process, few to the network building-out load;

2. because the SMAC that adopts can the network-oriented test provide regeneration pulse per second (PPS) clock signal, therefore can realize the multinode synchronous data collection;

3. for the network that links to each other by a switching equipment, clock frequency stability≤10 of switching equipment and node configuration ^-9The time, can realize each timing tracking accuracy from ten nanosecond orders between the node.

Description of drawings

Fig. 1 is IEEE 1588 a time transmission system system assumption diagram.

Fig. 2 is IEEE 1588 independent latency measurement process schematic diagrames.

Fig. 3 is a SMAC open loop time transfer chain schematic diagram of the present invention.

Fig. 4 is a SMAC building-block of logic of the present invention.

Fig. 5 is a SMAC time passing service cellular logic structure chart of the present invention.

Fig. 6 is a SMAC time mark processing unit building-block of logic of the present invention.

Fig. 7 is a SMAC time synchronizing cellular logic structure chart of the present invention.

Fig. 8 is a SMAC clock regenerating signal cellular logic structure chart of the present invention.

Fig. 9 is a SMAC local clock processing unit building-block of logic of the present invention.

Figure 10 handles schematic diagram the SMAC time of the present invention.

Figure 11 is a SMAC switching equipment structural representation of the present invention.

Figure 12 is the local area network (LAN) timing system structure chart that adopts the present invention to set up

Figure 13 adopts the present invention to carry out the flow chart that the local area network (LAN) chain-circuit time delay is measured.

Figure 14 adopts the present invention to carry out the flow chart of local area network (LAN) open loop time transmission.

Figure 15 is that the Ethernet SMAC that the present invention uses measures frame assumption diagram.

Figure 16 is the Ethernet SMAC synchronous frame stucture figure that the present invention uses.

Embodiment

Fig. 1 is IEEE 1588 clock synchronization system architectural schematic.This clock synchronization system is made up of IEEE 1588 switches and a plurality of IEEE 1588 timing nodes.Dispose boundary clock in the switch, it is synchronized with the main website clock, simultaneously again as the master clock from station clock.The time bag of IEEE 1588 clock synchronization systems does not exchange transmission by switch, but realizes the time transmission of each timing node by boundary clock.IEEE 1588 clock synchronization systems divide carries out synchronizing process in two steps: at first, correct the time difference (being offset measurement) between main website and the slave station.When correcting skew, main website sends a sync message that comprises the correct time estimated value circularly, and this message sends to relevant slave station at a fixed time at interval.Then, slave station sends one to main website and postpones request package, measures delay or wait between slave station and the main website.IEEE 1588 clock synchronization systems are fit to the time transmission of underload Ethernet, adopt boundary clock to avoid the uncertain switching delay of switch.But independently the latency measurement process is carried out the time delay correction when split-second precision transmits.

Fig. 2 is the independent latency measurement process schematic diagram of IEEE 1588.Slave station sends one to main website and postpones request package, determines to send the correct time of message in this process.Main website generates a time stamp when accepting request bag, in " delayed response " bag time of reception is beamed back slave station then.Slave station utilizes these time stamps to calculate time of delay between slave station and main website.Latency measurement is a feedback procedure of offset measurement, therefore, and closed loop time transfer mode during IEEE 1588 clock synchronization systems.

Fig. 3 is a SMAC open loop time transfer chain schematic diagram of the present invention.Article one, the time transfer chain is by the host node of 1 configuration SMAC, 0 or the switching equipment of a plurality of configuration SMAC and forming from node of 1 configuration SMAC.A node SMAC directly is connected with another node SMAC, or is connected with a SMAC of switching equipment, links to each other by a pair of SMAC between the switching equipment.The external time source of host node SMAC is for the time transfer chain provides the standard time.Host node SMAC produces the synchronization frame that is packaged with the standard time, and passes through the time transfer chain to broadcasting from node SMAC; The time transfer chain measure in real time synchronization frame by host node SMAC to the path delay of time that from node SMAC transmittance process, produces and be encapsulated in the synchronization frame to transmitting from node SMAC; Be made up of the switching delay of each section chain-circuit time delay and each switching equipment the path delay of time that produces in the synchronization frame transmittance process, chain-circuit time delay adopts the measurement frame to measure when a pair of SMAC connects, and switching delay adopts synchronization frame to be measured in real time by switching equipment SMAC.Calculate time deviation with the host node time source standard time and the path delay of time by the synchronization frame transmission from node SMAC, realize correction from node time by this time deviation.

Inlet SMAC chain-circuit time delay and the switching delay of supposing i switching equipment of time transfer chain are Δ τ _{Acceptance, link} ⁱWith Δ τ _Exchange ⁱ, the purpose of time transfer chain is Δ τ from node SMAC chain-circuit time delay _{Purpose, link}, the Δ τ in the path delay of time of the outlet SMAC of the 1st of synchronization frame elapsed time transfer chain the switching equipment then _{Hand over and send out path} ¹Equal this switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ¹With switching delay Δ τ _Exchange ¹Sum, that is:

The Δ τ in the path delay of time of the outlet SMAC of i switching equipment of synchronization frame elapsed time transfer chain _{Hand over and send out path} ⁱEqual the Δ τ in the path delay of time of i-1 switching equipment outlet SMAC _{Acceptance, path} ^I-1, an i switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ⁱWith switching delay Δ τ _Exchange ⁱSum, that is:

Synchronization frame is delivered to the Δ τ in the path delay of time of outlet SMAC of last (N) switching equipment of time transfer chain _{Hand over and send out path} ^NEqual the Δ τ in the path delay of time of N-1 switching equipment outlet SMAC _{Acceptance, path} ^N-1, a N switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ^NWith switching delay Δ τ _Exchange ^NSum, that is:

When then synchronization frame is delivered to from node SMAC, the Δ τ in the path delay of time that is produced _PathEqual the Δ τ in the path delay of time of the outlet SMAC of last (N) switching equipment _{Hand over and send out path} ^NWith from node SMAC chain-circuit time delay Δ τ _{From, link}Sum, that is:

The path delay of time is along with the transmission of synchronization frame in the time transfer chain, adds up piecemeal and calculates in real time, when being delivered to from node, promptly obtaining synchronization frame and is delivered to entire path time delay Δ τ from node SMAC by host node SMAC _Path

Fig. 4 is a SMAC building-block of logic of the present invention.SMAC is an integrated circuit, form by media access controller, time passing service unit, time mark processing unit, time synchronizing unit, clock regenerating signal unit and local clock processing unit, realize interconnection by bus interface or clock cable between each unit.Except having the medium access controlled function, also realize transmitting and unified relevant time transmission, time detecting and clock regeneration function and operation with the time in the physical layer digital interface.SMAC is upwards by bus interface and upper layer logic interconnection, downwards by physical layer digital interface and PHY interconnection.

Media access controller is the transmission medium access control circuit that meets concrete procotol, carries out media access and control protocol, the transmission of achieve frame and reception.This unit is by bus interface and upper layer logic and time passing service cell interconnection, by physical layer digital interface and the interconnection of time mark processing unit.It is on the one hand from upper layer logic and time passing service unit receiving data frames and time frame (comprise and measure frame, acknowledgement frame, claim frame and synchronization frame), frame is carried out verification and calculates and line up processing, when waiting for link idle, pass to the time mark processing unit and carry out the frame transmission, the time of reception mark is handled the frame from PHY of unit forwards on the one hand, and all frames are passed to upper layer logic, time frame is passed to and time passing service unit.Time passing service unit is a processor, it coordinates and manages the time transmittance process, the time service is provided, generation time transmits required measurement frame and synchronization frame, and calculation delay and storage SMAC status attribute and time variable, be connected with upper layer logic, media access controller, time mark processing unit and local clock processing unit by bus interface.The time mark processing unit is a processor, it is from the media access controller received frame, detect to measure frame, acknowledgement frame and synchronization frame and mark transmitting-receiving time stamp, extract in the frame time stab information and in frame, insert time stab information, it is on the physical layer digital interface between media access controller and the PHY, be connected with PHY with media access controller by the physical layer digital interface, be connected with time passing service unit, time synchronizing unit and local clock processing unit by bus interface simultaneously.Time synchronizing unit calculating path time delay and compensation deals time delay, the clock signal of generation and time source time synchronized, it is connected with time mark processing unit, clock regenerating signal unit and local clock processing unit by bus interface.The clock regenerating signal unit is a logical circuit that postpones the output pulse, produces pulse per second (PPS) and strobe pulse signal, synchronizing clock signals by the generation of bus interface time of reception synchronous processing unit, carry out after a whole second delay compensation and an empty second signal fill up, the 1PPS clock signal of regeneration and host node time source time synchronized, it is connected with the time synchronizing unit by bus interface, is connected with the local clock processing unit by clock cable.The local clock processing unit is the circuit of generation time information and clock pulse, it is connected with external crystal-controlled oscillation or time source (as GPS) by clock line, be connected with time passing service unit, time synchronizing unit and time mark processing unit by bus interface, be connected with the clock regenerating signal unit by clock cable.

Fig. 5 is a SMAC time passing service cellular logic structure chart of the present invention.Time passing service unit is a processor, it coordinates and manages the time transmittance process, the time service is provided, generation time transmits required measurement frame and synchronization frame, and calculation delay and storage SMAC status attribute and time variable, be connected with upper layer logic, media access controller, time mark processing unit and local clock processing unit by bus interface, form by frame service module, time service module and SMAC attribute variable district, be connected by bus interface between frame service module and time service module and the SMAC attribute variable district.Frame service module is process of processor, by data/address bus and media access controller interface, produce and measure frame, acknowledgement frame, synchronization frame and claim frame, and send to media access controller, measure frame and when SMAC connects, produce, be used for the measure link time delay; Acknowledgement frame is used for the measurement frame that receives is replied; Synchronization frame produces when SMAC can regularly produce or receive claim frame from node during as host node, be used to realize the standard time by host node to measuring from the node transmission and to switching delay; Claim frame can regularly produce as from node the time at SMAC, to realize sending synchronization frame to the host node request.The time service module is another process of processor, link to each other with upper layer logic, local clock processing unit, time mark processing unit by bus interface, receive the time service request of upper layer logic, read the current time from the local clock processing unit and reply; This module calculates chain-circuit time delay according to the time stab information that the time mark processing unit extracts from acknowledgement frame, and stores in the SMAC attribute variable district; For the SMAC that is operated in the switching equipment, this module is gone back the time stab information that time of reception mark processing unit extracts simultaneously from synchronization frame, stores into by bus interface in the time variable memory block of switching equipment.SMAC attribute variable district is the register of store configuration information and temporal information, the information of configuration information such as the time interval that memory node role, synchronization frame produce and Link State and chain-circuit time delay and time stab information etc. and time correlation; It by bus interface receive configuration information from upper layer logic, the time stab information that extracts from the time mark processing unit and from the chain-circuit time delay information of time service module, and provide configuration information and temporal information access interface to upper layer logic and frame service module.Transmission time stamp in the time stab information of supposing to extract in the acknowledgement frame and delay time delay are TS _{Send out}With Δ τ _Stay, the reception time stamp that receives acknowledgement frame is TS _Receive, chain-circuit time delay Δ τ then _LinkEqual to come and go half of link propagation delay, that is:

Δ τ _Link=(TS _Receive-TS _{Send out}-Δ τ _Stay)/2

Fig. 6 is a SMAC time mark processing unit building-block of logic of the present invention.The time mark processing unit is a processor, it is from the media access controller received frame, detect to measure frame, acknowledgement frame and synchronization frame and mark transmitting-receiving time stamp, extract in the frame time stab information and in frame, insert time stab information, by sending the certification mark module, receiving certification mark module and verification and computing module and form.This unit is on the physical layer digital interface between media access controller and the PHY, be connected with PHY with media access controller by the physical layer digital interface, be connected with time passing service unit, time synchronizing unit and local clock processing unit by bus interface simultaneously.Send the certification mark module from the media access controller received frame, detect and measure frame, acknowledgement frame and synchronization frame, insert the transmission time stamp for measuring the new synchronization frame that produces of frame and current SMAC, calculate and insert the delay time delay for acknowledgement frame, then calculate and insert the path delay of time for the synchronization frame in transmission and the exchange; Verification and computing module to send the certification mark module inserted the frame of time stab information recomputate verification and, send to PHY; Receive the certification mark module and detect measurement frame, acknowledgement frame and the synchronization frame that receives from PHY, the reception time stamp of record frame, extract time stab information in the frame (comprising that the source node of measuring in the frame sends source node in time stamp, the acknowledgement frame and sends time stamp and frame and be detained host node in time delay and the synchronization frame and send time stamp and frame path delay of time), and the time stab information of extraction is passed to time passing service unit and time synchronizing unit by bus interface.The transmitting-receiving time stamp is from time that the local clock processing unit reads by bus interface.The time mark processing unit is directly transmitted Frame and is left intact.

Fig. 7 is a SMAC time synchronizing cellular logic structure chart of the present invention.The time synchronizing unit be one by pulse signal producer and 2 logical circuits that adder is formed, calculating path time delay and compensation deals time delay, the clock signal of generation and time source time synchronized, it is connected with time mark processing unit, clock regenerating signal unit and local clock processing unit by bus interface.The chain-circuit time delay of storage in the path delay of time and the time passing service cell S MAC attribute variable district in the synchronization frame that first adder time of reception mark processing unit extracts, give pulse signal producer and second adder the path delay of time that calculates the synchronization frame transmission: suppose that chain-circuit time delay is Δ τ _Link, be Δ τ the path delay of time of extraction _Path1, the Δ τ in the path delay of time that calculates of first adder then _Path2Be the path delay of time and the chain-circuit time delay sum of extracting, that is:

Δτ _path2＝Δτ _path1+Δτ _link

Pulse signal producer is that a pulse signal produces and recording impulse rising edge circuit constantly, is receiving the Δ τ in the path delay of time that first adder calculates _Path2The time produce a pulse signal, and extract pulse signal rising edge time information T from the local clock processing unit _Node, this pulse signal is outwards exported to clock regenerating signal unit and local clock processing unit as lock-out pulse, with T _NodePass to second adder.

The pulse signal rising edge time information T of second adder received pulse signal generator record _Node, the Δ τ in the path delay of time that calculates of first adder _Path2And the synchronization frame of time mark processing unit mark receives time stamp TS _ReceiveSend time stamp TS with the host node that from synchronization frame, extracts _{The source}, calculate T lock in time _{Synchronously}(sending time stamp, the path delay of time and processing delay sum):

T _{Synchronously}=TS _{The source}+ Δ τ _Path2+ (T _Node-TS _Receive)

Wherein, T _Node-TS _ReceiveFor time mark processing unit mark synchronization frame produces the processing delay that produces during the synchronization pulse to pulse signal producer.

T _{Synchronously}Be the synchronization pulse rising edge moment that is synchronized with the host node time source time, this time information is exported to clock regenerating signal unit and local clock processing unit with lock-out pulse as synchronizing clock signals.

Fig. 8 is a SMAC clock regenerating signal cellular logic structure chart of the present invention.The clock regenerating signal unit is a logical circuit that postpones the output pulse, produces pulse per second (PPS) and strobe pulse signal, synchronizing clock signals by the generation of bus interface time of reception synchronous processing unit, carry out after a whole second delay compensation and an empty second signal fill up, the 1PPS clock signal of regeneration and host node time source time synchronized, by whole second delay compensation module, an empty second signal fills up module and processor is formed, it is connected with the time synchronizing unit by bus interface, is connected with the local clock processing unit by clock cable.

Processor is by T lock in time in the bus interface reception synchronizing clock signals _{Synchronously}, the clock pulse frequency according to the output of local clock processing unit calculates T _{Synchronously}Give whole second delay compensation module with respect to the whole second pairing time delay comparison value of time difference constantly of the nearest next one, and calculate a whole second pairing whole second comparison value and fill up module for an empty second signal; Simultaneously, in current second, whether receive T lock in time _{Synchronously}, generation is filled up enable signal and is filled up module for an empty second signal.Processor receives the 1PPS clock signal that empty second signal is filled up module output by holding wire, whenever receive a 1PPS pulse after, fill up enable signal again and judge, receiving T lock in time _{Synchronously}The time for filling up invalid, do not receive T lock in time _{Synchronously}The time for filling up effective.

The delay compensation module was a pulse daley output circuit in whole second, synchronizing clock signals by the generation of bus interface time of reception synchronous processing unit, non-whole second alignment synchronization pulse carried out delay compensation, produce whole second alignment clock pulse and send to an empty second signal and fill up module.

It is that a local pulse per second (PPS) generation and pulse signal are selected circuit that an empty second signal is filled up module, receive whole second alignment clock pulse of delay compensation module generation in whole second by holding wire, and the clock pulse that receives the output of local clock processing unit by clock cable, be used for filling up whole second signal of whole second alignment clock pulse vacancy, produce 1PPS clock signal and time information with the host node time synchronized.This module with the clock pulse of local clock processing unit output as count pulse, the whole second comparison value counting that transmits by bus interface according to processor produces pulse per second (PPS), when processor is filled up enable signal when filling up effective by the holding wire transmission, select whole second alignment clock pulse as output, realize filling up of whole second signal of vacancy, Shu Chu pulse signal is the 1PPS clock signal at last.

Fig. 9 is a SMAC local clock processing unit building-block of logic of the present invention.The local clock processing unit is the circuit of generation time information and clock pulse, is made up of timing module, 2 frequency multiplication modules and time correcting module.It is connected with external crystal-controlled oscillation or time source (as GPS) by clock line, is connected with time passing service unit, time synchronizing unit and time mark processing unit by bus interface, is connected with the clock regenerating signal unit by clock cable.Timing module is a timer, its receive external crystal-controlled oscillation after frequency multiplication module frequency multiplication clock pulse or the clock pulse of time source, carry out timing generation time information and export to time mark processing unit and time synchronizing unit.External crystal-controlled oscillation is exported to the clock regenerating signal unit by frequency multiplication module back generation frequently clock pulse signal; The time correcting module is by the time signal synchronous with time source of bus interface time of reception synchronous processing unit output, calculate the deviation of node with respect to the host node time source time, by the parameter of frequency multiplication module is controlled, realize correction to local zone time.The present node clock equals the time T of time synchronizing unit pulse recorder trace constantly with respect to the deviation delta T of host node time source time _NodeDeduct T lock in time _{Synchronously}, that is:

Δ T=T _Node-T _{Synchronously}

Figure 10 handles schematic diagram the SMAC time of the present invention.The time synchronizing unit is that produce constantly not to align with time source with pulse signal host node time source time synchronized in whole second; Synchronization pulse through the whole second delay compensation in clock regenerating signal unit after, produces whole second alignment clock pulse, but a vacancy pulse per second (PPS) occurred with respect to the 3rd second moment of time source; After the alignment clock pulse was filled up through the empty second signal in clock regenerating signal unit in whole second, produce the synchronous 1PPS signal that constantly alignd in whole second with time source.

Figure 11 is a SMAC switching equipment structural representation of the present invention.Switching equipment is the frame crosspoint in the time transfer chain, is made up of exchange logic, some SMAC and time variable memory block.Each SMAC interconnects by bus interface with exchange logic between exchange logic and physical layer, links to each other by the physical layer digital interface with PHY, and each SMAC also links to each other with the time variable memory block by bus interface simultaneously.Exchange logic is to meet logical block procotol, that achieve frame exchanges between each SMAC, the transmitting-receiving of SMAC achieve frame and with the processing and the calculating of time correlation, time variable storage area stores temporal information is also shared between each SMAC.

Figure 12 is the local area network (LAN) timing system structure chart that adopts the present invention to set up, and this timing system is made up of node and the switching equipment of configuration SMAC, passes through network system of the interconnected one-tenth of switching equipment between the node.Node SMAC is between IP layer and PHY, and switching equipment SMAC is between exchange logic and PHY.Node is by 1 host node and a plurality ofly form from node, and the external standard time source of host node is as all time references from node.The time unification process of whole system is all at the MAC layer, realize and finish with open loop time delivering method.

Figure 13 adopts the present invention to carry out the flow chart that the local area network (LAN) chain-circuit time delay is measured.The medium access control unit of source node S MAC produces chain-circuit time delay measurement frame and sends to the time mark processing unit, and the time mark processing unit inserts in the physical layer digital interface and sends time stamp TS _{The source is sent out}, calculation check and back send measures frame; Destination node SMAC time mark processing unit detect to be measured frame and is that reference recording receives time stamp TS by the time mark processing unit with the local clock in the physical layer digital interface _{Order is received}Time passing service unit directly returns as acknowledgement frame after the head of measuring frame is exchanged, and is that reference recording sends time stamp TS with the local clock by the time mark processing unit _{Order is sent out}, calculate and be detained time delay Δ τ _Stay, Δ τ _Stay=TS _{Order is sent out}-TS _{Order is received}, and with Δ τ _StayBe inserted in the acknowledgement frame, calculation check and after pass to source node S MAC.

Source node S MAC receives acknowledgement frame, and the time mark processing unit is that reference recording receives time stamp TS with the local clock _{Receive in the source}, and extract the transmission time stamp TS that writes down in the frame _{The source is sent out}With delay time delay Δ τ _Stay, adopt round mensuration to calculate the chain-circuit time delay Δ τ of source node S MAC to destination node SMAC _Link, store in the SMAC attribute variable district by time passing service unit as the basic parameter of SMAC,

Figure 14 adopts the present invention to carry out the flow chart of local area network (LAN) open loop time transmission.

At first, the host node SMAC in connect hours source regularly produces synchronization frame or according to producing at the synchronization frame from node from the request of node SMAC, in the frame transmitting time relevant with temporal information and the path delay of time two territories be both initialized to zero.Then, the time mark processing unit by host node SMAC inserts transmission time stamp TS in the transmitting time territory of synchronization frame _{The source is sent out}, and calculation check and after frame is sent.

Synchronization frame is being transferred to from the process of node SMAC, and the chain-circuit time delay on each section link is measured when SMAC connects, and switching delay is then measured in real time by switching equipment.Detailed process is, synchronization frame behind the link that links to each other between the switching equipment, enters a certain port SMAC of switching equipment through host node, detects synchronization frame by the time mark processing unit, and is that reference recording receives time stamp TS with the local clock of switching equipment _{Hand over, receive}, extract in the frame Δ τ in the path delay of time _{Acceptance, path}And be stored in chain-circuit time delay Δ τ in the SMAC attribute variable district of time passing service unit _{Acceptance, link}, with reception time stamp TS _{Hand over, receive}Store in the time variable memory block of switching equipment by time passing service unit together; When switching equipment has exchanged synchronization frame and leaves a certain port SMAC, detect and the transmission time stamp TS of record synchronization frame by the time mark processing unit _{Hand over, send out}, receive time stamp TS according to the synchronization frame that writes down in the switching equipment time variable memory block again _{Hand over, receive}, the path delay of time Δ τ _{Acceptance, path}Chain-circuit time delay Δ τ with receiving port SMAC _{Acceptance, link}The Δ τ in the path delay of time that calculating makes new advances _{Hand over and send out path}, the path delay of time that is inserted into frame is in the territory, and calculation check and after, continue to transmit synchronization frame.Switching delay Δ τ _ExchangeEqual synchronization frame and send time stamp TS _{Hand over, send out}Deduct synchronization frame and receive time stamp TS _{Hand over, receive}, that is:

Δ τ _Exchange=TS _{Hand over, send out}-TS _{Hand over, receive}

New route time delay Δ τ _{Hand over and send out path}Synchronization frame Δ in the path delay of time τ that equals to extract _{Acceptance, path}, receiving port SMAC chain-circuit time delay Δ τ _{Acceptance, link}With synchronization frame switching delay Δ τ _ExchangeSum, that is:

Δ τ _{Hand over and send out path}=Δ τ _{Acceptance, path}+ Δ τ _{Acceptance, link}+ Δ τ _Exchange

When node SMAC receives synchronization frame, be that the reference recording synchronization frame receives time stamp TS with the local clock by the time mark processing unit _Receive, and from frame, extract the transmission time stamp TS of frame _{The source}With Δ τ in the path delay of time _Path1, calculate time T with the time source time synchronized by the time synchronizing unit _{Synchronously}, the time correcting module of local clock processing unit calculates the deviation delta T with respect to the host node time source time, can realize the time synchronized with host node directly to carrying out time adjustment from node according to this time deviation.

Figure 15 is that the Ethernet SMAC that the present invention uses measures frame assumption diagram.Measuring frame is the data transmission unit that meets concrete procotol frame structure, is used to measure the chain-circuit time delay when connecting between two SMAC of direct interconnection.Measure frame except comprising the frame head information that meets network protocol standard, also comprise territory with time correlation, mainly contain frame type (2 byte), measure flag of frame word (2 byte), measure frame ID (2 byte), source node sends time stamp (6 byte) and frame is detained time delay (6 byte), (frame is measured in difference to the type of frame type field mark present frame, synchronization frame and other frames), measure flag of frame word field mark frame type (frame and acknowledgement frame are measured in difference), measure frame ID territory and write down the sequence number of current measurement frame, source node sends the time stamp territory record time of frame when source node sends, and frame is detained the time delay domain record and enters the time delay that destination node SMAC is experienced from measuring frame when acknowledgement frame leaves.Source node S MAC success and destination node SMAC create and measure frame at the back that connects, and are that benchmark is filled and sent time stamp territory and initialization frame to be detained time delay domain be zero with the source node time when transmit frame.It is that benchmark calculate and fill with its local clock by destination node SMAC when sending the acknowledgement frame of measuring frame that frame is detained time delay domain.

Figure 16 is the Ethernet SMAC synchronous frame stucture figure that the present invention uses.Synchronization frame is the data transmission unit that meets concrete procotol frame structure, is used to transmit standard time information, measures switching delay and bang path time delay information.Synchronization frame is except comprising the frame head information that meets network protocol standard, also comprise the territory with time correlation, mainly contain frame type (2 byte), synchronization frame banner word (2 byte), synchronization frame ID (2 byte), host node and send time stamp (6 byte) and the frame path delay of time (6 byte).The type of frame type field mark present frame (frame, synchronization frame and other frames are measured in difference), synchronization frame banner word territory is used for marker frame type (difference synchronization frame and claim frame), synchronization frame ID territory record is when the sequence number of preamble frame, host node sends the time stamp territory record time of frame when host node sends, and frame territory in the path delay of time is write down synchronization frame and is delivered to time delay information from node SMAC from host node SMAC.Synchronization frame produces when regularly being produced or being received from the node time synchronization request by host node SMAC, and fill to send the time stamp territory by SMAC and initialization frame territory in the path delay of time is zero when transmit frame; Frame territory in the path delay of time is calculated and is filled by the transmit port SMAC of SMAC switching equipment, is extracted at each receiving port SMAC.

Claims (9)

1. open loop time delivering method, it is characterized in that forming a timing system by many time transfer chains, article one, the time transfer chain is made up of from node 1 host node, 0 or a plurality of switching equipment and 1, in switching equipment and the node all configuration synchronization media access controller SMAC be Synchronization Medium Access Controller; A node SMAC directly is connected with another node SMAC, or is connected with a SMAC of switching equipment, links to each other by a pair of SMAC between the switching equipment; The external time source of host node SMAC is for the time transfer chain provides the standard time; Host node SMAC produces the synchronization frame that is packaged with the standard time, and passes through the time transfer chain to broadcasting from node SMAC; The time transfer chain measure in real time synchronization frame by host node SMAC to the Δ τ path and being encapsulated in the synchronization frame in the path delay of time that from node SMAC transmittance process, produces to transmitting from node SMAC; Be made up of the switching delay of each section chain-circuit time delay and each switching equipment the path delay of time that produces in the synchronization frame transmittance process, the time delay that synchronization frame produces when being delivered to next SMAC by a SMAC through transmission line is a chain-circuit time delay, and synchronization frame exchanges the time delay that produces when handling in switching equipment be switching delay; Chain-circuit time delay adopts and measures frame local clock with each SMAC when a pair of SMAC connects is that benchmark is measured, and it is that benchmark is measured in real time with the local clock by switching equipment SMAC that switching delay adopts synchronization frame; Calculate time deviation Δ T with the host node time source standard time and the path delay of time by the synchronization frame transmission from node SMAC, realize correction from node time by this time deviation.

2. open loop time delivering method as claimed in claim 1, it is characterized in that host node SMAC produces synchronization frame and to the method from node SMAC broadcasting is: host node SMAC regularly produces synchronization frame or produces at the synchronization frame from node according to the request from node SMAC, in the frame transmitting time relevant with temporal information and the path delay of time two territories be both initialized to zero, then, the time mark processing unit by host node SMAC inserts transmission time stamp TS in the transmitting time territory of synchronization frame _{The source is sent out}, and calculation check and after frame is sent.

3. open loop time delivering method as claimed in claim 1 is characterized in that the real-time measuring route time delay of time transfer chain Δ τ _PathMethod be:

3.1 suppose that the inlet SMAC chain-circuit time delay and the switching delay of i switching equipment of time transfer chain are Δ τ _{Acceptance, link} ⁱWith Δ τ _Exchange ⁱ, the purpose of time transfer chain is Δ τ from node SMAC chain-circuit time delay _{Purpose, link}, the Δ τ in the path delay of time of the outlet SMAC of the 1st of synchronization frame elapsed time transfer chain the switching equipment then _{Hand over and send out path} ¹Equal this switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ¹With switching delay Δ τ _Exchange ¹Sum, that is:

3.2 the Δ τ in the path delay of time of the outlet SMAC of i switching equipment of synchronization frame elapsed time transfer chain _{Hand over and send out path} ⁱEqual the Δ τ in the path delay of time of i-1 switching equipment outlet SMAC _{Acceptance, path} ^I-1, an i switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ⁱWith the switching delay Δ _{The τ exchange} ⁱSum, that is:

3.3 last i.e. Δ τ in the path delay of time of the outlet SMAC of N switching equipment that synchronization frame is delivered to the time transfer chain _{Hand over and send out path} ^NEqual the Δ τ in the path delay of time of N-1 switching equipment outlet SMAC _{Acceptance, path} ^N-1, a N switching equipment inlet SMAC chain-circuit time delay Δ τ _{Acceptance, link} ^NWith switching delay Δ τ _Exchange ^NSum, that is:

When 3.4 synchronization frame is delivered to from node SMAC, the Δ τ in the path delay of time that is produced _PathEqual the Δ τ in the path delay of time of the outlet SMAC of N switching equipment _{Hand over and send out path} ^NWith from node SMAC chain-circuit time delay Δ τ _{From, link}Sum, that is:

4. as claim 1 or 3 described open loop time delivering methods, it is characterized in that the detailed process that chain-circuit time delay is measured is:

4.1 source node S MAC produces and sends chain-circuit time delay and measures frame, is inserted by the time mark processing unit and sends time stamp TS _{The source is sent out}, and calculation check and this measurement frame of back transmission; After destination node SMAC detects this measurement frame, be that reference recording receives time stamp TS with the local clock by the time mark processing unit _{Order is received}By directly returning after the head exchange of time passing service unit to the measurement frame, be that reference recording sends time stamp TS with the local clock by the time mark processing unit as acknowledgement frame _{Order is sent out}, and calculate the delay time delay Δ τ of frame in SMAC _Stay, being inserted in the acknowledgement frame, transmit to source node S MAC calculation check and back; Can get the delay time delay Δ τ of frame in destination node SMAC thus _Stay:

Δ τ _Stay=TS _{Order is sent out}-TS _{Order is received}

4.2 source node S MAC receives acknowledgement frame, is that reference recording receives time stamp TS with the local clock by the time mark processing unit _{Receive in the source}, and extract the transmission time stamp TS that writes down in the frame _{The source is sent out}With the delay time delay Δ τ of frame in destination node SMAC _Stay, calculate the chain-circuit time delay Δ τ of source node S MAC to destination node SMAC _LinkBasic parameter as SMAC is stored in the SMAC attribute variable district of time passing service unit by time passing service unit; Chain-circuit time delay Δ τ _LinkFor:

5. open loop time delivering method as claimed in claim 1, it is characterized in that the detailed process that switching delay is measured is: after synchronization frame arrives the link that links to each other between the switching equipment through host node, enter a certain port SMAC of switching equipment, detect synchronization frame by the time mark processing unit, and be that reference recording receives time stamp TS with the local clock of switching equipment _{Hand over, receive}, extract in the frame Δ τ in the path delay of time _{Acceptance, path}And be stored in chain-circuit time delay Δ τ in the time passing service cell S MAC attribute variable district _{Acceptance, link}, with reception time stamp TS _{Hand over, receive}Store in the time variable memory block of switching equipment by time passing service unit together; When switching equipment has exchanged synchronization frame and leaves a certain port SMAC, detect and the transmission time stamp TS of record synchronization frame by the time mark processing unit _{Hand over, send out}, receive time stamp TS according to the synchronization frame that writes down in the switching equipment time variable memory block again _{Hand over, receive}, the path delay of time Δ τ _{Acceptance, path}Chain-circuit time delay Δ τ with receiving port SMAC _{Acceptance, link}The Δ τ in the path delay of time that calculating makes new advances _{Hand over and send out path}, the path delay of time that is inserted into frame is in the territory, and calculation check and after, continue to transmit synchronization frame; Switching delay Δ τ _ExchangeEqual synchronization frame and send time stamp TS _{Hand over, send out}Deduct synchronization frame and receive time stamp TS _{Hand over, receive}, that is:

Δ τ _Exchange=TS _{Hand over, send out}-TS _{Hand over, receive}

6. open loop time delivering method as claimed in claim 1, it is characterized in that being: when node SMAC receives synchronization frame, be that the reference recording synchronization frame receives time stamp TS with the local clock by the time mark processing unit from the method that node SMAC calculates with the time deviation of host node time source _Receive, and from frame, extract the transmission time stamp TS of frame _{The source}With Δ τ in the path delay of time _Path1, calculate time T with the time source time synchronized by the time synchronizing unit _{Synchronously}, the time correcting module of local clock processing unit calculates the deviation delta T with respect to the host node time source time, Δ T=T _Node-T _{Synchronously}, can realize time synchronized directly to carrying out time adjustment from node with host node according to this time deviation.

7. open loop time delivering method as claimed in claim 1, it is characterized in that described SMAC is upwards by bus interface and upper layer logic interconnection, downwards by physical layer digital interface and PHY interconnection, SMAC is an integrated circuit, form by media access controller, time passing service unit, time mark processing unit, time synchronizing unit, clock regenerating signal unit and local clock processing unit, realize interconnection by bus interface or clock cable between each unit; Except having the medium access controlled function, also realize transmitting and unified relevant time transmission, time detecting and clock regeneration function and operation with the time in the physical layer digital interface:

7.1 the time, the passing service unit was according to Δ τ _Link=(TS _Receive-TS _{Send out}-Δ τ _StayChain-circuit time delay Δ τ is calculated in)/2 _LinkWherein, TS _{Send out}Be the transmission time stamp in the time stab information that extracts in the acknowledgement frame, Δ τ _StayFor being detained time delay, TS _ReceiveFor receiving the reception time stamp of acknowledgement frame;

7.2 the time synchronizing unit is according to Δ τ _Path2=Δ τ _Path1+ Δ τ _LinkCalculating path time delay Δ τ _Path2Wherein, Δ τ _LinkBe chain-circuit time delay, Δ τ _Path1Be the path delay of time of extracting in the synchronization frame;

7.3 the time synchronizing unit is according to T _{Synchronously}=TS _{The source}+ Δ τ _Path2+ (T _Node-TS _Receive) calculate compensation deals time delay T _{Synchronously}T wherein _NodeThe nodal clock time of the lock-out pulse rising edge correspondence that produces for the time synchronizing unit, TS _{The source}Be transmitting time, T _Node-TS _ReceiveFor time mark processing unit mark synchronization frame produces the processing delay that produces during the lock-out pulse to the time synchronous processing unit;

7.4 the local clock processing unit is according to Δ T=T _Node-T _{Synchronously}Calculate the deviation delta T of node with respect to the host node time source time; Wherein, T _NodeBe the time of time synchronizing unit record.

8. open loop time delivering method as claimed in claim 1, it is characterized in that in the time transfer chain using four kinds of frames with time correlation: measurement frame, acknowledgement frame, synchronization frame and claim frame, measure frame and be used for the measure link time delay, acknowledgement frame is to measure replying of frame, synchronization frame is used for passing time, and claim frame is used for the request that send to produce synchronization frame to host node from node of time transfer chain;

8.1 measuring frame is the data transmission unit that meets concrete procotol frame structure, is used between two SMAC of direct interconnection measure link time delay when connecting; Measure frame except comprising the frame head information that meets network protocol standard, also comprise territory with time correlation, mainly contain frame type, measurement flag of frame word, measurement frame ID, source node transmission time stamp and frame and be detained time delay, the type of frame type field mark present frame, measure flag of frame word field mark frame type, measure frame ID territory and write down the sequence number of current measurement frame, source node sends the time stamp territory record time of frame when source node sends, and frame is detained the time delay domain record and enters the time delay that destination node SMAC is experienced from measuring frame when acknowledgement frame leaves; Source node S MAC success and destination node SMAC create and measure frame at the back that connects, and are that benchmark is filled and sent time stamp territory and initialization frame to be detained time delay domain be zero with the source node time when transmit frame; It is that benchmark calculate and fill with its local clock by destination node SMAC when sending the acknowledgement frame of measuring frame that frame is detained time delay domain;

8.2 acknowledgement frame has and measures identical structure and the type of frame, distinguishes by measuring the flag of frame word, is used for the measurement frame that receives is replied;

8.3 claim frame has structure identical with synchronization frame and type, distinguishes by the synchronization frame banner word, can regularly produce as from node the time at SMAC, to realize sending synchronization frame to the host node request.

8.4 synchronization frame is the data transmission unit that meets concrete procotol frame structure, is used to transmit standard time information, measures switching delay and bang path time delay information; Synchronization frame also comprises the territory with time correlation except comprising the frame head information that meets network protocol standard, mainly contain frame type, synchronization frame banner word, synchronization frame ID, host node and send time stamp and frame path delay of time; The type of frame type field mark present frame, synchronization frame banner word territory is used for the marker frame type, synchronization frame ID territory record is when the sequence number of preamble frame, host node sends the time stamp territory record time of frame when host node sends, and frame territory in the path delay of time is write down synchronization frame and is delivered to time delay information from node SMAC from host node SMAC; Synchronization frame produces when regularly being produced or being received from the node time synchronization request by host node SMAC, and fill to send the time stamp territory by SMAC and initialization frame territory in the path delay of time is zero when transmit frame; Frame territory in the path delay of time is calculated and is filled by the transmit port SMAC of SMAC switching equipment, is extracted at each receiving port SMAC.

9. open loop time delivering method as claimed in claim 1, it is characterized in that switching equipment is made up of exchange logic, some SMAC and time variable memory block, each SMAC is between exchange logic and physical layer, interconnect by bus interface with exchange logic, link to each other by the physical layer digital interface with physical layer, each SMAC also links to each other with the time variable memory block by bus interface simultaneously; Exchange logic achieve frame exchange, the transmitting-receiving of SMAC achieve frame and with the processing and the calculating of time correlation, time variable storage area stores temporal information is also shared between each SMAC.

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