CN1819059A - Semiconductor integrated device - Google Patents
Semiconductor integrated device Download PDFInfo
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- CN1819059A CN1819059A CNA200610006409XA CN200610006409A CN1819059A CN 1819059 A CN1819059 A CN 1819059A CN A200610006409X A CNA200610006409X A CN A200610006409XA CN 200610006409 A CN200610006409 A CN 200610006409A CN 1819059 A CN1819059 A CN 1819059A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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Abstract
A semiconductor non volatile memory device capable of multiple write operations with high reliability is implemented. The memory device includes memory cells, each comprising a first electrode, a second electrode, and an information storage section put between the two electrodes, wherein an operation to feed a first pulse current from the first electrode to the second, and another operation to feed a second pulse current from the second electrode to the first. A segregation of composing elements of the information storage section is caused by applying the first pulse, however, the segregation of elements is resolved by applying the second pulse, and the composition of the element recovers to the original state.
Description
Technical field
The present invention relates to conductor integrated circuit device, be particularly related to the storage unit of utilizing resistance difference to differentiate canned data comprising, for example, the superintegrated memory circuit that comprises the storage unit of using phase-change material, or memory circuitry and logical circuit be arranged on the logic mixed packing storer on the same semiconductor substrate, or have the effective technology of using in the conductor integrated circuit device of mimic channel.Be particularly related to the high speed of under low-voltage, working and have non-volatile random access storage device.
Background technology
The expansion in the market of the nonvolatile memory that is affected by the needs that with the portable phone are the mobile apparatus of representative is tangible.Its representative is the FLASH storer, but because speed is slow in essence, as programming ROM.On the other hand, the storer as operation is used needs high-speed RAM, loads FLASH and two kinds of storeies of DRAM in portable machine.If realization possesses the element of the feature of these two kinds of storeies, not only FLASH and DRAM can be incorporated on the chip, on whole semiconductor memories displacement this point, its influence is greatly.
Realizing one of candidate of this element, is the nonvolatile memory that utilizes phase-change film, for example, detailed introduction is arranged in patent documentation 1.Phase transition storage is also referred to as PRAM, OUM, ovonic memory.This storer is according to the Joule heat that flows through the electric current of memory element itself crystalline state of memory element to be changed to write canned data.Use the material of chalkogenide as memory element.So-called chalkogenide is the material that comprises at least a element among sulphur, selenium, the tellurium.As the composition of chalkogenide, for example, use Ge sometimes
2Sb
2Te
5
Principle of work to phase transition storage gives simple declaration below.When making phase change portion become amorphous state, apply set pulse, phase change portion is heated to more than or equal to chilling after the fusing point of chalcogenide material.Fusing point is for example 600 ℃.Chilling period is for example 10nsec.When making the phase change portion crystallization, in the part with the temperature maintenance of phase change portion more than or equal to Tc and smaller or equal to fusing point.The temperature of this moment for example, is 400 ℃.The time that crystallization needs is different because of the composition of chalcogenide material, for example, is 200nsec.After, the phase change portion crystallization that makes phase-change memory cell is called the set action, amorphous material is called homing action.In addition, the state of phase change portion crystallization is called SM set mode, the state of amorphous material is called reset mode.
The characteristics of phase transition storage are to be crystalline state or amorphous state corresponding to phase change portion, the resistance value of phase change portion has two (numbers) variation to three (numbers), because the height of this resistance value is read accordingly with binary message " 0 " and " 1 ", so resistance difference is big more, it is easy more to read action, and reading speed more at a high speed.In addition, by with three or more the information of multi-system is corresponding, also can carry out many-valued storage.
About the wiring method of phase transition storage, on the books in patent documentation 1.In addition, about since follow write relatively for the element of positive electricity to negative electrode move and relatively for the element of negative electricity to the moving of positive electrode, the composition of storage medium produces the problem that departs from, and is on the books in patent documentation 2.Document about the direction of the current impulse of flowing through phase-change element is as follows.In the phase transition storage that has by the upper electrode and the information storage part of the structure of inserting electrode clamping phase-change material, the method that electric current flows to the insertion electrode from upper electrode, on the books in patent documentation 3.In addition, electric current is on the books non-patent literature 1 to the moving method of top electrode stream from inserting electrode.
Patent documentation 1: No. 5883827 communique of United States Patent (USP) (USP5,883,827)
Patent documentation 2: the Jap.P. spy opens clear 50-65177 communique
Patent documentation 3: No. the 6576921st, United States Patent (USP) (USP6,576,921)
Non-patent literature 1:2003, Symposium on VLSI Technology, the 173rd page to the 174th page, Digest of Technical Papers
Summary of the invention
Fig. 2 illustrates the structure and the composition of the information storage part that writes as yet.The composition of chalkogenide 102 is uniform.Select Ge below
2Sb
2Te
5Composition example as chalkogenide 102 is illustrated.
Fig. 3 illustrates the existing fashionable oscillogram of writing.The direction of current that uses in set and in resetting is a direction.About carrying out once seldom write fashionablely, it is even that the composition of chalkogenide 102 roughly keeps.In homing action, near the place the electrode 104 that write current is concentrated becomes the extra-high-speed temperature, shown in Fig. 4 (a), becomes amorphous state.At this moment, the long enough because the length 121 of high-resistance amorphous phase 111 becomes, the resistance between electrode 103 and the electrode 104 uprises.
Yet, carrying out 10
5～10
12Writing in a large number about inferior is fashionable, shown in Fig. 4 (b), when placing reset mode, becomes crystallization phase 143 near the insertion electrode 154.Its reason is seen below and is stated.Because the length 144 of amorphous phase 141 shortens, the resistance between electrode 103 and the electrode 104 reduces.
On the other hand, not too big variation of the resistance of SM set mode.Therefore, owing to write repeatedly, just be difficult to differentiate canned data " 0 " and " 1 ".
At reset mode, become the reasons are as follows of crystallization phase near the insertion electrode 154.Phase transition storage, owing to be to utilize Joule heat to heat chalkogenide to rewrite, chalkogenide applies electric field under the condition of high temperature.Therefore, owing to constitute the result that electronegative difference of the element of chalkogenide produces ionic conduction, form to produce and depart from.
For example, at Ge
2Sb
2Te
5Occasion, it is low that Ge (electronegativity 1.8 of polarization) and Sb (electronegativity 1.9) and Te (electronegativity 2.1) compare electronegativity, owing to be the element that aligns mutually, moves to direction of current.Relative therewith, because Te is negative relatively element, move to the opposite direction of electric current.
Therefore, as shown in Figure 5, at electric current 134 when electrode 103 flows to electrode 104, the ratio of components height of the Te of the chalkogenide 132 the electrode 103 near, the ratio of components height of Ge, the Sb of near the chalkogenide 133 the electrode 104.
Crystallization rate depends on the composition of chalkogenide.Because the segregation that material is formed, crystallization rate become part at a high speed, also can not become amorphous state and become crystalline state even apply reset pulse.Therefore, shown in Fig. 4 (b), in reset mode, crystallization phase 143 forms near inserting electrode 154.
Among the invention disclosed, the summary of typical example is as follows in this application.
In having the storage unit that is clipped in the information storage part between the 1st electrode and the 2nd electrode, be a kind of it is characterized by electric current from the 1st electrode stream to the action of the 2nd electrode with to make electric current be the mode of constantly being undertaken by set from the 2nd electrode to reciprocal action to the 1st electrode stream under ideal conditions.Because the 1st pulse composition can depart from, but can eliminate departing from of composition and make and form the original state that turns back to by applying the 2nd pulse.
Preferably, information storage part is made of variable resistor.
Preferably, variable resistor is the phase-change element that changes by its resistance value of crystalline state.
Preferably, the material of phase-change element is to be made of chalkogenide.
When using the conductor integrated circuit device that adopts technology of the present invention, increase even write indegree, also can realize the semiconductor non-volatile memory storage that reliability is high.This device by loading in mixture on same basal disc with the logic semiconductor arithmetic unit, can provide reliability high high function internally-arranged type microcomputer.In addition, this device also can be used as monolithic chip provides.
Description of drawings
Fig. 1 is the diagrammatic sketch that illustrates about the working method of the information storage part of embodiment 1.
Fig. 2 illustrates the structure of phase transition storage and the synoptic diagram of composition.
Fig. 3 is the diagrammatic sketch that the working method of existing mode is shown.
Fig. 4 is the synoptic diagram of information storage part that the problem of existing mode is shown.
Fig. 5 is the synoptic diagram of information storage part that the problem of existing mode is shown.
Fig. 6 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Fig. 7 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Fig. 8 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Fig. 9 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Figure 10 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Figure 11 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 1.
Figure 12 is element and the electronegative chart thereof that illustrates about embodiment 2.
Figure 13 is the synoptic diagram about the information storage part of embodiment 3.
Figure 14 is the diagrammatic sketch that illustrates about an example of the working method of the information storage part of embodiment 4.
Figure 15 is the circuit diagram about the memory module of embodiment 5.
Figure 16 is the working waveform figure of memory module shown in Figure 15.
Figure 17 is the diagrammatic sketch that the relation of read-around number and read current is shown.
Figure 18 is the diagrammatic sketch that the effect of boosting word line is shown.
Figure 19 is the planimetric map of storage array.
Figure 20 is the circuit diagram about the memory module of embodiment 5.
Figure 21 is a memory module working waveform figure shown in Figure 15.
Figure 22 is the circuit diagram about the memory module of embodiment 6.
Figure 23 is a memory module working waveform figure shown in Figure 16.
Figure 24 is the planimetric map of storage array.
Figure 25 is the circuit diagram about the memory module of embodiment 7.
(description of reference numerals)
102,191... chalkogenide, 103... electrode 1,154... inserts electrode, and 110,142, the 143... crystallization phase, 111, the 141... amorphous phase, the length of the amorphous phase of 121... after write-once " 0 ", 131...Ge
2Sb
2Te
5, 132...Ge
1.8Sb
1.8Te
5.4, 133...Ge
2.2Sb
2.2Te
4.6144... the length of the amorphous phase after repeatedly writing " 0 ", 151... storage unit, 152... selection transistor, 153... information storage part, 154... insertion electrode, 155... upper electrode, 161,171,202,251,253... the 1st pulse, 162,172,203,252,254... the 2nd pulse, 184... word line, 185... source line, 186,197... bit line, 192... zone of heating, 193... adhesive linkage, 194... electrode 2,195... electrode 1,196... inserting column, 198... diffusion layer, 201... the 1st current impulse, 202... the 2nd current impulse, 203... the 3rd current impulse, ADD... address, ARRAY... storage array, BL... bit line, BLS... bit line select circuitry, BS... bit line select signal, BSW... bit line switch, CBL... shared bit line, CBSW... in length and breadth (intersection) switch, CL... bridging line, CNT... contact, CSL... common source line, Di... import data, Do... output data, Icell... memory cell current, Iread... read current (source), Ireset... resetting current (source), Iset... set current (source), IW... write current, L... diffusion layer, M1... the 2nd wiring layer, M2... the 1st wiring layer, MC... storage unit, MN...N channel type MOS transistor, the MP...P channel type MOS transistor, NG... node, PS... polysilicon layer, R... memory element, RA... read-out control circuit, READ... read action, the REF... reference voltage, the RIS... resetting current is selected signal, RSW... switch, RWC... read/write circuit, SA... sensor amplifier, SE... sensor amplifier activation signal, SIS... set current is selected signal, SL... source line, SS... source line options signal, SSW... source line switch, STANDBY... holding state, SW... switch, VDD... power supply potential, VIA... path, WA... write amplifier, WDC... write data selection circuit, the WE... write control signal, the WIC... write current is selected circuit, WL... word line, WRITE... write activity, WD_ARY... word driver array, ADEC...X is an address decoder, VWL... power lead, the WIC... write control circuit
Embodiment
Below with reference to concrete example embodiments of the present invention are elaborated.
[embodiment 1]
Fig. 1 and Fig. 6 to Figure 10 are the storage unit and the working waveform figures of the conductor integrated circuit device of embodiments of the present invention 1.
Has the storage unit 151 of selecting element 152 and information storage part 153 shown in Fig. 1 (a).Information storage part 153 has and the structure that is connected with source line 185 as the MOS transistor of selecting element 152.Certainly, also can be and the structure of selecting to be connected between element 152 and the bit line 186.In this occasion, on word line 184, apply pulse voltage and make the selection element conductive, electric current flows out from the direction of bit line 186 or source line 185.In diagrammatic cross-section with storage unit shown in the figure (b).The structure of information storage part 153, be by with the bigger upper electrode 155 of the contact area of chalkogenide with compare the structure that clips chalkogenide 102 with the little insertion electrode 154 of the contact area of chalkogenide with above-mentioned upper electrode.
At this moment, shown in figure (c) because when work electric current polarity constantly switch, can prevent to follow the segregation of composition of the chalkogenide of ionic conduction, can produce and can write the effect that indegree increases.The amplitude and the pulse width of the positive negative impulse current when resetting or during set can be selected arbitrarily in the scope with thermal effect identical with existing Fig. 3.
For example, the occasion of switch current direction when applying reset pulse, the pulse width of the 1st pulse 171 are 30ns, and current value is 200 μ A.The pulse width of the 2nd pulse 172 is 20ns, and current value is 200 μ A.Certainly select the optimal value of above-mentioned pulse width and current value corresponding to the composition of the composition of the chalkogenide that uses and electrode.The total of the generating capacity of the Joule heat that above-mentioned the 1st current impulse 171 of information storage part 153 and above-mentioned the 2nd current impulse 172 cause equates with the generating capacity of the Joule heat that the reset pulse of existing mode causes.
In addition, in the occasion of switch current direction, the pulse width of the 1st pulse 171 is 80ns when applying set pulse, and current value is 100 μ A.The pulse width of the 2nd pulse 172 is 70ns, and current value is 100 μ A.
In addition, also switch current direction when resetting only as required.This is because Da Wendu and the set action that is up to of the chalkogenide in the homing action is compared very highly, forms segregation and mainly takes place when resetting.In addition, suppose in each time band that pulse current 171,172 is flow through, on word line 184, to apply word pulse voltage.Reversal can obtain to bit line (BL) 186 sides to source line (SL) 185 or from source line (SL) 185 effluents by bit line (BL) 186 effluents from Fig. 1.Above-mentioned word pulse voltage shown in Fig. 1 (c), both can be one and comprise two electric currents 171 and 172, perhaps also can be to be split up into two and comprise two electric currents 171 and 172 respectively.
Fig. 6 to 10 illustrates for example and is used for resetting and the pulse current of set.
The feature of Fig. 6 is that the amplitude and the time of the 1st pulse current 161 and the 2nd pulse current 162 is roughly the same.In this occasion, because the quantity of electric charge that flows through chalkogenide that flows through the quantity of electric charge of chalkogenide and the 2nd pulse current in the 1st pulse current about equally, that can suppress to form departs from.In the manner, because make it or flow out from bit line side by a pulse current source is switched, perhaps this source line effluent goes out and produces reversal, so can make the design that produces the storage unit peripheral circuit that writes pulse become simple.
The feature of Fig. 7 is that the electric current of the 1st ratio of pulse length to the total cycle length the 2nd pulse is big.Advantage is as follows.When the temperature of chalkogenide rose, the interatomic adhesion that constitutes chalkogenide died down, even in the occasion that applies same electric field segregation takes place easily also.In the moment that applies the 1st pulse, because the temperature of chalkogenide raises, in the amplitude of the 2nd pulse current occasion identical with the amplitude of the 1st pulse current, the atomicity that is moved by the 2nd pulse is Duoed than the atomicity that is moved by the 1st pulse and is produced and form segregation.In order to address this problem, the amplitude of the 2nd pulse can be reduced to than the 1st pulse is little and to get final product.As a result, the atomicity that moves by the 1st pulse and become equal by the atomicity that the 2nd pulse is moved.
In addition, also can utilize variation corresponding to the transistorized drive current of selection of direction of current.Utilize Fig. 1 (a) that the reason of drive current variations is described below.When the current potential of bit line 186 was higher than the current potential of source line 185, voltage was the potential difference (PD) of word line 184 and source line 185 between the grid source of above-mentioned selection transistor 152.Secondly, when the current potential of bit line 186 was lower than the current potential of source line 185, voltage was the potential difference (PD) between the current potential of the current potential of place X and word line 184 between the grid source of above-mentioned selection transistor 152.Wherein, the current potential of place X is smaller or equal to source line current potential and more than or equal to the bit line current potential.Therefore, select the drive current of transistor 152, when the current potential of bit line 186 is higher than source line 185, become big.
Relative therewith, the feature of Fig. 8 is that the width of the 1st ratio of pulse length to the total cycle length the 2nd pulse is long.This is in order to carry out the correction identical with Fig. 7.In the manner, because homing action or set action are carried out in the timing (timing) that can use a constant current source to apply by pulse, so can make the formation of storage unit peripheral circuit become simple.
Relative therewith, the feature of Fig. 9 is that the electric current of the 1st ratio of pulse length to the total cycle length the 2nd pulse is little.Chalkogenide has because of heating and becomes low-resistance character.Therefore, when the amplitude of the amplitude of supposing the 1st pulse current and the 2nd pulse current equates, utilize the 1st pulse to put on the voltage height that the voltage ratio on the chalkogenide utilizes the 2nd pulse to apply, the atomicity that is moved by the 1st pulse surpasses the atomicity that is moved by the 2nd pulse.So, become less than the amplitude of the 2nd pulse current by the amplitude that makes the 1st pulse current, the mobile number of atom is equated.
In addition, the amplitude by making the 2nd pulse shown in Figure 10 can obtain same effect greater than the amplitude of the 1st pulse.
Figure 11 is the combination examples of Fig. 6～10.For homing action, be to flow to the opposite direction of above-mentioned the 1st pulse by the 2nd pulse 252 that after the 1st pulse 251, makes bigger electric current with 50～1000 microamperes and the relatively shorter pulse width of 5～100 nanoseconds to carry out with 20～400 microamperes smaller electric current and long pulse width of 50～1000 nanoseconds.In addition, set action, be with homing action in the 1st pulse and the 2nd pulse sequence carry out on the contrary.Homing action is the combination of Fig. 8 and 9, and the set action is the combination of Fig. 7 and 10.
For homing action, be to utilize the 1st pulse current 251 to make the chalkogenide crystallization, utilize with above-mentioned the 1st pulse consecutive pulses electric current 252 to make chalkogenide become amorphous state.
For the set action, be to utilize the 1st pulse current 253 to make chalkogenide become amorphous state, utilize with above-mentioned the 1st pulse consecutive pulses electric current 254 and make the chalkogenide crystallization.
In this mode,, have circuit and constitute characteristic of simple owing to only utilize these two kinds of pulses of above-mentioned the 1st pulse and above-mentioned the 2nd pulse just can carry out set and homing action.In addition, because setting time and reset time equate to have the feature that is user-friendly to.
Utilize Fig. 1 (a) that the method that produces reciprocal electric current is illustrated below.Storage unit 151 is by selecting element 152 and information storage part 153 to constitute.Selecting transistor is the N channel-type.Nature also can use the P channel-type.Select transistorized grid to link to each other with word line 184, leakage links to each other with bit line 186.Information storage part is disposed at and selects between transistorized source and the source line 185, is writing fashionablely, at first word line is applied voltage, afterwards the source line is applied voltage.As a result, pulse current flows to bit line from the source line by selecting transistor and information storage part.Above-mentioned pulse current is equivalent to the 1st pulse current of being put down in writing with figure (c) 171.Afterwards, the voltage of source line returns 0V, and pairs of bit line applies voltage.As a result, pulse current flows to the source line from bit line by information storage part and selection transistor.Above-mentioned pulse current is equivalent to the 2nd pulse current of being put down in writing with figure (c) 172.Afterwards, the voltage of source line and word line returns 0V.By above action, can switch the sense of current that flows through information storage part.In the manner,, has the simple advantage of word driver because the current potential of word line is that 2 values get final product.
Certainly, also can be before the voltage of word line rises, the voltage of bit line rises or before the voltage of source line descended, the voltage of word line descended.
In addition, also can use following method.Before write activity, word line 184, bit line 186, source line 185 remain 1/2VDD.At first, make word line 184 rise to VDD, afterwards, make bit line 186 drop to the intermediate potential of 0V and 1/2VDD.As a result, pulse current flows to bit line from the source line by selecting transistor and information storage part.Above-mentioned pulse current is equivalent to the 1st pulse current of being put down in writing with figure (c) 171.Afterwards, make bit line rise to the intermediate potential of 1/2VDD and VDD.As a result, pulse current flows to the source line from bit line by information storage part and selection transistor.Above-mentioned pulse current is equivalent to the 2nd pulse current of being put down in writing with figure (c) 172.By adopting above method,, can make consecutive storage unit and source line 185 sharings because can apply the such DC voltage of 1/2VDD to the source line.So, can reduce the area of storage unit.
In addition, also information storage part can be disposed between bit line and the selection transistor, or select element, or adopt bipolar transistor with the knot conduct.
As the feature of present embodiment, the adducible pulse width weak point that puts on the pulse voltage of bit line and source line in addition.Above-mentioned pulse width, for example, smaller or equal to 100ns.
[embodiment 2]
Utilize invention disclosed in this application, can prevent the segregation of the composition in the chalkogenide.Therefore, can use in existing mode owing to being easy to produce the composition segregation and out of use chalkogenide.As being easy to generate the standard of forming segregation, the electronegative poor of the element that constitutes storage medium arranged.As the storage medium that phase transition storage is used, the composition of the chalkogenide of main research is Ge-Sb-Te.Shown in electronegative complete list as shown in Figure 12, the electronegativity of Ge is 1.8, and Sb is 1.9, and Te is 2.2.Move to positive electrode relative to Te thus for negative element.Electronegativity minimum between three kinds of elements of Ge-Sb-Te be Ge, that maximum is Te, its difference is 0.3.
The electronegative difference that constitutes element exists to be easy to produce the problem of forming segregation greater than 0.3 chalkogenide.On the other hand, in the big chalkogenide of electronegative difference, the ionic link that forms between cation element and anion element is very firm, because Tc rises, has the advantage that 10 annual datas keep temperature to improve.
Utilize invention disclosed in this application, can realize and repeatedly to write, and have the phase transition storage that 10 very high annual datas keep temperature concurrently.
As an example of forming, can enumerate Ge
2Sb
2Se
5, Ge
2Sb
2S
5And Zn-Ge-Sb-Te.
[embodiment 3]
Figure 13 is the diagrammatic cross-section of storage part of the storage unit of embodiments of the present invention 4.Between electrode 195 and electrode 194, clip adhesive linkage 192, zone of heating 193 and chalkogenide 191.Wherein, adhesive linkage 192 is for when storer manufacture process and the memory operation, does not produce the space and be provided with between chalkogenide and electrode.In addition, zone of heating 193 is provided with for high-level efficiency when write current flows through produces Joule heat.In this structure, can be diffused into chalkogenide from these layers owing to constitute the atom of zone of heating or adhesive linkage, so do not adopt the big material of rate of propagation as zone of heating or adhesive linkage in the past.But, in the manner of switch current direction because can prevent because these elemental diffusion of causing of ionic conduction, thus can use existing since big and out of use Si of rate of propagation and C as zone of heating and adhesive linkage.Because the conformability of the semiconductor fabrication of Si is good, C is the strong material of cohesiveness, has advantage easy to manufacture.
[embodiment 4]
The feature of Figure 14 (a) is in the set action, the current opposite in direction of the 1st pulse 201 and the 2nd pulse 203, and have the part 201 that has especially big electric current to flow through near the front end of the 1st pulse 202.By this part 201, can be temporarily to chalkogenide, for example, between 20ns, apply that high voltage produces that two-way switch switches and the resistance that reduces chalkogenide.Therefore, when pulse current 202 and 203 flows through, put on the voltage on the chalkogenide, very little getting final product.By use the manner when set is moved, generation can reduce the advantage of set power.
The feature of Figure 14 (b) is that direction of current is carried out switching more than or equal to 2 times.By increasing switching times, move the needed time with atom and compare, can carry out the switching of direction of current with short time interval, can suppress to form segregation.
On the other hand, phase transition storage when reading, for preventing the destruction of information, must make electric current flow in the scope that the state that can not make phase change resistor changes, and the electric current that flows through is less than rewriting electric current.Reading speed can degenerate when but, electric current reduced.In other words, consider, must make read current little, and consider that from the viewpoint of reading speed read current is essential big to have trade-off relation from the viewpoint that prevents corrupt.When the viewpoint of reading speed is considered, read and may read at a high speed by destroying data, but in order to keep data to rewrite, rewriting number of times increases, reliability reduces worrying.Carrying out this destruction when reading, can use above-mentioned positive and negative inversion pulse.In other words, can suppress to form segregation, can increase the rewriting number of times, may destroy and read/rewrite.
Utilize accompanying drawing that several preferences of semiconductor storage of the present invention are illustrated below, the method (destroying data reads and rewrite) that is used to make the reading speed high speed is at first described, afterwards, illustrated constituting by the circuit of introducing above-mentioned positive negative pulse stuffing increase rewriting number of times.
Circuit component to each functional block of constituting embodiment has no particular limits, and the integrated circuit technique that can utilize known CMOS (complementary type MOS transistor) etc. forms on the such semiconductor substrate of monocrystalline silicon.In the drawings, the not special expression of the method for attachment of the substrate potential of MOS transistor, but so long as in MOS transistor can the scope of operate as normal, its method of attachment is not particularly limited.In addition, in the occasion that does not have to specify, the low level note of signal is made " L ", and the high level note is made " H ".
[embodiment 5]
The structure of＜memory module 〉
Utilize the memory module of Figure 15 to be elaborated below.Constitute the storage array ARRAY of memory module, constitute, on the intersection point of word line WL and bit line BL, be connected with storage unit MC by many word line WL and multiple bit lines BL.Each storage unit MC as illustrated with storage unit MC00, is made of N channel type MOS transistor MN00 and memory element R00.Memory element R00 is the element that is called phase change resistor, it is characterized by, and for example, in crystalline state the low resistance about 1k Ω～10k Ω, in amorphous state high resistance more than or equal to 100k Ω.On the gate electrode of N channel type MOS transistor MN00, be connected with word line WL0, make in the state of selecting the N channel type MOS transistor to be the ON state by controlling, and be the OFF state in nonselection mode.The terminal of R00 is connected with bit line BL0, and another terminal is connected with the drain electrode of MN00.The source electrode of MN00 is connected with earthing potential.In the present embodiment, phase-change element R is connected between bit line BL and the N channel type MOS transistor MN, but also can be connected between earthing potential and the N channel type MOS transistor MN.In addition, also can use bipolar transistor to replace MOS transistor.
Being connected with X on word line WL is the address decoder circuit piece, and utilizing X is that address signal is selected a word line WL.
On bit line BL, be connected with bit line select circuitry BLS, utilize switch SW to be connected with bridging line CL selectively.Switch SW, being used to from Y is that the bit line select signal BS of address decoder circuit piece controls.
Read/write circuit RWC is by sensor amplifier SA, write amplifier WA, write data selection circuit WDC and read-out control circuit RA constitutes.Sensor amplifier SA amplifies the signal of bridging line CL.Read-out control circuit RA is made up of switch RSW and current source (Iread).Write amplifier WA, select circuit WIC to form, constitute current mirroring circuit by P channel type MOS transistor (MP0, MP1), current source (Iset, Ireset) and write current.The source electrode of P channel type MOS transistor MP0 is connected with power supply potential VDD, gate electrode is connected with node NG with drain electrode, the source electrode of P channel type MOS transistor MP1 is connected with power supply potential VDD, and gate electrode is connected with node NG, and drain electrode is connected with bridging line CL.Node NG utilizes write current to select circuit WIC to be connected with current source (set current source Iset or resetting current source Ireset).The current potential of node NG changes so that the electric current of the current source that is connected is identical with electric current I W0 in MP0.In addition, because voltage is identical between the grid source of MP1 and MP0, so electric current I W1 also is the electric current identical with IW0.Its result, the electric current that the electric current of inflow bit line BL becomes the current source that is connected with node NG is identical.
Writing what import on the data selection circuit WDC is write control signal WE, input data Di and output data Do, signal (resetting current selects signal RIS, set current to select signal SIS) is outputed to write data selection circuit WIC.
＜manner of execution 〉
Utilize Figure 16 that detailed action is illustrated below.The supply voltage VDD of internal circuit for example, is 1.5V, is holding state STANDBY during beginning, and ADD is switched when the address, when write control signal WE becomes " L ", just begins to read action READ.Main herein occasion of just reading " 1 " ((high resistance) state resets) from storage unit MC00 describes.In Figure 16, illustrate with solid line.The occasion of reading " 0 " (set (low resistance) state) is shown in broken lines.
Make word line WL0 when " L " is activated to " H ", making switch RSW become ON, drive current Iread flow into bit line BL0.Phase-change element is to utilize heat to change element, particularly amorphous (resetting) attitude of crystalline state, even the also slowly crystallization (set) of heating that is caused by little electric current.Because this variation is constantly accumulation, to postpone a little in order to make crystallization, the past must be used the electric current littler than write current when reading.The relation of Iread shown in Figure 17 and read-around number.For example, when electric current is 100 μ A, just once reads and to make data corruption, and during the electric current about 10 μ A, almost can infinitely read.Yet the current potential of chien shih bit line BL changes when utilizing electric current about 10 μ A to need, and reading speed is slack-off.So, in the present invention, Iread is increased to, for example, 100 μ A can make the reading speed high speed.But because there is the possibility of data corruption, the data of reading must rewrite.
When making read current Iread flow through bit line BL0, because be what storage unit MC00 write, for example, and the value of the high resistance of 100k Ω (suitable) with data " 1 ", the current potential of bit line BL0 rises always and reaches near the power supply, for example, 1.2V.If on storage unit MC00, write, for example, the value of the low resistance of 10k Ω (suitable) with data " 0 ", the not conference of current potential of bit line BL0 is risen and about 1.0V.By making sensor amplifier activation signal SE become " H ", in sense amplifier circuit SA, this voltage and reference voltage REF are compared, this potential difference (PD) is amplified.To output to Do through the data of amplifying and finish to read.When writing high resistance, to Do output " 1 ", and when writing low-resistance value, to Do output " 0 ".
In the present embodiment, after reading, with the data rewrite of reading.As a result, just there is not the problem of the data corruption when reading.
In the present embodiment, read " 1 " afterwards, the data of reading are delivered to write data selection circuit WDC, and resetting current selects signal RIS to become " H " from " L ".As a result, drive write current and select circuit WIC, make current source Ireset be connected to node NG.The electric current I W1 of P channel type MOS transistor MP1 also becomes and is Ireset as a result, can make electric current I reset flow to bit line BL0.
Resetting current Ireset for example, is 200 μ A.Owing to reading data are damaged, when element becomes low resistance, are continuing to flow into the electric current of 200 μ A, bit line rises near the power supply potential always.In addition, even do not make the element low resistanceization by reading, because resetting current Ireset element meeting low resistanceization, the electric current of 200 μ A continues to flow into.This state continues 5 nanoseconds to tens of nanosecond element will become molten condition.Afterwards,, the electric current that flows into element carries out chilling, memory element R00 amorphous material and to become be high resistance (suitable with data " 1 ") by sharply being descended.
In addition, non-selected bit line BL is connected with earthing potential.
If in the occasion of reading " 0 ", because memory element R is a SM set mode, even read current Iread is flow through, resistance value can not change yet, and does not need the data write-back.But, in the present embodiment,, when reading " 0 ", also write in order to simplify control.In this occasion, after reading, utilization writes amplifier WA makes set current Iset flow to bit line BL0.Because the element low resistanceization, the electric current of 100 μ A continues to flow through.This state continuance is about 100 nanoseconds and finish write activity.
When write activity finished, word line WL0 transferred to " L " and finishes the set action from " H ".Write activity WRITE after sense data, utilizes to write data selection circuit WDC, selects the input data Di from the outside, and selects signal RIS and set current to select signal SIS to write data according to this Data Control resetting current.
In the oscillogram that the solid line of present embodiment is represented, write " 0 " afterwards reading " 1 ", and in the oscillogram that is represented by dotted lines, write " 1 " afterwards reading " 0 ".When writing " 0 ", the SIS signal is become from " L " be " H ", by making set current Iset flow into bit line BL element is carried out set.When writing " 1 ", by being become from " L ", the RIS signal is " H ", make resetting current Ireset flow into bit line BL and element is resetted.
In write activity WRITE, do not need to read, but carry out and read action READ same control in order to simplify control.
In the present embodiment, when resetting, must make the electric current I reset of 200 μ A flow into element.Therefore, the N channel type MOS transistor MN of storage unit MC also must have the driving force that equal electric current is flow through.In order to strengthen current driving capability, transistorized grid width is strengthened, but this also can make the size of storage unit increase.So, replace to increase grid width and adopt and make the boost in voltage of word line WL when " H " increase current driving capability to the value higher than supply voltage VDD.In the present embodiment, be to make the voltage of word line be elevated to 2.5V than the high 1.0V of supply voltage VDD.The size of essential storage unit and the relation of word voltage when the electric current at 200 μ A shown in Figure 18 flows through.Because when word voltage was risen, the electric current that flows through increased, and grid width is reduced, and can dwindle unit size.Become 1.5V with making word voltage, strengthen the occasion of grid width and compare, make word voltage rise to the occasion of 2.5V, cellar area is become to about 60%, make unit size become 6F2.The voltage that boosts is considered reliability, must not apply the voltage more than or equal to 5MV/cm on gate electrode.
In addition, as the other method that the current driving capability of the N channel type MOS transistor MN that makes storage unit MC increases, reduce the method for threshold value in addition.In this occasion, can be supply voltage VDD with the voltage of word line WL when " H ", but because the leakage current during non-the selection increases, word line WL must apply negative voltage when " L ".For example, when threshold value decline 0.5V, its effect must apply-0.5V non-selected word line WL with to make word line WL boost to 2V identical.
Figure 19 illustrates the planimetric map of storage array.Word line WL is formed by polysilicon layer (PS), and source line SL is formed by the 1st wiring layer M1, and bit line BL is formed by the 2nd wiring layer M2.In addition, diffusion layer L utilizes contact CNT to be connected with wiring layer M1, and wiring layer M1 utilizes path VIA to be connected respectively with wiring layer M2.
The occasion of＜control word line 〉
Utilize the memory module of Figure 20 that the occasion of controlling word line is described below.Constitute the storage array ARRAY of memory module, constitute, on the intersection point of word line WL and bit line BL, be connected with storage unit MC by many word line WL and multiple bit lines BL.Each storage unit MC as illustrated with storage unit MC00, is made of N channel type MOS transistor MN00 and memory element R00.Memory element R00 is the element that is called phase change resistor.Word line WL is connected with word driver array WD_ARY, and to utilize X be address decoder ADEC to X is that address signal XADD deciphers and selects a word line WL.Word driver array WD_ARY is made of word driver WD, word driver WD0, for example, become the negative circuit that constitutes by N channel type MOS transistor MN10 and P channel type MOS transistor MP10, output is connected with word line WL, and the source electrode of P channel type MOS transistor MP10 is connected with power lead VWL.
Bit line BL is connected with bit line select circuitry BLS, utilizes switch SW to be connected with bridging line CL selectively.Switch SW, being used to from Y is that the bit line select signal BS of address decoder circuit piece controls.
Read/write circuit RWC is by sensor amplifier SA, write amplifier WA, write data selection circuit WDC and write control circuit WIC constitutes.Writing what import on the data selection circuit WDC is write control signal WE, input data Di and output data Do, and control signal CW is outputed to write control circuit WIC.Write control circuit WIC is according to CE signal control power supply line VWL and signal BS.Write amplifier WA and constitute, input control signal BC on gate electrode by P channel type MOS transistor MP1.
＜manner of execution 〉
Utilize Figure 21 that detailed action is illustrated below.The supply voltage VDD of internal circuit for example, is 1.5V, is holding state STANDBY during beginning, and ADD is switched when the address, when write control signal WE becomes " L ", just begins to read action READ.Main herein occasion of just reading " 1 " ((high resistance) state resets) from storage unit MC00 describes.In Figure 16, illustrate with solid line.The occasion of reading " 0 " (set (low resistance) state) is shown in broken lines.
During beginning,, control signal BC carries out precharge by being become to " L " pairs of bit line BL0.Word line WL0 is activated to " H " from " L ", utilize storage unit MC00 to obtain electric current from bit line BL0.Because MC00 writes to storage unit, for example, the value of 100k Ω high resistance (suitable) with data " 1 ", the current potential of bit line BL0 is almost constant, for example is 1.5V.If write for example low resistance of 10k Ω (being equivalent to data " 0 ") value among the storage unit MC00, bit line BL0 reduces to become and is about 0.5V.By making sensor amplifier activation signal SE become " H ", in sense amplifier circuit SA, this voltage and reference voltage REF are compared, this potential difference (PD) is amplified.To output to Do through the data of amplifying and finish to read.When writing high resistance, to Do output " 1 ", and when writing low-resistance value, to Do output " 0 ".
In the present embodiment, after reading, with the data rewrite of reading.As a result, just there is not the problem of the data corruption when reading.
In the present embodiment, read " 1 " afterwards, the data of reading are delivered to write data selection circuit WDC, signal CW is exported.Its result utilizes write control circuit WIC, control power lead VWL and signal BC.In the occasion of reading " 1 ", bit line is supply voltage 1.5V, and word voltage keeps supply voltage 1.5V constant.
Element is a high resistance before reading, but by reading data is damaged, and during the element low resistance, flows through the resetting current Ireset of 200 μ A.In addition, even do not make the element low resistanceization by reading, because resetting current Ireset element meeting low resistanceization, the electric current of 200 μ A continues to flow into.This state continues 5 nanoseconds to tens of nanosecond element will become molten condition.Afterwards,, the electric current that flows into element carries out chilling, memory element R00 amorphous material and to become be high resistance (suitable with data " 1 ") by sharply being descended.
In addition, non-selected bit line BL is connected with earthing potential.
If in the occasion of reading " 0 ", because memory element R is a SM set mode, even read current Iread is flow through, resistance value can not change yet, and does not need the data write-back.But, in the present embodiment,, when reading " 0 ", also carry out writing of set in order to simplify control.In this occasion, because after reading, bit line is set to supply voltage 1.5V, and word voltage is set to 1.0V, the element low resistanceization, and the electric current of 100 μ A continues to flow through.This state continuance is about 100 nanoseconds and finish write activity.
When write activity finished, word line WL0 transferred to " L " and finishes the set action from " H ".Write activity WRITE after sense data, utilizes to write data selection circuit WDC, selects the input data Di from the outside, and writes data according to this Data Control supply voltage VWL.
In the oscillogram that the solid line of present embodiment is represented, write " 0 " afterwards reading " 1 ", and in the oscillogram that is represented by dotted lines, write " 1 " afterwards reading " 0 ".
In write activity WRITE, do not need to read, but carry out and read action READ same control in order to simplify control.
[embodiment 6]
Below, to before rewriteeing and writing, the method that applies current impulse is illustrated.Utilize the manner can carry out the rewriting of unlimited number of times.In addition, in the present embodiment, set current source Iset is shared with reading with current source Iread, removes to read with control circuit RA to reduce area.
The structure of＜memory module 〉
Utilize Figure 22 only to narrating below with embodiment 1 dissimilarity.Source line SL is not connected with earthing potential, with the parallel formation of bit line BL, utilizes bit line select circuitry BLS to be connected with common source line CSL.For example, line SL0 in source utilizes source line switch SSW0 to be connected with common source line CSL.In addition, bit line BL also utilizes bit line select circuitry BLS to be connected with shared bit line CBL.For example, bit line BL0 utilizes bit line switch BSW0 to be connected with shared bit line CBL.
Bit line switch BSW is by bit line select signal BS control, and source line switch SSW is controlled by source line options signal SS.
Shared bit line CBL and common source line CSL are input to crossbar switch CBSW, are connected with bridging line CL or earthing potential.
＜manner of execution 〉
Utilize Figure 23 only to narrating below with embodiment 1 dissimilarity.Identical up to sense data in reading action READ with embodiment 1.After sense data, at first input current pulse.
For example, when reading " 1 ", flow through bit line BL0 by making set current select signal SIS to become to " H " makes set current Iset from " L ".When reading " 0 ", flow through bit line BL0 by making resetting current select signal RIS to become to " H " makes resetting current Ireset from " L ".With opposite direction of current, rewrite the value of being read afterwards.When reading " 1 ", bit line BL0 is connected with earthing potential, be " H ", make resetting current Ireset flow through source line SL0 by making set current select signal SIS to become to " L " and make resetting current select signal RIS to become, write " 1 " from " L " from " H ".When reading " 0 ", bit line BL0 is connected with earthing potential, be " H ", make set current Iset flow through source line SL0 by making resetting current select signal RIS to become to " L " and make set current select signal SIS to become, write " 0 " from " L " from " H ".
Write activity, after reading, the input current pulse afterwards, is flow through writing of data to be imported (value of Di) by making reciprocal electric current equally.
By before writing, applying reciprocal current impulse in the above described manner, just can carry out the rewriting of unlimited number of times, even when reading, carry out the mode of write-back, so owing to also be out of question without limits to writing indegree.
In an embodiment, write the ratio of components height of the Te in the chalkogenide of the bit line side of phase-change element R, and the ratio of components height of the Ge in the chalkogenide of transistor side, Sb owing to constantly have electric current to flow to source line SL from bit line BL.
In the present embodiment, in ablation process, make direction of current reverse.Therefore, even occur departing from,, the pulse that applies current opposite in direction forms the original state that turns back to owing to can making departing from of composition eliminate and make owing to writing to make to form.Its result can prevent to follow the segregation of composition of the chalkogenide of ionic conduction, and can write indegree increases, and can carry out the rewriting of unlimited number of times.
Figure 24 illustrates the planimetric map of storage array.Word line WL is formed by polysilicon layer (PS), and source line SL is formed by the 1st wiring layer M1, and bit line BL is formed by the 2nd wiring layer M2.In addition, bit line BL and the parallel formation of source line SL.
In addition, in the present embodiment, read combination with destruction and describe, be used in combination, just can obtain increasing the effect of rewriting number of times by utilizing positive negative pulse stuffing to write but might not read with destruction.
[embodiment 7]
Figure 25 illustrates the example of using the manner to constitute the multiport storage array.Each bit line is connected with two selector switch SW, and for example, bit line BL0 utilizes switch SW 00 to be connected with read/write circuit RWC0, is connected with RWC1 through switch SW 10.By this constituted mode, can parallel processing read action and write activity.In addition, use the manner can utilize writing fashionable data of reading and test, can effectively utilize data.
For example, read the action and the occasion of write activity, when utilizing SW00 that BL0 is connected to RWC0 to read action, can utilize switch SW 11 that BL1 is connected with read/write circuit RWC1 and carry out write activity in parallel processing.
Along with significantly popularizing of portable machine, the needs of nonvolatile memory are expanded.The storer that particularly requirement easily and logical circuit loads in mixture, can write at a high speed, can write often, driving voltage is low.Phase transition storage is the memory component that expection can have all these features.
Realize stable the present invention who writes of phase transition storage, very big to the practicability contribution of phase transition storage.Particularly load in mixture in microcomputer, the IC-card at nonvolatile memory, widely used possibility is very big.
Claims (27)
1. a semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
The 2nd pulse current writing information that utilization is flow through the 1st pulse current of above-mentioned bit line and flow through on the opposite direction of above-mentioned the 1st pulse current.
2. semiconductor storage as claimed in claim 1 is characterized in that: the pulse width of above-mentioned the 1st pulse current is different with the pulse width of above-mentioned the 2nd pulse current.
3. semiconductor storage as claimed in claim 2 is characterized in that: the pulse width of above-mentioned the 1st pulse current is longer than the pulse width of above-mentioned the 2nd pulse current.
4. semiconductor storage as claimed in claim 1 is characterized in that: the amplitude of above-mentioned the 1st pulse current is different with the amplitude of above-mentioned the 2nd pulse current.
5. semiconductor storage as claimed in claim 4 is characterized in that: the amplitude of above-mentioned the 2nd pulse current of the amplitude ratio of above-mentioned the 1st pulse current is big.
6. semiconductor storage as claimed in claim 1 is characterized in that: above-mentioned selection element is made of the MIS transistor npn npn.
7. semiconductor storage as claimed in claim 1 is characterized in that: above-mentioned selection element is made of bipolar transistor.
8. semiconductor storage as claimed in claim 1 is characterized in that: above-mentioned selection element is made of knot.
9. semiconductor storage as claimed in claim 1 is characterized in that: above-mentioned information storage part is to constitute by the 1st electrode layer, because of the phase-change material layers and the 2nd electrode layer of heating resistance change.
10. semiconductor storage as claimed in claim 9 is characterized in that: above-mentioned phase-change material layers is the material that comprises Te at least.
11. a semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
Be provided with the 1st pulse current that flows through above-mentioned bit line and have amplitude different or the 2nd pulse current of pulse width, utilize the 1st pulse combined that constitutes by above-mentioned the 1st pulse with continuous above-mentioned the 2nd pulse of above-mentioned the 1st pulse and by above-mentioned the 2nd pulse and the 2nd pulse combined writing information that constitutes with continuous above-mentioned the 1st pulse of above-mentioned the 2nd pulse with above-mentioned the 1st pulse current.
12. a semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
Utilization flow through above-mentioned bit line the relatively short pulse width with 50～1000 microamperes bigger amplitude and 5～100 nanoseconds the 1st pulse current and with above-mentioned the 1st pulse current continuous have smaller amplitude and 50～1000 nanoseconds pulse width and 2nd a pulse current writing information opposite of 20～400 microamperes with above-mentioned the 1st pulse current direction.
13. semiconductor storage, have by be arranged on many word lines, across multiple bit lines that insulation course and above-mentioned word line intersect and the information storage part on the intersection point of the source line that insulation course and above-mentioned word line or above-mentioned bit line intersect and a plurality of storage unit of selecting element to form, it is characterized in that:
Be applied to voltage pulse width on above-mentioned bit line and the above-mentioned source line all more than or equal to 5ns and smaller or equal to 100ns.
14. semiconductor storage as claimed in claim 9 is characterized in that: above-mentioned phase-change material is to be made of greater than two or more elements of 0.3 electronegative difference.
15. semiconductor storage, have by being arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect, the contact bed adjacent and a plurality of storage unit of selecting element to form, it is characterized in that with above-mentioned information storage part:
Utilization with the direction of above-mentioned word line quadrature on the 1st pulse current that flows through and the 2nd pulse current writing information that on the opposite direction of above-mentioned the 1st pulse current, flows through, the composition of above-mentioned contact bed is silicon or carbon.
16. a semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
Utilization flows through the 1st pulse current of above-mentioned bit line, than above-mentioned the 1st pulse current amplitude little the 2nd pulse current and the 3rd pulse current writing information, any in above-mentioned the 1st, above-mentioned the 2nd, above-mentioned the 3rd pulse current flows in different directions.
17. a semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
Two or more pulse current writing informations that utilization is flow through the 1st pulse current of above-mentioned bit line and flow through on the opposite direction of above-mentioned the 1st pulse current.
18. semiconductor storage, have by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, it is characterized in that: flow through pulse current in above-mentioned bit line, the voltage of above-mentioned word line and the amplitude of above-mentioned pulse current are got 3 values respectively.
19. microcomputer that loads in mixture semiconductor storage, this semiconductor storage has by a plurality of storage unit that are arranged on many word lines and the information storage part on the intersection point of the multiple bit lines that insulation course and above-mentioned word line intersect and select element to form, and it is characterized in that:
The 2nd pulse current writing information that utilization is flow through the 1st pulse current of above-mentioned bit line and flow through on the opposite direction of above-mentioned the 1st pulse current.
20. a semiconductor device is characterized in that having:
Many word lines,
The multiple bit lines that intersects with above-mentioned many word lines,
Be arranged on the intersection point of above-mentioned many word lines and above-mentioned multiple bit lines a plurality of storage unit and
Read/write circuit,
Above-mentioned a plurality of storage unit comprises phase-change element,
When reading action, will rewrite from the information that above-mentioned a plurality of storage unit are read.
21. semiconductor device as claimed in claim 20 is characterized in that: when write activity, the information of reading is used the information displacement that writes from the outside and the information after the above-mentioned displacement is written to storage unit.
22. semiconductor device as claimed in claim 20 is characterized in that: above-mentionedly reading, utilizing same drives said memory cells in above-mentioned rewriting and above-mentioned the writing.
23. semiconductor device as claimed in claim 20 is characterized in that: above-mentioned read and above-mentioned rewriting between, before above-mentioned rewrite pulse electric current, apply pulse current opposite polarity with it.
24. semiconductor device as claimed in claim 21 is characterized in that: above-mentioned read and above-mentioned writing between, apply pulse current opposite polarity above-mentioned before writing pulse current with it.
25. a semiconductor device is characterized in that having:
Many word lines,
The multiple bit lines that intersects with above-mentioned many word lines and
Be arranged on a plurality of storage unit on the intersection point of above-mentioned many word lines and above-mentioned multiple bit lines;
Above-mentioned a plurality of storage unit comprises phase-change element respectively;
The high level of above-mentioned word line is 5MV/cm or lower voltage than the supply voltage height that drives above-mentioned bit line with respect to gate oxidation films.
26. a semiconductor device is characterized in that having:
Many word lines,
The multiple bit lines that intersects with above-mentioned many word lines and
Be arranged on a plurality of storage unit on the intersection point of above-mentioned many word lines and above-mentioned multiple bit lines;
Above-mentioned a plurality of storage unit comprises phase-change element respectively;
The low level of above-mentioned word line is lower than earthing potential.
27. a semiconductor device is characterized in that having:
Many word lines,
The multiple bit lines that intersects with above-mentioned many word lines,
Be arranged on the intersection point of above-mentioned many word lines and above-mentioned multiple bit lines a plurality of storage unit and
A plurality of sensing circuits that write;
Above-mentioned a plurality of storage unit comprises phase-change element respectively;
Above-mentioned a plurality of storage unit can be connected simultaneously with corresponding above-mentioned a plurality of sensing circuits that write.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005-034155 | 2005-02-10 | ||
| JP2005034155A JP4535439B2 (en) | 2005-02-10 | 2005-02-10 | Semiconductor integrated circuit device |
| JP2005034155 | 2005-02-10 | ||
| JP2005116612 | 2005-04-14 | ||
| JP2005-116612 | 2005-04-14 | ||
| JP2005116612A JP4668668B2 (en) | 2005-04-14 | 2005-04-14 | Semiconductor device |
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| CN1819059A true CN1819059A (en) | 2006-08-16 |
| CN1819059B CN1819059B (en) | 2012-07-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200610006409XA Expired - Fee Related CN1819059B (en) | 2005-02-10 | 2006-01-20 | Semiconductor memory device |
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| JP (1) | JP4535439B2 (en) |
| CN (1) | CN1819059B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102057438A (en) * | 2008-06-11 | 2011-05-11 | Nxp股份有限公司 | Phase change memory device and control method |
| US8987701B2 (en) | 2009-05-28 | 2015-03-24 | Cornell University | Phase transition memories and transistors |
| CN105283920A (en) * | 2013-05-29 | 2016-01-27 | 惠普发展公司，有限责任合伙企业 | Writable device based on alternating current |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
| CN112447205A (en) * | 2019-09-05 | 2021-03-05 | 铠侠股份有限公司 | Semiconductor memory device with a plurality of memory cells |
| CN112447203A (en) * | 2019-09-05 | 2021-03-05 | 铠侠股份有限公司 | Semiconductor memory device with a plurality of memory cells |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4742696B2 (en) * | 2005-06-27 | 2011-08-10 | ソニー株式会社 | Storage device |
| KR100738092B1 (en) * | 2006-01-05 | 2007-07-12 | 삼성전자주식회사 | Method of operating a phase change memory device with multi-bits |
| KR101296288B1 (en) * | 2006-12-29 | 2013-08-14 | 삼성전자주식회사 | Non-volatile memory device and method of operating the same |
| KR100851548B1 (en) * | 2007-01-23 | 2008-08-11 | 삼성전자주식회사 | Phase change memory device and method of forming the same |
| JP5225372B2 (en) | 2008-04-01 | 2013-07-03 | 株式会社東芝 | Information recording / reproducing device |
| CN102422361B (en) | 2010-03-30 | 2014-03-19 | 松下电器产业株式会社 | Non-volatile storage device and method for writing to non-volatile storage device |
| JP5672143B2 (en) * | 2011-05-16 | 2015-02-18 | 日本電気株式会社 | Control method of resistance change element and semiconductor device |
| CN106571160A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Processing method of phase change memory |
| US10134470B2 (en) | 2015-11-04 | 2018-11-20 | Micron Technology, Inc. | Apparatuses and methods including memory and operation of same |
| US10446226B2 (en) | 2016-08-08 | 2019-10-15 | Micron Technology, Inc. | Apparatuses including multi-level memory cells and methods of operation of same |
| US10157670B2 (en) * | 2016-10-28 | 2018-12-18 | Micron Technology, Inc. | Apparatuses including memory cells and methods of operation of same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4134637B2 (en) * | 2002-08-27 | 2008-08-20 | 株式会社日立製作所 | Semiconductor device |
| JP2004273615A (en) * | 2003-03-06 | 2004-09-30 | Matsushita Electric Ind Co Ltd | Resistance change type memory |
| DE102004016408B4 (en) * | 2003-03-27 | 2008-08-07 | Samsung Electronics Co., Ltd., Suwon | Phase change memory module and associated programming method |
-
2005
- 2005-02-10 JP JP2005034155A patent/JP4535439B2/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102057438A (en) * | 2008-06-11 | 2011-05-11 | Nxp股份有限公司 | Phase change memory device and control method |
| US8987701B2 (en) | 2009-05-28 | 2015-03-24 | Cornell University | Phase transition memories and transistors |
| CN105283920A (en) * | 2013-05-29 | 2016-01-27 | 惠普发展公司，有限责任合伙企业 | Writable device based on alternating current |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
| CN105336378B (en) * | 2014-07-03 | 2018-10-19 | 中芯国际集成电路制造(上海)有限公司 | Phase-change memory cell test structure and test method, phase transition storage |
| CN112447205A (en) * | 2019-09-05 | 2021-03-05 | 铠侠股份有限公司 | Semiconductor memory device with a plurality of memory cells |
| CN112447203A (en) * | 2019-09-05 | 2021-03-05 | 铠侠股份有限公司 | Semiconductor memory device with a plurality of memory cells |
| CN112447205B (en) * | 2019-09-05 | 2023-07-28 | 铠侠股份有限公司 | Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell |
| CN112447203B (en) * | 2019-09-05 | 2024-03-08 | 铠侠股份有限公司 | Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006221737A (en) | 2006-08-24 |
| JP4535439B2 (en) | 2010-09-01 |
| CN1819059B (en) | 2012-07-18 |
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