CN1818694A - Crystal wafer for testing aging and electricity performances and construction thereof - Google Patents
Crystal wafer for testing aging and electricity performances and construction thereof Download PDFInfo
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- CN1818694A CN1818694A CN 200510008164 CN200510008164A CN1818694A CN 1818694 A CN1818694 A CN 1818694A CN 200510008164 CN200510008164 CN 200510008164 CN 200510008164 A CN200510008164 A CN 200510008164A CN 1818694 A CN1818694 A CN 1818694A
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- crystalline substance
- generative circuit
- naked crystalline
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Abstract
A wafer being able to carry out ageing and electrical test consists of the first die, scribe line, the first ageing pattern generation circuit and electrode pad .It is featured as forming scribe line on wafer at external of the first die, utilizing said circuit to carryout ageing test on the first die, setting said pad on scribe line and electric-connecting said pad to said circuit.
Description
[technical field]
The invention relates to a kind of wafer, and particularly relevant for a kind of wafer and implementation method thereof of implementing aging and testing electrical property.
[background technology]
Aging (aging) test is test of semiconductor integrated circuit (Integrated CircuitReliability, IC RA) one of big event generally is just to carry out burn-in test after being a complete IC in that naked crystalline substance (die) cutting (saw) and encapsulation (package) are finished.The fundamental purpose of burn-in test be before shipment from mass-produced SIC (semiconductor integrated circuit) (IC), will have the IC of hiding property defective to screen ahead of time, remove bad IC of the initial stage that may have in advance, in order to avoid shipment is to client.Generally speaking, can utilize tester table (tester) or patterning generator (pattern generator/Gen) that input signal is sent among the IC earlier, under high temperature, carry out burn-in test simultaneously.Again by the display panel of watching tester table (panel), distinguishing the quality of IC, and the IC that damages is eliminated.
Yet, because the probe of tester table is difficult to contact simultaneously the electronic pads of all naked crystalline substances on the wafer, so must adopt the mode of the naked crystalline substance of measuring semiconductor one by one.Thus, the required test duration is extremely long, and the cost cost is too high, can't finish a large amount of tests at short notice, even can only do part sampling and testing (sampletest), just can't carry out the full test for all IC finished products.In addition rather ineffective for the service efficiency of the tester of costliness owing to adopt the naked crystalline substance of measuring semiconductor one by one, can reduce its cost benefit, also can't shorten simultaneously consistent process required time (Turn-around-time, TAT).
[summary of the invention]
In view of this, purpose of the present invention is exactly that a kind of implement wafer and implementation method thereof aging and testing electrical property are being provided, change the process that after encapsulation, just wears out that has now, on wafer, promptly wear out simultaneously and testing electrical property, in the hope of reducing Production Time, raise the efficiency, and the conservation cost consumption.
According to purpose of the present invention, a kind of wafer (wafer) is proposed, comprise the first naked crystalline substance (die), Cutting Road (scribe line), the first aging pattern generative circuit (aging pattern generation circuit) and electronic pads (pad).Cutting Road is formed on the wafer outside the first naked crystalline substance, and the first aging pattern generative circuit is in order to carry out burn-in test to the first naked crystalline substance.Electronic pads is arranged on the Cutting Road and with the first aging pattern generative circuit and electrically connects, and electronic pads is in order to electrically connect with a voltage source.
According to purpose of the present invention, reintroduce a kind of method that may be implemented in the burn-in test of above-mentioned wafer.At first, provide this wafer.Then, electrically connect electronic pads and voltage source, last, the first aging pattern generative circuit wears out and testing electrical property to the first naked crystalline substance.
According to another object of the present invention, reintroduce a kind of method of aging and testing electrical property, comprise the following steps: (1). the first naked crystalline substance and the second naked crystalline substance of built-in aging pattern generative circuit are provided; (2). a proving installation is provided; And (3). with proving installation, simultaneously the first naked crystalline substance is made testing electrical property and the second naked crystalline substance is made burn-in test.
According to another object of the present invention, a kind of method of aging and testing electrical property is more proposed, comprise the following steps: (1). the first naked crystalline substance and the second naked crystalline substance are provided; (2). a proving installation that comprises aging pattern generative circuit is provided; And (3). with proving installation, simultaneously the first naked crystalline substance is made testing electrical property and the second naked crystalline substance is made burn-in test.
It is noted that, the method for aforesaid aging and testing electrical property, be can be in cutting (saw) naked brilliant execution the after the preceding or cutting.
[description of drawings]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A and Figure 1B illustrate the synoptic diagram of the wafer that is first embodiment of the invention.
It is the process flow diagram that carries out the method for burn-in test on the wafer of first embodiment of the invention that Fig. 1 C illustrates.
Fig. 2 A and Fig. 2 B illustrate the synoptic diagram of the wafer that is second embodiment of the invention.
It is the process flow diagram that carries out the method for burn-in test on the wafer of second embodiment of the invention that Fig. 2 C illustrates.
Fig. 3 A illustrates the synoptic diagram of the wafer that is third embodiment of the invention.
It is the process flow diagram that carries out the method for burn-in test on the wafer of third embodiment of the invention that Fig. 3 B illustrates.
It is process flow diagram according to the method for the aging and testing electrical property of fourth embodiment of the invention that Fig. 4 illustrates.
It is process flow diagram according to the method for the aging and testing electrical property of fifth embodiment of the invention that Fig. 5 illustrates.
[embodiment]
First embodiment
Each naked crystalline substance is provided with built-in aging pattern generative circuit, as long as provide a voltage source to naked crystalline substance, just can produce degraded test pattern (aging pattern), carries out burn-in test.Please refer to Figure 1A and Figure 1B, illustrate the synoptic diagram of the wafer that is first embodiment of the invention.Since have on the wafer have in a large number the identical practice naked crystalline substance, for ease of clear explanation, do representative with six naked crystalline substances with identical practice at this.As shown in Figure 1A, comprise first naked brilliant 110, the first aging pattern generative circuit (aging patterngeneration circuit) 120, electronic pads (pad) 130 and Cutting Road (scribe line) 140 on the wafer 100.
Cutting Road 140 is on the wafer 100 that is formed at outside first naked brilliant 110.That is, between any two adjacent naked crystalline substances on the wafer 100, leave Cutting Road 140, with as the gap of cutting between the naked crystalline substance.After wafer 100 cuttings are finished, just only stay naked crystalline substance.
Each aging pattern generative circuit is in order to carry out burn-in test to its corresponding naked crystalline substance.In first embodiment, the first aging pattern generative circuit 120 is in order to carry out burn-in test to first naked brilliant 110, is built on first naked brilliant 110 in being.And electronic pads 130 is arranged on the Cutting Road 140, in order to electrically connect with a voltage source (not being shown on the figure).Electronic pads 130 also electrically connects with the first aging pattern generative circuit 120.
Wafer among first embodiment of the invention described above is the method that can pass through the burn-in test of a wafer, and the naked crystalline substance on the wafer is carried out burn-in test.Please be simultaneously with reference to Figure 1A and Fig. 1 C, it is the process flow diagram that carries out the method for burn-in test on the wafer of first embodiment of the invention that Fig. 1 C illustrates.The method comprises step 101～103, at first, in step 101, provides wafer 100.Then, in step 102, electrically connect electronic pads 130 and voltage source.At last, in step 103, first aging 120 pairs first naked brilliant 110 of the pattern generative circuits carry out burn-in test.
In addition, for the formation position of the first aging pattern generative circuit 120, within shown in Figure 1A, be built on first naked brilliant 110, also can be formed on the Cutting Road 140, shown in Figure 1B, and the flow process that illustrates of suitable Fig. 1 C.
Carry out in the method for burn-in test on the wafer of first embodiment of the invention, electronic pads 130 is that the position is on the Cutting Road of wafer 100, can directly utilize probe contact electrode pad 130 to carry out burn-in test so that voltage source to be provided, therefore go out wafer factory (FAB) before at wafer, can in wafer factory, finish burn-in test to all naked crystalline substances (die), and by the wafer pin survey (circuit probing, CP test) will have defective naked crystalline substance screen.
Second embodiment
Please refer to Fig. 2 A, illustrate the synoptic diagram of the wafer that is second embodiment of the invention.As shown in Fig. 2 A, comprise first naked brilliant 210, a plurality of second naked brilliant 211, the first aging pattern generative circuit 220, a plurality of second aging pattern generative circuit 221, electronic pads 230, Cutting Road 240 and cabling 250 on the wafer 200.
Cutting Road 240 is on the wafer 200 that is formed at outside first naked brilliant 210 and second naked brilliant 211.That is, between any two adjacent naked crystalline substances on the wafer 200, leave Cutting Road 240, with as the gap of cutting between the naked crystalline substance.After wafer 200 cuttings are finished, just only stay naked crystalline substance.
Each aging pattern generative circuit is in order to carrying out burn-in test to corresponding naked crystalline substance, but all aging pattern generative circuits all electrically connect with an electronic pads.In second embodiment, the first aging pattern generative circuit 220 is in order to carry out burn-in test to first naked brilliant 210, and the second aging pattern generative circuit 221 is then in order to carry out burn-in test to second naked brilliant 211.Be built on first naked brilliant 110 in the first aging pattern generative circuit 220, the second aging pattern generative circuit 221 is built on second naked brilliant 211 in then.
Wafer among second embodiment of the invention described above is the method that can pass through the burn-in test of a wafer, and the naked crystalline substance on the wafer is carried out burn-in test.Please be simultaneously with reference to Fig. 2 A and Fig. 2 C, it is the process flow diagram that carries out the method for burn-in test on the wafer of second embodiment of the invention that Fig. 2 C illustrates.The method comprises step 201～203, at first, in step 201, provides wafer 200.Then, in step 202, electrically connect electronic pads 230 and voltage source.At last, in step 203, the first aging pattern generative circuit 220 and the second aging pattern generative circuit 221 carry out burn-in test to first naked brilliant 210 and second naked brilliant 211 respectively simultaneously.
In addition, for the formation position of the first aging pattern generative circuit 220, within shown in Fig. 2 A, be built on first naked brilliant 210, also can be formed on the Cutting Road 240, shown in Fig. 2 B, and the flow process that illustrates of suitable Fig. 2 C.
Carry out the method for burn-in test on the wafer of second embodiment of the invention,, can carry out burn-in test, can significantly raise the efficiency, and save cost consumption a plurality of naked crystalline substances as long as electrically connect electronic pads and voltage source.
The 3rd embodiment
On Cutting Road, only do one group of aging pattern generative circuit, make all naked crystalline substances produce degraded test pattern individually, further carry out burn-in test.Please refer to Fig. 3 A, illustrating is the wafer synoptic diagram of third embodiment of the invention.As shown in Fig. 3 A, comprise first naked brilliant 310, a plurality of second naked brilliant 311, the first aging pattern generative circuit 320, electronic pads 330, Cutting Road 340 and cabling 350 on the wafer 300.
Cutting Road 340 is on the wafer 300 that is formed at outside first naked brilliant 310 and second naked brilliant 311.That is, between any two adjacent naked crystalline substances on the wafer 300, leave Cutting Road 340, with as the gap of cutting between the naked crystalline substance.After wafer 300 cuttings are finished, just only stay naked crystalline substance.
Use an aging pattern generative circuit, all naked crystalline substances are carried out burn-in test.In the 3rd embodiment, the first naked brilliant 310 and first aging pattern generative circuit 320 electrically connects, and a plurality of second naked brilliant 311 passes through the cabling 350 and first aging pattern generative circuit 320 electric connections.And electronic pads 330 is to be arranged on the Cutting Road 340, in order to electrically connect with a voltage source (not being shown on the figure).Electronic pads 330 also electrically connects with the first aging pattern generative circuit 320.
Wafer among the 3rd above-mentioned embodiment is the method that can pass through the burn-in test of a wafer, and the naked crystalline substance on the wafer is carried out burn-in test.Please be simultaneously with reference to Fig. 3 A and Fig. 3 B, it is the process flow diagram that carries out the method for burn-in test on the wafer of third embodiment of the invention that Fig. 3 B illustrates.The method comprises step 301～303, at first, in step 301, provides wafer 300.Then, in step 302, electrically connect electronic pads 330 and voltage source.At last, in step 303, first aging 320 pairs first naked brilliant 310 and a plurality of second naked brilliant 311 of the pattern generative circuits carry out burn-in test simultaneously.
When being connected as the first aging pattern generative circuit of burn in test circuit and tested naked crystalline substance, when being formed on the Cutting Road of wafer, when cutting crystal wafer, can cut off the test distribution really, and the reservation distribution after cutting off is the shortest, can avoid keeping the harmful effect that distribution causes.Also can when carrying out the survey of wafer pin, directly carry out burn-in test by tester table, to finish whole testing process.
Above-mentioned three embodiment have disclosed wafer and the implementation method thereof that can implement to wear out, change to have the process that just wears out now after encapsulation, promptly carry out burn-in test on wafer.In addition, in following the 4th embodiment and the 5th embodiment, disclosed and on wafer, can implement method aging and testing electrical property simultaneously, in the hope of reducing process time, raise the efficiency, and saved cost consumption.
The 4th embodiment
Please refer to Fig. 4, it illustrates is process flow diagram according to the method for the aging and testing electrical property of fourth embodiment of the invention.This aging method with testing electrical property comprises step 401～404, at first, in step 401, provides the first naked crystalline substance and the second naked crystalline substance of built-in aging pattern generative circuit.Then, in step 402, provide a proving installation.Afterwards, in step 403,, simultaneously the first naked crystalline substance is made testing electrical property and the second naked crystalline substance is made burn-in test with this proving installation.At last, in step 404,, simultaneously the second naked crystalline substance is made testing electrical property and the first naked crystalline substance is made burn-in test with this proving installation.
The 5th embodiment
Please refer to Fig. 5, it illustrates is process flow diagram according to the method for the aging and testing electrical property of fifth embodiment of the invention.This aging method with testing electrical property comprises step 501～504, at first, in step 501, provides the first naked crystalline substance and the second naked crystalline substance.Then, in step 502, provide a proving installation that comprises aging pattern generative circuit.Afterwards, in step 503,, simultaneously the first naked crystalline substance is made testing electrical property and the second naked crystalline substance is made burn-in test with this proving installation.At last, in step 504,, simultaneously the second naked crystalline substance is made testing electrical property and the first naked crystalline substance is made burn-in test with this proving installation.
For the formation position of aging pattern generative circuit, also inequality in the 4th above-mentioned embodiment and the 5th embodiment.In the 4th embodiment, aging pattern generative circuit is built on the naked crystalline substance in being, and in the 5th embodiment, aging pattern generative circuit then is arranged in the proving installation.And the disclosed method of the 4th embodiment can be used with first, second embodiment cross-reference.In addition, the disclosed method of the 5th embodiment can be used with the first, the 3rd embodiment cross-reference.
It is noted that, the method for the aging and testing electrical property of the 4th embodiment and the 5th embodiment, be can be in cutting (saw) naked brilliant execution the after the preceding or cutting.
Disclosed wafer and its implementation method of implementing aging and testing electrical property of the above embodiment of the present invention, can use the digital test board to wear out and testing electrical property, therefore improved the speed of test greatly, and also reduced the cost of test, simultaneously, owing to be used for doing the aging pattern generative circuit of proving installation, electronic pads and cabling etc., preferably be to be positioned on the Cutting Road of wafer, therefore also do not increase any manufacturing cost.In addition, the present invention changes and has the process that just wears out after encapsulation now, promptly wears out simultaneously and testing electrical property on wafer, can significantly raise the efficiency cost-effective expending.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (21)
1. wafer comprises:
One first naked crystalline substance;
One Cutting Road is formed on this wafer outside this first naked crystalline substance;
One first aging pattern generative circuit, this first aging pattern generative circuit is in order to carry out burn-in test to this first naked crystalline substance; And
One electronic pads is arranged on this Cutting Road and electrically connects with this first aging pattern generative circuit, and this electronic pads is in order to electrically connect with a voltage source.
2. wafer according to claim 1 is characterized in that, this wafer more comprises:
One second naked crystalline substance; And
One second aging pattern generative circuit, this second aging pattern generative circuit is in order to carry out burn-in test to this second naked crystalline substance, and this second aging pattern generative circuit system and this electronic pads electrically connect;
Wherein, when this electronic pads and the electric connection of this voltage source, this first aging pattern generative circuit and this second aging pattern generative circuit carry out burn-in test to this first naked crystalline substance and this second naked crystalline substance respectively simultaneously.
3. wafer according to claim 2 is characterized in that, this electronic pads system utilizes a cabling, electrically connects with this first aging pattern generative circuit and this second aging pattern generative circuit.
4. wafer according to claim 2 is characterized in that, this first aging pattern generative circuit and this second aging pattern generative circuit are to be built on this first naked crystalline substance and this second naked crystalline substance in separately or to be formed at separately on this Cutting Road.
5. wafer according to claim 1 is characterized in that, this wafer more comprises one second naked crystalline substance, electrically connects with this first aging pattern generative circuit; When this electronic pads and the electric connection of this voltage source, this first aging pattern generative circuit carries out burn-in test to this first naked crystalline substance and this second naked crystalline substance simultaneously.
6. wafer according to claim 5 is characterized in that, this first aging pattern generative circuit is to utilize a cabling, with this first naked crystalline substance and this second naked brilliant electric connection.
7. wafer according to claim 5 is characterized in that, this first aging pattern generative circuit is to be formed on this Cutting Road.
8. wafer according to claim 1 is characterized in that, is built on this first naked crystalline substance in this first aging pattern generative circuit system or is formed on this Cutting Road.
9. method of implementing the burn-in test of the described wafer of claim 1 comprises:
This wafer is provided;
Electrically connect this electronic pads and this voltage source; And
This first aging pattern generative circuit carries out burn-in test to this first naked crystalline substance that is positioned on this wafer.
10. the method for burn-in test according to claim 9 is characterized in that, after this carries out burn-in test, more comprises:
Cut this wafer along this Cutting Road.
11. the method for burn-in test according to claim 9 is characterized in that, is built on this first naked crystalline substance in this first aging pattern generative circuit system or is formed on this Cutting Road.
12. the method for burn-in test according to claim 9, it is characterized in that, this wafer more comprises one second naked crystalline substance and one second aging pattern generative circuit, this second aging pattern generative circuit is in order to carry out burn-in test to this second naked crystalline substance, this second aging pattern generative circuit system and this electronic pads electrically connect, wherein, carry out in the step of burn-in test in this, this first aging pattern generative circuit and this second aging pattern generative circuit carry out burn-in test to this first naked crystalline substance and this second naked crystalline substance respectively.
13. the method for burn-in test according to claim 12 is characterized in that, this electronic pads system utilizes a cabling, electrically connects with this first aging pattern generative circuit and this second aging pattern generative circuit.
14. the method for burn-in test according to claim 12 is characterized in that, this first aging pattern generative circuit and this second aging pattern generative circuit are to be built on this first naked crystalline substance and this second naked crystalline substance in separately or to be formed at separately on this Cutting Road.
15. the method for burn-in test according to claim 9 is characterized in that, this wafer more comprises one second naked crystalline substance, and this second naked crystalline substance and this first aging pattern generative circuit electrically connect; Wherein, carry out in the step of burn-in test in this, this first aging pattern generative circuit carries out burn-in test to this first naked crystalline substance and this second naked crystalline substance simultaneously.
16. the method for burn-in test according to claim 15 is characterized in that, this first aging pattern generative circuit is to utilize a cabling, with this first naked crystalline substance and this second naked brilliant electric connection.
17. the method for burn-in test according to claim 15 is characterized in that, this first aging pattern generative circuit is to be formed on this Cutting Road.
18. the method for aging and testing electrical property comprises the following steps:
The one first naked crystalline substance and the one second naked crystalline substance of built-in one aging pattern generative circuit are provided;
One proving installation is provided; And
With this proving installation, simultaneously this first naked crystalline substance is made testing electrical property and this second naked crystalline substance is made burn-in test.
19. the method for aging and testing electrical property according to claim 18 is characterized in that, more comprises:
With this proving installation, simultaneously this second naked crystalline substance is made testing electrical property and this first naked crystalline substance is made burn-in test.
20. the method for aging and testing electrical property comprises the following steps:
One first naked crystalline substance and one second naked crystalline substance are provided;
A proving installation that comprises an aging pattern generative circuit is provided; And
With this proving installation, simultaneously this first naked crystalline substance is made testing electrical property and this second naked crystalline substance is made burn-in test.
21. the method for aging and testing electrical property according to claim 20 is characterized in that, more comprises:
With this proving installation, simultaneously this second naked crystalline substance is made testing electrical property and this first naked crystalline substance is made burn-in test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510008164 CN100533163C (en) | 2005-02-08 | 2005-02-08 | Crystal wafer for testing aging and electricity performances and construction thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510008164 CN100533163C (en) | 2005-02-08 | 2005-02-08 | Crystal wafer for testing aging and electricity performances and construction thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1818694A true CN1818694A (en) | 2006-08-16 |
| CN100533163C CN100533163C (en) | 2009-08-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510008164 Expired - Fee Related CN100533163C (en) | 2005-02-08 | 2005-02-08 | Crystal wafer for testing aging and electricity performances and construction thereof |
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| Country | Link |
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| CN (1) | CN100533163C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101311737B (en) * | 2007-05-23 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Wafer quality control method |
| CN101320075B (en) * | 2007-06-06 | 2011-11-23 | 日商日本工程技术股份有限公司 | Connector |
| CN102565570A (en) * | 2010-12-02 | 2012-07-11 | Tdk株式会社 | Method for performing burn-in test |
| CN101968527B (en) * | 2009-07-27 | 2013-06-19 | 智邦科技股份有限公司 | System-level encapsulation device batch test method and device batch test system thereof |
| WO2013097213A1 (en) * | 2011-12-31 | 2013-07-04 | 北京大学深圳研究生院 | High-temperature burn-in test method and device for contactless wl/wlp chip |
-
2005
- 2005-02-08 CN CN 200510008164 patent/CN100533163C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101311737B (en) * | 2007-05-23 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Wafer quality control method |
| CN101320075B (en) * | 2007-06-06 | 2011-11-23 | 日商日本工程技术股份有限公司 | Connector |
| CN101968527B (en) * | 2009-07-27 | 2013-06-19 | 智邦科技股份有限公司 | System-level encapsulation device batch test method and device batch test system thereof |
| CN102565570A (en) * | 2010-12-02 | 2012-07-11 | Tdk株式会社 | Method for performing burn-in test |
| CN102565570B (en) * | 2010-12-02 | 2015-02-11 | Tdk株式会社 | Method for performing burn-in test |
| WO2013097213A1 (en) * | 2011-12-31 | 2013-07-04 | 北京大学深圳研究生院 | High-temperature burn-in test method and device for contactless wl/wlp chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100533163C (en) | 2009-08-26 |
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Granted publication date: 20090826 Termination date: 20140208 |