CN1809931B - 沟槽mos结构 - Google Patents

沟槽mos结构 Download PDF

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CN1809931B
CN1809931B CN2004800171512A CN200480017151A CN1809931B CN 1809931 B CN1809931 B CN 1809931B CN 2004800171512 A CN2004800171512 A CN 2004800171512A CN 200480017151 A CN200480017151 A CN 200480017151A CN 1809931 B CN1809931 B CN 1809931B
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source electrode
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CN1809931A (zh
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R·J·E·许廷
E·A·海曾
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Nexperia BV
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Abstract

一种半导体器件具有邻近单元(18)的沟槽(42)。该单元包括相反导电类型的中心本体(40)以及源极和漏极接触区(26、28)。该器件是双向的，并且在相对低的接通电阻的情况下沿任一方向控制电流。优选实施例包括电位极板(60)，其与源极和漏极漂移区(30、32)一起起作用以产生RESURF效果。

Description

沟槽MOS结构
技术领域
本发明涉及沟槽MOS结构，具体涉及用于双向开关的横向沟槽MOS结构。
背景技术
对于许多应用来说，具有能够转换负和正偏压的开关是有吸引力的。例如，在由可再充电的电池或单电池所供电的便携式装置中，使用功率开关来把电池连接到装置上。该功率开关需要能够阻塞沿任一方向流过它的电流。
一种解决方法是使用串联的两个低电压沟槽金属氧化物半导体场效应晶体管(MOSFET)。这两个MOSFET的漏极或源极分别以共漏或共源的方式连接在一起。当两个MOSFET都接通时，该对导通以充电。该方法的缺点在于使用两个MOSFET增加了大于单个器件的电阻的该对的电阻。
现有解决方法是图1所示意性地示出的所谓的ACCUFET。n+衬底2具有形成淀积在顶部上的本体的n型外延层4。沟槽栅极6垂直延伸进入外延层4，该栅极6通过薄的栅绝缘体8与外延层4绝缘。N+源极扩散10邻近栅极设置，并且前接触12和后接触14连接该结构。
在使用中，电子在施加到沟槽栅极6的电压的控制下从源极扩散10流到衬底2。
与常规的垂直沟槽MOS结构不同，图1的ACCUFET不具有p型本体。这样做是为了提供两种方式的阻塞，并通过省去沟道电阻来降低总的接通电阻。然而，存在多个缺点。首先，对沟槽栅极6之间的横向掺杂浓度的积分存在相当大的限制。掺杂浓度轮廓必须是这样的，即当栅极电压为负时，每个沟槽的耗尽层到达中心以夹断源极和漏极间的电子电流。这在T Syau等人的1994年5月第41卷第5期的IEEE电子器件会刊上有更详细的讨论，其提出例如1×1014cm-3的掺杂浓度和1μm的台宽对低漏电流产生1×1010cm-2的积分，以及阈值电压的实际值。其次，该阈值电压很低。第三，衬底形成接通电阻的重要部分。
由此需要双向开关的改进的半导体结构。
发明内容
根据本发明的第一方面，提供具有相对的第一和第二主表面的半导体器件，包括：第一主表面处的本体区；具有从第一主表面延伸进入本体区的纵向隔开的源极和漏极注入的至少一个单元，该源极和漏极注入借助部分本体区与衬底隔开，并限定该源极和漏极注入之间的本体区的沟道部分；以及穿过本体区从源极注入纵向延伸到漏极注入的至少一个绝缘栅沟槽，该绝缘栅沟槽包括沿沟槽的底部和端壁和侧壁，通过栅极电介质来与源极和漏极注入以及本体区绝缘的栅导体，该源极和漏极注入沿沟槽的部分侧壁延伸，其中该源极和漏极注入包括垂直延伸进入本体直到不超过沟槽深度的35％的深度的第一主表面处的导电浅接触区。
该结构具有优于以上参考图1所描述的结构的多个优点。由于源极和漏极都在第一主表面上，因此衬底电阻不是总电阻的重要部分。
由于源极和漏极注入可容易地通过在衬底中的注入、可毫无困难地执行的常规半导体工艺来形成，因此该结构相对易于制造。
该结构制造相对简单的另一原因在于，它形成在单个半导体本体中，即集成在单个衬底上。在绝缘体上硅中，该半导体本体可以是例如半导体衬底上的外延层。此处不需要根据本发明的使用该方法的复杂混合结构。
应当理解，具有不同特性的多种现有技术的半导体器件是可用的。本发明目的在于，与低掺杂横向扩散MOS(LDMOS)技术相比，改善电流处理能力，或者换句话说是在击穿电压和特定接通电阻之间实现折衷，其比使用这种现有技术在双向器件中所获得的要好。
源极和漏极注入以及衬底之间的部分本体区的厚度应是足够的厚度，以便在一种导电类型的源区或漏区以及相反导电类型的衬底之间形成的二极管不随着施加到源极和漏极的设计电压而击穿。
所需的尺寸和厚度将取决于所需的击穿电压。对于20V-30V的器件来说，沟道长度可优选在0.5～2μm的范围内，以及n+源极和漏极与p本体的距离为大约0.5～1.5μm。
源区和漏区包括导电的浅接触区。为了使该区导电，通常将需要高掺杂，并且仅把此设置到浅深度可容易制造。该“浅”深度可优选不超过沟槽深度的35％，更优选不超过20％，最优选不超过10％。或者表达为，浅掺杂可以不多于0.5μm，优选不多于0.3μm。典型值位于0.15μm～0.25μm的范围内。
优选地，本体具有与接触相反的导电类型。使用与源极和漏极接触相反导电类型的本体避免了对本体层中的精确掺杂值的需要，其是用于图1的ACCUFET的情形。该结构通常是关断的。
在替换的不太优选的实施例中，本体区具有相同的导电类型。这具有的缺点在于，将需要结果形成低的总掺杂密度的相同的低掺杂浓度和宽度，如同在图1的垂直ACCUFET中一样-参见T Syau等(以上已引用)。
每个源极和漏极注入可以是具有在第一主表面处的接触区和垂直延伸进入接触区下方的本体的较低掺杂区的双掺杂注入，该较低掺杂区具有与接触区相同的第二导电类型，但具有更低的掺杂。
该双掺杂对于较高电压的应用和/或获得更高电流并相应地降低特定接通电阻是尤其有用的。
可获得更深的源极或漏极和更深的沟槽、更多的电流。双掺杂结构允许更高的电流值，而不需要对深入衬底的接触区注入优选的高掺杂密度，其将引起制造困难。优选地，较低掺杂区延伸到沟槽的至少80％的深度。
或者，在较低电压的应用中，源区和漏区可仅包括浅接触区。
在优选配置中，沟槽深度为0.5～2μm。
在优选实施例中，存在多个这种源极注入、与相应的源极注入纵向隔开的相应的多个漏极注入、以及在相应的源极和漏极注入之间延伸的相应的多个绝缘栅沟槽。
这增加了器件的电流处理能力，并降低了接通电阻。器件的设计是这样的，即它易于并联连接多个器件而毫不复杂，并且不占用太多的硅区域。
在优选配置中，源极注入包括较高掺杂源区和在较高掺杂源区和本体之间的较低掺杂源极漂移区；漏极注入包括较高掺杂漏区和在较高掺杂漏区和本体之间的较低掺杂漏极漂移区；绝缘栅沟槽包括在中心区的任一侧上纵向延伸的电位极板区，该电位极板区分别邻近源极和漏极漂移区，并且该中心区邻近本体；以及栅极电介质侧壁的厚度在绝缘栅的电位极板区中比中心区大。
发明者由此已认识到，如何把降低的表面电场(RESURF)原理应用到双向器件上。电位极板区起作用以保证获得RESURF效果，并且该配置中的器件因此称为RESURF器件。当该器件关断时，邻近电位极板的漂移区耗尽，并由此沿漂移区相对均匀地降低电压。与其中省去电位极板的器件相比，源极和漏极之间的总击穿电压可由此改善。
该器件可设置在第一导电类型的导电衬底上。该衬底可接地以使本体接地。
本体可外延生长或注入在衬底的顶部上。
可设置接触以接触本体。在其中本体生长在导电衬底上的实施例中，这可以是后接触。
在替换实施例中，可使用绝缘衬底，例如绝缘半导体衬底、蓝宝石或将被公知的其它绝缘衬底。在这种情况下，导电掩埋层优选设置在本体之下和衬底之上以接触本体。
附图说明
为了更好地理解本发明，现在将参考附图来描述现有技术结构和本发明的实施例，其中：
图1示出了现有技术的ACCUFET结构；
图2示出了根据本发明第一实施例的结构的侧截面图；
图3示出了图2的结构的顶视图；
图4示出了图2和3所示的多个结构的阵列；
图5示出了根据本发明第二实施例的结构的侧截面图；
图6示出了对图5的器件所测量的接通电阻值；
图7示出了根据本发明第三实施例的结构的侧截面图；以及
图8示出了图7的结构的顶视图。
这些图是示意性的并且未按比例绘制。在不同的图中，相同的参考数字用于相同的或类似的特征。
具体实施方式
图2和3示出了根据本发明的半导体器件的第一实施例。p+衬底2具有p型本体4，在其上限定第一主表面16。单个单元18具有类似的源极和漏极注入22、24，其在第一主表面18处设置在p型本体4中相互隔开，在它们之间留有沟道区40。每一个源极和漏极注入都是双掺杂结构，即双扩散结构，具有在第一主表面18处的深度为0.2μm(在该实例中)的相对浅的n+接触区26、28，和从n+接触区延伸离开第一主表面18进入衬底的n-低掺杂区30、32。注意，该结构是双向对称结构，因此术语源极和漏极仅仅与常规的命名方式相符合，并没有暗示它们之间的任何差别。
绝缘沟槽42穿过沟道40从源极22延伸到漏极注入24。该沟槽具有侧壁44、端壁46和底部48、所有的栅极电介质，并填充有导电的多晶硅栅50。该沟槽设置成从n+源极接触区26内延伸到n+漏极接触区28，因此n+接触区26、28和较低掺杂区30、32沿沟槽的两个侧壁44延伸。
在替换配置中，多晶硅可用金属或金属互化物来代替。
外延层h的厚度优选为相当厚，即比沟道区厚，以避免在接触区26、28、较低掺杂区30、32、层4和衬底2的n+-n- -p--p+二极管处的接触1和2的过早击穿。
导电栅电极54设置成跨越晶体管横向延伸，与栅极50接触并借助如图2所示的绝缘体52与沟道40中的本体4绝缘。该绝缘体可例如为氧化物。源极接触电极56和漏极接触电极58分别连接到源极和漏极22、24。后接触14被设置以通过导电衬底2连接到本体层4。在使用中，该接触可接地。该接触的电位决定了阈值电压。如果该接触连接到正电压，那么它将增加总的阈值电压。
图2和3示出了单个单元18，虽然实际上多个单元18将跨越衬底横向隔开设置，以改善电流处理并降低接通电阻。这在图4中示出，其示出了一种构造，其中单元18并排设置，并且横向延伸的栅电极54并联连接到所有栅极上，以及横向延伸的源电极56和漏电极58同样横向延伸以分别并联连接源极和漏极。
单个单元的设计使它易于以这种方式并联连接单元18。源极栅极和漏电极可仅仅横向延伸以并联连接到横向设置的单元上。
技术人员将知道制造根据本发明的半导体器件的许多方法，并且不存在任何特定的限制。例如，p本体层4可外延地生长在衬底2上，或可通过注入到衬底2的第一主表面18中来形成。实际上，器件仅使用相对标准的工艺这一事实具有特别的好处。使用浅n+注入避免了可能发生在注入深n+注入过程中的任何困难，其或许被另外需要以使电子流动均匀，并避免太多的电流流经器件顶部而在沟槽中是不足的。
在本发明的该实施例中，使用较低掺杂的源区和漏区来增强穿过本体的整个深度的电流。较低掺杂意味着更容易把这些注入到相当大的深度，并获得更高的击穿电压。
在使用中，源极、栅极和漏极接触按照需要来连接，并且后接触14优选接地。由于p型沟道40的缘故该结构通常关断，因此不导通，除非在栅电极54上施加电压。正栅极电压允许电子如箭头58所指示的那样从源极22流动到漏极24，假设源极比漏极更负。该器件是双向的，因此它同样有可能控制电子沿相反方向流动。
与ACCUFET相比，该结构的优点在于鉴于p型本体，不限定源区和漏区的掺杂。另外，电流不流过衬底2，因此衬底电阻并不是一个因素。
在替换实施例中，适合于较低电压的应用，较低掺杂区30、32被省去，如图5所示。在这种情况下，p本体4和衬底2是短路的，并且接地。
图6示出了图5所示的器件的一些测量的接通电阻值。对于10V栅极电压下获得10mΩ.mm2的最小接通电阻。注意此处对沟槽长度具有一些依赖性。
图7和8分别用侧截面图和顶视图示出了本发明的第三实施例。
在该配置中，p-层4设置在p+衬底2上。多个横向隔开的单元18每一个跨越由p-层的顶部所形成的半导体器件的第一主表面16纵向延伸。
每个单元包括中心p型本体40。在本体40的一端是由n+掺杂源极接触区26和在源极接触区26和本体40之间的n掺杂源极漂移区30所构成的源极注入。在本体40的另一端是由n+掺杂漏极接触区28和在漏极接触区28和本体40之间的n型漏极漂移区32所构成的漏极注入。因此，当该单元导通时，电流穿过源极漂移区30、本体40和漏极漂移区32，从源极接触区26流到漏极接触区26。该器件是双向的，因此电流也可沿相反方向流动。
栅极沟槽42和单元18横向交替。该栅极沟槽包括中心区62和从中心区60的每一端纵向延伸的电位极板区60。电位极板区60的侧壁64的栅极电介质44的厚度大于中心区的侧壁66的厚度。
中心区62与本体40邻接，电位极板区60与源极和漏极漂移区26、28邻接，不过电位极板和中心区之间的边界不需要与源区和漂移区之间的边界精确地对准。
栅极连接件54横向延伸连接到栅极32，借助绝缘体52与本体区40绝缘，其中栅极连接件54在本体区40上穿过。源极连接件和漏极连接件56、58同样横向延伸以分别连接到源极接触26和漏极接触28。为了清楚起见，这些仅在图7中示出，而在图8中省略。
在该配置中，沟槽与本体40一样深。然而，优选地，沟槽不如本体40深，以避免在低阈值电压下沟槽下面的寄生电流。
在使用中，当器件关断时，漂移区26、28耗尽，并且漂移区的长度l决定了击穿电压。选择p型层4的厚度h以便足够大，以避免在由源极和漏极注入以及p+衬底2所构成的垂直p-n二极管中的击穿。由此，击穿电压会增加。
当正电压施加到栅极上时，器件导通，并且电子或者从源极到漏极，或者从漏极到源极穿过单元。通过使用RESURF，对于相同的源极漏极击穿电压，源极和漏极漂移区30、32中的掺杂可高于在不使用RESURF的情况。该较高的掺杂结果产生较低的接通电阻。
正如在其它实施例中那样，该配置的关键好处在于该器件是双向的。
在替换的RESURF配置中，漂移区26、28中的掺杂例如通过提供具有从本体40向外增大的掺杂的线性渐变掺杂轮廓而渐变。
在另外的替换中，电位极板60不连接到栅极32，但提供与电位极板的单独连接。在该配置中，另外的电介质层设置在电位极板和栅极32之间。
从本公开中可以看出，对本领域的技术人员来说，其它的变化和修改是显而易见的。这些变化和修改可包括在半导体器件的设计、制造和使用中早已已知的，并且除了或代替此处所描述的特征还可使用的相当的和其它的特征。虽然已经在对一些特征的特定组合的应用中列出了权利要求，但是应当理解，本公开的范围还包括此处明确地或隐含地公开的任何新型特征或任何新型的特征组合，或者其综合，而不论它是否和本发明一样减少了任何或所有的相同的技术问题。因此申请者通告，在本申请或由其衍生的任何其它申请的申请期间，对任何这些特征和/或这些特征的组合可列出新的权利要求。
例如，本发明可通过反型所用的导电类型用p-MOS代替n-MOS来实施。漂移区中的掺杂可具有与本体相同的导电类型来代替相反的类型。本发明可用于绝缘体上硅(SOI)器件中，而代替导电半导体衬底上硅；衬底2可用掩埋层来代替。
另外，第一主表面上的单元配置可按照需要来改变。

Claims (8)

1.一种具有相对的第一和第二主表面的半导体器件，包括：
衬底(2)；
衬底(2)上第一导电类型的本体区(4)，所述本体区(4)沿着半导体器件的第一主表面(16)延伸；
至少一个单元(18)，其具有从第一主表面延伸进入本体区(4)的纵向隔开的源极和漏极掺杂区(22、24)，该源极和漏极掺杂区(22、24)借助部分本体区(4)与衬底(2)隔开；以及
至少一个绝缘栅沟槽(42)，其穿过本体区(4)从源极掺杂区(22)纵向延伸到漏极掺杂区(24)，该绝缘栅沟槽(42)包括沿沟槽的底部和端壁以及侧壁，通过栅极电介质(44、46、48、64、66)来与源极和漏极掺杂区(22、24)以及本体区(40)绝缘的栅导体(50)，
其中本体区(4)另外包括沟道部分(40)，所述沟道部分(40)沿着第一主表面(16)在沟槽的侧壁处纵向地在源极和漏级掺杂区(22，24)之间延伸，
其中该源极和漏极掺杂区沿沟槽的部分侧壁延伸，从而栅极上的电压能够控制沿着源极和漏级掺杂区之间的沟道部分(40)的纵向导通，
其中该源极和漏极掺杂区(22、24)包括垂直延伸进入本体区直到不超过沟槽深度35％的深度的第一主表面处的与第一导电类型相反的第二导电类型的导电浅接触区(26、28)；
其中每一个源极和漏极掺杂区(22、24)另外包括掺杂低于浅接触区的较低掺杂区(30、32)；
源极掺杂区(22)包括较高浅源极接触区(26)和在较高浅源极接触区(26)和本体区(4)之间的较低掺杂源极漂移区(30)；
漏极掺杂区(24)包括较高浅漏极接触区(28)和在较高浅漏极接触区(28)和本体区(4)之间的较低掺杂漏极漂移区(32)；并且
其中绝缘栅沟槽(42)包括在中心区(62)的任一侧上纵向延伸的电位极板区(60)，该电位极板区(60)分别邻近较低掺杂源极和漏极漂移区，并且该中心区(62)邻近本体区。
2.根据权利要求1的半导体器件，其中：
导电浅接触区包括较高浅源极接触区和较高浅漏级接触区，所述较低掺杂区包括较低掺杂源极漂移区和较低掺杂漏级漂移区；并且
绝缘栅沟槽(42)的栅极电介质侧壁(64、66)的厚度在绝缘栅沟槽(42)的电位极板区(60)中比中心区(62)大。
3.根据权利要求1至2之一的半导体器件，包括跨越第一主表面横向隔开的多个单元(18)。
4.根据权利要求3的半导体器件，其中绝缘栅沟槽(42)跨越第一主表面横向地与单元(18)交替。
5.根据权利要求3的半导体器件，其中每个单元(18)具有横向处于该单元界限内的绝缘栅沟槽(42)。
6.根据权利要求2的半导体器件，其中掺杂低于导电浅接触区的较低掺杂区(30、32)在导电浅接触区(26、28)下方垂直延伸到沟槽深度的至少80％的深度。
7.根据权利要求1的半导体器件，其中该衬底(2)是第一导电类型的导电衬底(2)。
8.根据权利要求1的半导体器件，另外包括绝缘衬底和该绝缘衬底之上该本体区(4)之下的第一导电类型的掩埋层。
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