CN1802744A - 集成电路的电交互连接结构及其制造方法 - Google Patents

集成电路的电交互连接结构及其制造方法 Download PDF

Info

Publication number
CN1802744A
CN1802744A CNA2004800159031A CN200480015903A CN1802744A CN 1802744 A CN1802744 A CN 1802744A CN A2004800159031 A CNA2004800159031 A CN A2004800159031A CN 200480015903 A CN200480015903 A CN 200480015903A CN 1802744 A CN1802744 A CN 1802744A
Authority
CN
China
Prior art keywords
top layer
copper
welding
electric wire
cupric oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800159031A
Other languages
English (en)
Inventor
戴维托马斯·贝亚特森
霍斯特·克劳贝格
肯尼思凯尔·杜里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kulicke and Soffa Investments Inc
Original Assignee
Kulicke and Soffa Investments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kulicke and Soffa Investments Inc filed Critical Kulicke and Soffa Investments Inc
Publication of CN1802744A publication Critical patent/CN1802744A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明揭示了采用含氮化铜的压焊表层的交互连接结构和方法。所述交互连接结构包括一个含氮化铜的压焊表层，有效防止下层导电材料的氧化和/或其他不希望的侵蚀，同时为高导电压焊打基础。所述氮化铜压焊表层提供了相对非导电、抗氧化的压焊表层，且在压焊之前或同时，容易转化成一导电层。

Description

集成电路的电交互连接结构及其制造方法
技术领域
本发明涉及集成电路模块的交互连接结构和制作该交互连接结构的方法，具体地说，涉及用于电性连接两个或更多电子元件的铜材料的交互连接结构。
背景技术
交互连接技术是包含半导体装置的电子元件制作中的一个重要方面。例如，在芯片焊接中，芯片的背面机械地附着于适当的介质，如陶瓷衬底，金属引线架或者球栅阵列(BGA)。用于芯片配线的较高层通常包括电连接的压焊盘(bond pad)，通过必要的连接连到下层电路。芯片通常具有防护套(PO)层，一般作为钝化，防护套层上具有通向压焊盘的孔。芯片电路侧的压焊盘通过电线或者其它电导物电性连接模块的导线，使得该集成电路(IC)可应用。所使用的交互连接配置的类型可根据所述模块的预期特性进行各种变换。例如，细导线典型地用作交互连接的一部分，它们可超声焊接到压焊盘(有些时候在这里称为“导线焊接”)或者通过焊球结构，所述焊球直接连接在芯片的压焊盘和基层之间(如在倒装芯片处理中)。其他用于制造IC交互连接的惯用方法，例如连接压焊盘到引线架的引线，或者其他导体支撑装置的导线，通过使用导电粘合剂，包括有卷带式晶粒接合(TAB)，可控塌陷芯片连接(controlled collapse chip connection)(C4)或者焊接突起。
铝至今还常常作为用于形成交互连接元件中的材料，例如交互连接元件包括半导体电路的金属线迹，压焊盘和(应用于大间距)电线。然而，由于集成电路工业降低成本和IC装置尺寸，以提高这些装置输入/输出容量和速度的压力，使用铝的愿望近来受到了影响。该压力增加了半导体上更小线迹和更小间距互连的需要，这常常需要更细且某些时候来说更长的电线。结果是，铝及其合金的一些缺陷，例如相对电流的高阻抗，可靠性和电迁移，激发了要在IC电路中使用更可靠的和更高导电性金属的需要。半导体装置和支撑基底之间的小间距交互连接，例如引线架或球栅阵列(BGA)，通常使用细金线制作。金高昂的成本以及更高速和更细电线的压焊也产生了为小间距电线焊接寻求更高导电性和更低成本金属的需要。
为了解决这些问题，引起越来越多关注的金属就是铜。虽然铜具有比铝或金更低的阻抗，但应用于交互连接装置，会遇到一系列使用铝或金所不曾出现的问题。例如，铜衬垫的交互连接结构的形成通常需要在其连接到压焊盘前，暴露于周围空气和湿度中，且形成连接的过程中温度高达近200度。这样，由于金属表层会快速形成粘附的非导电的氧化物，即使在室温下也如此，就产生了一个重要的问题。这些氧化铜的出现通常阻碍了电线焊接或者焊球与裸露的铜表层的良好的连接。类似地，由于即使保存在相对低氧浓度和低湿度环境中铜线表层也会形成薄的氧化层，所以铜线的使用寿命通常很有限。该氧化铜层将在该交互连接的传导上产生不希望的负面效应。
如果在半导体上镀铜，一种针对上述问题所通常采用的方法是，在压焊盘上淀积一更强抗氧化性的金属薄层，以防止铜被氧化。典型地，该第二层金属镀层由金或铝构成，如5,785,236号美国专利所披露。典型的实现方式为，采用掩模(mask)将金属层汽相淀积到半导体晶元上。然而，该解决方案产生了一些自身的问题。例如，需要另一套光刻步骤来模制、掩模和蚀刻金属，从而形成能导线接合的压焊盘。这些额外的晶元制造步骤大大增加了装置的成本。另外，当铝或金与铜焊接，由其他金属制成的薄的中间阻挡层通常需要防止铜和金或铝之间的相互扩散。
例如，4,987,750号美国专利描述了使用氮化钛(TiN)、钨(W)、氮化钨(WN)、氮化锌(ZrN)、碳化钛(TiC)、碳化钨(WC)、钽(Ta)、氮化钽(TaN)，或者钨化钛(TiW)作为铜的阻挡层。然而，这类材料大多也形成非导电的氧化物，或者具有弱的导电或导热性，或者高热膨胀。
最近，有人提议采用诸如氧化硅或者氮化硅之类的瓷绝缘体的脆层，它具有对焊接来说适合的厚度而不需要助焊剂，且具有在球焊或楔焊(wedgebonding)过程中有足够的脆性而在焊接表层和需焊接电线之间获得金属间连接。上述方法在6,352,743号美国专利中被揭示，该专利已经转让给本发明的申请人。虽然该方法具有一些优点和期望的特性，但如果操作步骤没有精密控制的话，还是要出问题。例如，若陶瓷层脆性不够，会导致传导性的实质性下降，甚至在某些情况下，潜在地阻碍连接的构成。
对于铜引线架，用于焊接的端部通常包覆抗氧化金属，通常是银。这类方法的明显缺点是，增加了成本以及制造过程的复杂度和时间。对于焊球撞击，需要焊剂来去除回流过程中的氧化物。
相应地，需要一个交互连接结构，能简化高传导性焊接的构成。也需要一个具有抑制氧化物生成层的铜压焊盘，它具有良好的导电性、热传导性、低热膨胀性，以及形成该铜压焊盘的过程要简单。本发明符合这些需求，并提供了其它的优点。这将在下面的发明内容和具体
实施方式中讨论。
发明内容
本申请揭露了一种克服上述问题的解决方案，并且达到其他有益的和所需的效果。更为具体地，本发明涉及采用含氮化铜的焊接表层的交互连接结构和方法。申请人发现，包括含氮化铜的焊接表层的交互连接结构能非常有效防止其下面的导电材料的氧化和/或其他不想发生的侵蚀，同时对高传导焊接提供基础。另外，本申请简化了制造过程，和/或降低了制造过程的成本。这些优点，至少一部分，来自申请人的发现和认知，即氮化铜在这种结构中能提供相对绝缘、防侵蚀的焊接表层，并且可在焊接同时或者早于焊接步骤前容易地转化成导电层。根据本发明的方法的某些实施例，交互连接的焊接结构可以通过如下方式形成：提供具有相对绝缘、抗侵蚀的含Cu(N)的焊接表层的导电基材，在所述焊接表层区域形成导电压焊部；在该压焊部形成之前或者同时，在所述焊接表层分解足够量的Cu(N)以使含有Cu(N)的层的导电性实质增加，由此形成一相对导电的焊接表层。优选地，分解步骤引起的导电效果的变化，足以形成商业上可接受的电连接。
在本发明的优选实施例中，交互连接结构包括至少一个从包括铜压焊盘、铜线，铜引线架，铜接线柱(stud bumps)，以及两个或两个以上上述物品的组合中选出的交互连接元件。通常优化地，本发明的包括Cu(N)焊接表层的交互连接元件通过焊接步骤焊接到另一个交互连接元件，所述焊接步骤包括在压焊部区域施加能量，例如热、压力和/或超声能量，在电线焊接实施例中，优选为热、压力和超声能量。在其他应用中，用发自激光器的电离的气体(等离子体)或光可以用来提供分解Cu(N)层的能量。针对该目的，激光的一个特别应用是，用激光器将焊球熔化在带有氮化铜涂层的铜衬垫上，所述涂层在融化过程中会分解为铜。
这里所用的术语“非导电的”是相对于电导率而言的，意为，其导电率低于构成交互连接元件导电部分或者基层的材料的导电性。类似地，这里所用的术语耐侵蚀是相对于通常的抵抗侵蚀而言，特别是针对抗氧化，其耐侵蚀能力实际大于构成交互连接元件导电部分的金属，特别是铜或者铜合金的耐侵蚀能力。
Cu(N)的电导性远低于铜，铜是作为许多诸如压焊盘、电线以及引线架之类交互连接元件的优选导电材料的。由于其低导电性，熟知本领域的人员会很自然地避免在交互连接元件的焊接表层使用Cu(N)。然而，申请人已经认识到，Cu(N)也是相对不稳定的，尤其在作为表层频繁遭受暴露于焊接工序的条件下。这些焊接工序都包括某些形式能量的应用，例如热能、动能、辐射能、光子能或者两个或以上这些能量的组合。例如，为了充分增加含Cu(N)的层的导电性，足以分解Cu(N)的能量通常出现在热声波的或超声波电线焊接(包括球焊和楔焊)以及焊接凸起或者接线柱中，就如倒装芯片处理中所使用的。这样，在经常出现于许多焊接工序中的适当的条件下，含Cu(N)的层或者表面转化成相对高导电率的表层。可以相信，不一定需要受任何特别的操作原理的限定，这种转化是由Cu(N)分解成元素铜和氮而产生，后者氮作为气体从表层释放。
另外，可以相信，铜-氮混合物，即使仅包含少量的氮，也在降低电导性和增加耐侵蚀方面有效果。而且，该混合物还能容易地分解为铜和氮，从而在适当条件下，就在压焊部形成之前或者同时，能够转化成为高导电层。相应地，这里所用术语“Cu(N)”指的是基本由氮和铜组成的所有相态(phase)和化合物。因此，这里所用的符号“Cu(N)”表明，某些或所有氮与铜的结合(共价键或离子键)，例如Cu3N，但并非限于该化合物。因此，符号“Cu(N)”也涵盖了较少见的按照化学计量学(stoichiometry)的Cu4N以及其他有效化学计量和/或铜和氮的组合。
Cu(N)非导电的特性及其形成的方法存在另一优点，即不需要屏蔽而在半导体装置上形成Cu(N)。在一些实施例中，由于Cu(N)基本不导电，因而不需要屏蔽也不会在压焊盘之间形成短路，所以可在整个装置或装置大部分使用Cu(N)。在其他实施例中，可以通过转化现有的铜交互连接元件的表层为Cu(N)来形成Cu(N)。以这种方式，在诸如压焊盘之类的分离的铜交互连接元件之间就不形成Cu(N)。
附图说明
图1是根据本发明的一个实施例，在焊接步序之前的一块典型半导体芯片的一部分的顶视图。
图2是图1中半导体芯片的剖面图。
图3是包含图1中半导体芯片的集成电路模块的顶视图，该模块在根据本发明的某实施例的焊接步序后，与一电路基层电性连接。
图4是例1中取样的元素组成的俄歇(Auger)深度曲线图。该深度指示是基于二氧化硅的假定溅射速率。
图5是例2中取样的元素组成的俄歇深度曲线图。该深度指示是基于二氧化硅的假定溅射速率。
图6是例3中取样的元素组成的俄歇深度曲线图。该深度指示是基于二氧化硅的假定溅射速率。
具体实施方式
在下面的描述中，参考了本发明的各种详细的实施方式。这些实施方式的描述足够详尽，以达到熟悉本领域的人员可以实现本发明，另外，应该理解，还可以采用其他实施方式，在不脱离本发明的情况下，可以进行结构的、电的和方法的变化以及等效替换。因此，下述具体实施例并非用以限定本发明，本发明的保护范围应当以权利要求书为准。
本发明将与现在或将来作为半导体器件的一部分使用的任何类型的交互式结构或元件一并使用，例如，芯片或晶片(die)，包括含有这类器件的晶元。本发明的创新的交互连接结构由任何两个或更多相互焊接的交互连接元件构成。因而这些元件可包括但不限于导线，引线架和/或引线架的部分，压焊盘和/或压焊盘的部分，接线柱，芯片内部节点和其他任何在焊接过程中披露的连接。在较佳实施例中，本发明所创新的交互连接结构和方法用于一个集成电路模块的形成，该模块包含一芯片，一引线架和连接所述芯片和引线架的导线，这将在下面结合附图进行描述。在优选的实施例中，交互连接结构包括一位于芯片上的铜压焊盘，一个铜引线架(或者一个引线架的铜的焊接部分)和相互焊接与电性连接的铜电线，其中，在焊接交互连接元件中的至少一个之前，得到一个含有Cu(N)的焊接层。
这里所用的技术术语“芯片”和“晶片”可替换使用，都指半导体材料的较小的片，该小片上嵌有集成电路或分离的电子电路元件，如晶体管、电容、二极管等。这些电子电路元件或者集成电路也可以包括光电装置，例如发光二极管，激光器二极管等等。换句话说，芯片或晶片或其一部分可以是微机电***(MEMS)。
这里所用的技术术语“交互连接”和“交互连接结构”可互换使用，都指至少两个相互焊接的高传导元件，所述传导元件传递电信号到芯片或晶片的不同部分，和/或在芯片或晶片之间传递电信号。这类高传导元件有时在此指“交互连接元件”。让本领域技术人员欣慰的是，本发明并非限于交互连接结构的具体形状，而可以与任何交互连接元件的组合同时使用，例如导线，引线架，压焊盘，接线柱，卷带式晶粒接合(TAB)，可控塌陷芯片连接(C4)者焊接突起，导电胶等等。虽然许多交互连接结构适于和本发明一起使用，但典型的和优选的是由如下步骤形成的交互连接结构：提供至少一个交互连接元件，该结构具有一个基本不导电和耐腐蚀的包含Cu(N)的焊接表层；将不导电的焊接表层转化成导电的焊接表层，并将转化后的表层焊接到第二交互连接元件。在较优选的实施例中，所述转化步骤和焊接步骤基本同时进行。换句话说，焊接步骤是在可有效分解焊接层中的Cu(N)为可导电的铜的条件下实施的。本领域的技术人员会赞赏这种具有实质的和较满意的方法的优点。更为具体地，所述优选方法提供交互连接元件，其同时具有：(1)由于具备耐腐蚀、不导电的焊接表层而有相对较长的使用寿命；以及(2)能容易地和顺利地用于交互连接结构中，而不会降低交互连接的电导率。而且，由于本发明的表层材料不导电，它可就地应用到位于芯片上的压焊盘上，而不必担心引起芯片上压焊盘之间的短路。在本发明的一个较佳实施例中，所述交互连接结构上所存在的铜表层被化学转化成Cu(N)。这样，本发明的表层材料可以直接应用，而不需要屏蔽或者接下来的蚀刻步骤。这里所用的技术术语“压焊盘”包括所有合适的可进行焊接的终端结构，可以是既凸出又凹陷的压焊盘，以及平坦的，凹陷的或者凸起的压焊盘等等。
考虑这里所包含的方法，可以想到，焊接条件的多种组合能用于分解Cu(N)，所有这些条件落在本发明的范围之内。然而，可以预期，在特定优选实施例中，焊接步骤将包括将含有Cu(N)的表层暴露于至少150度的温度中。更为具体地，为了基于BGA交互连接的焊接，将含Cu(N)的表层暴露于大约150度至180度之间的温度中更好。为了焊接基于金属引线架的交互连接，最好将含有Cu(N)的表层暴露于大约180度到240度之间的温度中，更好的是190度到230度之间。
现在参阅附图，相同的元件对应图中相同的标记，本发明的优选方法和装置将结合图1-3进行描述。图1显示了普通结构的半导体芯片10，包括半导体基层11和形成于基层11上的集成电路12。这里所用的技术术语“半导体基层”包括任何基于半导体的支持结构或者芯片、集成电路或印刷电路板的基材。术语半导体基层理解为包括绝缘硅、掺杂质的硅或纯硅，以及其他半导体结构。另外，当涉及一种半导体基层，先前的方法步骤可以用于在基层半导体结构或者基础内或之上形成区域或者交联。图2中显示的半导体基层11为简便而显示为一个单层，但实际上它包括一个基础基层和形成集成电路12所需的各种材料层。终端触点13电性连接到内部的集成电路12。为了简化，图1仅显示了两个终端触点。显而易见，在许多实际应用中，可以有更多的终端触点连接到集成电路12。
在典型的集成电路制造过程中，芯片10与大量的其他芯片一块组装到晶元上。随后，晶元上的每个芯片10通过锯切或者其他合适的方法可成为独立体。正如将要进一步描述的那样，含有集成电路12的芯片10的上层包括一个以具有压焊盘20B的上层导电层20的形式的交互连接元件。在较佳实施例中，层20是金属的，最好是铜的，本发明的Cu(N)层就组合入所述压焊盘的一个表面中。然而，本发明还包括使用其他类型金属作为交互连接结构的一个或多个元件的基材。例如，若某一具体实施例采用具有本发明的焊接表层的铜线，该电线所焊接到的压焊盘的基层金属可以是铜，也可以不是铜。另外，可以想见，在某一实施例中，本发明的Cu(N)层可以形成位于非铜的基层金属上的焊接表层。所有这些实施例都在本发明的保护范围之内。区域20A的表层是铜压焊盘的焊接表层，另一个交互连接元件，诸如导线，优选的是铜的或者金的导线，更优选的是铜导线，焊接到上述区域。
图3显示了半导体芯片10和电路基层30之间的交互连接。电路基层30可以是连接芯片10的引线架，球珊阵列，芯片载体或者其他支持结构，产生一集成电路模块32。一个导电交互连接元件，如表层电路线路，或者如图3中显示的引线架，一套内部引线35包含在电路基层30上。封装过程中，电连接件40形成于终端连接13的压焊盘20B部分和电路基层的内部引线35之间。虽然电交互连接元件40可以根据本发明在较宽的范围内制成柱体(bump)、电线、导电胶，和/或胶带(tape)，通常优选的，该元件40由电线构成，最好是铜线，该电线球焊或者楔焊到压焊盘20B上。
根据本发明优选方法，一个或多个交互连接元件，即压焊盘20B，内部导线35和电线接头40，在各自的焊接点具有一个焊接表层。在某些实施例中，所有上述三类元件都包括本发明的焊接表层。现在再次参阅图2，优选的压焊盘20B包括在焊接区域覆盖在导电的铜上的焊接表层20A。导电的铜层20可以具有任何合适的厚度，例如大约0.1微米到5微米。
根据本文所教导的内容，焊接表层20A可以由多种专门技术制成。所有这些技术都在本发明的保护范围之内，所提供的焊接表层有效防止了下面的导电层退化，且在压焊部形成后，基本不削弱交互连接结构的导电性。在优选实施例中，本发明的焊接表层包括足够的Cu(N)以形成一表层，其平均Cu∶N摩尔比不超过15∶1，优选地为大约10∶1到1∶1，更为优选地从大约8∶1到2∶1。在某些实施例中，本发明的焊接表层优选地包括至少大约5％的氮(以氮原子含量计算)，更好的是包括至少8％。在这样的实施例中，通常优选地，焊接表层中的氧浓度不超过大约15％(以氧原子含量计算)。在某些优选实施例中，焊接层基本上由Cu3N构成。在这方面，需要提示的是，该Cu(N)层可包括一个或多个不会负面影响到本发明操作的杂质。正如举例所述，基本由Cu(N)构成的该层包括没有负面影响到本发明操作的作为杂质的碳和氧。还可以预期，在某些实施例中，适量的存在一个或多个氧化铜，不会造成毒化效应。另外，本发明的焊接表层的厚度可在大范围内变动并根据具体应用而变化。在某些优选实施例中，焊接表层具有至少大约20埃的厚度。更具体地，为大约25埃至大约3000埃之间，更佳地，为大约50埃到500埃之间。对涂有氮化铜的电线，优选的焊接表层厚度为至少30埃，更具体地，为大约100埃至大约20000埃之间，最好是大约200埃至大约10000埃之间。在较佳实施例中，一个Cu(N)表层用在一根焊接电线上，该电线上的Cu(N)将在焊球形成过程中分解/转化还原为铜和氮，特别是在使用所谓电子灭火EFO(electric flame off)的放电的部分过程中。这样，就在形成压焊部之前，Cu(N)从焊接表层去除。在优选实施例中，EFO在惰性气体或者还原气体环境中进行，例如氮气、氩气、氦气或者合成气体。
可以预期，在某些应用中，通过直接对导电材料的底部基层涂敷适当的含Cu(N)材料的层，可以在如图中显示的层20的导电层上或者如铜导线之类的金属导线上形成Cu(N)焊接表层。这些技术包括但不限于：在氮气中铜反应溅射或铜蒸发而在导电材料上淀积一含有Cu(N)的层；化学气相淀积；以及电化学技术。铜的溅射或者蒸发可以采用任何本领域熟知的方法进行，包括但不限于直流或者交流放电，例如射频或者微波技术，或者通过直接加热、电加热、空心阴极放电或者电子或离子轰击使铜蒸发。溅射或者蒸发可在本领域人员所熟知的任何淀积设备中进行，包括标准“高”真空技术和低真空技术，例如淀积过程中的压力可从几毫托到基本一个大气压。M.A.Lieberman和A.J.Lichtenberg所著的“等离子体放电和材料处理的原理”(John Wiley和Sons，纽约，1994)描述了合适的技术，特别是第十六章，在这里参考引用，此外，还可参考如下的美国专利：5,356,673；5,571,332；5,725,672和4,788,082。其他可选择的方法包括在等离子体中分解挥发性的铜的金属有机化合物。由于这些步骤不需要底层的导电元件的铜的存在，这些技术特别适合与主要由非铜构成的交互连接元件一起使用。当然这些技术也适合与主要由铜构成的导电层一起使用。可以理解，这里使用的术语“铜”不仅包括基本铜，还包括铜与其他痕量金属(trace metals)，或者半导体领域所公知的只要能导电的与其他金属的各种合金化合物。
对于其他导电层主要为铜的实施例，Cu(N)焊接表层可以通过使用来自导电层的铜形成。下面对能单独或者组合使用以形成各层的方法步骤非限定的列示如下：通过用气态氨对基材进行热处理，将铜表层转化为Cu(N)，可选择地，但最好是在升温时伴随用氧气同时或预处理该表层；用氨或氮气对铜基层进行等离子处理，可选择地，但最好伴随用氧气同时或预处理该表层；通过标准离子注入或者等离子浸没离子注入，将氮注入铜基层的表层内。依照本发明，用氮气等离子体转化铜或氧化铜表面，这可通过本文所包括的任何本领域已知的方法进行。例如，氮气等离子体可通过交流(AC)或直流(DC)电产生。通常，由于所产生的氮化铜的非导电或导电性差的特性，交流电处理更合适。在某些情况，使用直流偏压结合交流电场，会有好处。交流电场的频率可以是任何用于等离子处理领域所熟知的，包括射频和微波频率。形成等离子体的环境压力可从仅几毫托到接近一个大气压。在一些实施例中，通过在大约1托和大约1000托之间的相对高压情况下进行直流或交流放电来形成等离子体，优选地是在大约1托和大约200托之间，然后扩展到装置的低压区域，在此撞击基层。如本领域技术人员所知，氮气或氨气仅是形成等离子体的气体的一种。在某些应用中，特别对于在高压情况下形成的等离子体，氮气或氨气可在另一气体中稀释，如氦或氩，以便等离子体的形成。对于铜压焊盘和铜引线架的焊接，较优选的焊接成形的方法包括用氧热处理和同时或随后的氨处理。
申请人惊奇地发现，用氧气对表层进行预处理，优选地是氧化和热处理相结合，实际产生的效果比用例如氨气这样单独的氮处理要好。目前获得这样较好结果的原因还不清楚。中间的氧化铜的形成也可以用本领域所熟知的其他技术。这样的替换技术包括用除了氧气外的氧化化合物进行处理，例如过氧化氢，或者电化学技术。
                       实例
例1
图2中显示的普通类型的硅芯片，包括一个基层和一个导电铜层。导电铜层是10000埃，在芯片上形成压焊盘的基础。通过用95％摩尔百分比的氮气和5％摩尔百分比的氢气组成的合成气体对焊接表层进行第一次预处理，在压焊盘上形成一保护层。所述表层置于大约400度的第一预处理气体中大约9小时以形成焊接表层，基本避免了铜的氧化。然后将焊接表层进行第二预处理步骤，即置入大约200度的基本由氧气构成的合成气体中大约5分钟，形成一具有容易控制厚度的氧化铜层。然后氧化层用无水氨在大约275度下处理5小时，形成一基本非导电的大约200埃厚度的表层。表层的颜色从铜的特有色改变成青绿色。按照图4中的俄歇光谱分析，该层是铜和氮化铜的混合物，带有少量氧和碳。该层中Cu∶N的摩尔比大约为85∶10。因此形成的焊接表层基本上防止下面的铜氧化，具有的导电性弱于压焊盘的下层铜基层的导电性。铜电线在下述的条件下焊接到压焊盘后，交互连接的导电性足够提供对半导体装置的良好电性连接。
例2
通过在大约4毫托氮气的气氛下，采用铜靶射频溅射1微米均匀厚度的铜的方式，在四分之一的八英寸硅片上淀积氮化铜。在大约每秒33埃的溅射率下，形成一个200埃的淀积。在此过程中，晶元被加热到100度。图5显示了元素组成的俄歇深度曲线图。该俄歇数据清晰地指示出一大约200埃厚度的氮化铜涂层。在试验之前，硅和氧很可能是存在于晶元上的杂质。
例3
氮化铜的淀积采用下面的真空淀积技术。大约1个大气压的氦气穿过真空容器内的涂有铜的硅片上方大约10厘米的喷嘴。基层加热到大约120度。在阳极和铜中空阴极之间的放电在喷嘴内侧溅射目标，将铜原子和离子引入氦气中。在喷嘴下方引入氮气，产生大约30毫托的氮气环境压力。铜原子或离子与氮气的交互作用使得在表层淀积氮化铜。图6显示了在本试验中形成的俄歇元素深度曲线。该深度曲线证明了这样的构造，即在涂敷铜的晶元上形成具有大约50埃氮化铜的表层。看上去有很厚的氧化物是在淀积开始之前存在表面的氧化铜，这是因为在本试验中没有设法去除表层氧化物。
例4
具有大约300埃厚度的氮化铜层如下所述形成于直径为1毫英寸的铜线上。该铜线通过一长度为3厘米，内部直径为1.5毫英寸的小管，从外部线圈水平进入真空室。管子的中间设有一直角连接，通向去除进入真空室的其它气体的真空泵。铜线的引出也通过一个类似的管子，该管子设在真空室的另一边，也连接小的真空泵。在真空室内，铜线从距离大约4厘米处具有一3毫米开口的喷嘴下通过。一金属板通过两个间隔5毫米的平坦岛状物固定在位于距其大约1毫米高度处的喷嘴的上方。该真空室通过大型真空泵排空到大约500毫托。氮气从一个小腔室穿流过该喷嘴从该喷嘴溯流而上，喷嘴处的压力大约为5托。通过对位于从喷嘴溯流而上的该小腔室内侧的两极提供大约100瓦的射频交流电，在自喷嘴溯流而上的氮气中产生等离子体。然后氮气等离子体从喷嘴导出，轰击于铜线上。控制铜线的馈送率使其产生大约300埃厚度的氮化铜层。
例5
具有大约500埃厚度的氮化铜将如下所述形成于直径为1毫英寸的铜线上。该铜线通过一长度为3厘米，内部直径为1.5毫英寸的小管，从外部线圈水平进入真空室。管子的中间设有一直角连接，通向真空泵，去除另外进入真空室的气体。铜线的引出也通过一个类似的管子，该管子设在真空室的另一边，也连接小的真空泵。在真空室内，铜线从距离大约4厘米处具有一3毫米开口的喷嘴下通过。一金属板通过两个间隔5毫米的平坦岛状物固定在位于距其大约1毫米高度处的喷嘴的上方。该真空室通过大型真空泵排空到大约500毫托。从该喷嘴向上的小腔室装有两个电极，射频交流电施加于该电极上以在腔室中产生等离子体。在喷嘴下方该铜线的第一段通道内，5托压力的氧气导入小腔室内，采用大约100瓦射频电流在两极间撞击等离子体。在喷嘴下方铜线的馈送速率控制在氧化掉铜线外部500埃厚度的铜。一旦氧化铜层产生于铜线的所有线轴上，从喷嘴上溯的穿过小腔室的气体控制为5托氮气，且等离子体再次在该气体中产生。然后铜线再次馈入喷嘴下以将氧化铜转化为氮化铜。调整馈送率使其转化75％以上氧化铜到氮化铜。

Claims (38)

1、一种在半导体装置或模块中形成交互连接结构的方法，包括如下步骤：
1-1从包括压焊盘、电线，引线架，球珊阵列，接线柱，卷带式晶粒接合，可控塌陷芯片连接或焊接突起，以及两个以上上述物品的组合的组中选出至少一个金属交互连接元件；
1-2在至少一个所述交互连接元件上形成一包含Cu(N)的焊接表层，其有效量足以抑制下面金属层的氧化；
1-3在所述表层位置形成导电压焊；以及
1-4在形成压焊步骤之前或者同步，分解所述Cu(N)来充分增加该表层的传导性。
2、如权利要求1所述的方法，其特征在于，所述交互连接结构包括一个半导体模块，该模块具有一含至少一个铜压焊盘的芯片；所述芯片的底层；以及含有Cu(N)的表层。
3、如权利要求2所述的方法，其特征在于，所述压焊形成步骤包括超声波焊接或者热声波焊接。
4、如权利要求1所述的方法，其特征在于，所述步骤1-1包括提供至少一个铜制金属交互连接元件；所述步骤1-2包括将所述铜交互连接元件的表层暴露在氧气中，至少氧化所述表层的一部分。
5、如权利要求4所述的方法，其特征在于，所述步骤1-2还包括在氧化步骤之前或同时，对所述表层进行加热的步骤。
6、如权利要求5所述的方法，其特征在于，所述步骤1-2还包括将所述表层置于氮气等离子体中的步骤。
7、如权利要求5所述的方法，其特征在于，所述步骤1-2还包括将所述表层置于氨中的步骤。
8、如权利要求6或7所述的方法，其特征在于，所述步骤1-2还包括在将所述表层置于氮离子中的步骤之前或同时，将其加热。
9、如权利要求6或7所述的方法，其特征在于，所述置于氮离子中的步骤还包括将所述表层置于无水氨中。
10、一种用于形成具有铜交互连接的集成电路模块的装置，包括具有一个含有Cu(N)的焊接表层的至少一个交互连接元件。
11、一种用于形成一个集成电路模块的引线架，包括一个含有Cu(N)的焊接表层。
12、一种用于形成一个集成电路模块的电线，包括一个含有Cu(N)的焊接表层。
13、如权利要求12所述的电线，其特征在于，所述Cu(N)由含氮气和铜的气源淀积形成。
14、如权利要求13所述的电线，其特征在于，所述气源中的铜通过从一个铜靶进行电溅射方法产生。
15、如权利要求13所述的电线，其特征在于，所述气源中的铜通过直接加热或者暴露在热灯丝中蒸发产生。
16、如权利要求12所述的电线，其特征在于，所述Cu(N)通过将铜的表层暴露在氮气等离子体中产生。
17、如权利要求12所述的电线，其特征在于，所述Cu(N)的产生方式为，形成包含氧化铜的表层，然后将至少一部分氧化铜转化为Cu(N)。
18、如权利要求17所述的电线，其特征在于，所述氧化铜形成步骤包括将含有铜的表层置于氧等离子体中。
19、如权利要求17所述的电线，其特征在于，所述氧化铜形成步骤包括将含有铜的表层置于热的氧气中。
20、如权利要求17所述的电线，其特征在于，所述氧化铜形成步骤包括将含有铜的表层置于氧化剂中。
21、如权利要求17所述的电线，其特征在于，所述氧化铜形成步骤包括用电化学法氧化含有铜的表层。
22、如权利要求17所述的电线，其特征在于，所述转化包括将氧化铜置于氮离子等离子体中。
23、如权利要求17所述的电线，其特征在于，所述转化包括将氧化铜置于气态氨中。
24、一种在半导体装置中形成交互连接结构的方法，包括如下步骤：
提供至少一个导电的交互连接元件；
在上述交互连接元件上形成含Cu(N)的焊接表层；以及
在上述焊接表层的位置形成导电压焊。
25、如权利要求24所述的方法，其特征在于，所述导电的交互连接元件是金属电线。
26、如权利要求25所述的方法，其特征在于，所述金属电线包括铜线。
27、如权利要求25或26所述的方法，其特征在于，所述焊接表层形成步骤包括将所述电线表层部分置于含有氮和铜的气体中。
28、如权利要求27所述的方法，其特征在于，所述焊接表层形成步骤包括将铜从一个铜靶溅射到所述电线的至少一个表层部分上。
29、如权利要求27所述的方法，其特征在于，所述焊接表层形成步骤包括通过直接加热和/或者暴露在热灯丝中蒸发铜。
30、如权利要求27所述的方法，其特征在于，所述焊接表层形成步骤包括将所述电线的至少一个表层部分置于氮气等离子体中。
31、如权利要求25或26所述的方法，其特征在于，所述焊接表层形成步骤包括：在所述电线上形成包含氧化铜的表层，然后将至少一部分氧化铜转化成氮化铜。
32、如权利要求31所述的方法，其特征在于，所述氧化铜形成步骤包括将铜的表层置于氧气等离子体中。
33、如权利要求31所述的方法，其特征在于，所述氧化铜形成步骤包括将铜表层置于热的氧气中。
34、如权利要求31所述的方法，其特征在于，所述氧化铜形成步骤包括将铜表层置于氧化剂中。
35、如权利要求31所述的方法，其特征在于，所述氧化铜形成步骤包括用电化学法氧化铜表层。
36、如权利要求31所述的方法，其特征在于，所述转化包括将所述氧化铜置于氮气等离子体中。
37、如权利要求31所述的方法，其特征在于，所述转化包括将所述氧化铜置于气态氨中。
38、一种用于半导体装置中的改进的交互连接结构，其包括一个导电层和至少一个与所述导电层电性连接的压焊表层，所述压焊表层包含Cu(N)。
CNA2004800159031A 2003-04-09 2004-04-09 集成电路的电交互连接结构及其制造方法 Pending CN1802744A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46177603P 2003-04-09 2003-04-09
US60/461,776 2003-04-09

Publications (1)

Publication Number Publication Date
CN1802744A true CN1802744A (zh) 2006-07-12

Family

ID=33299860

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800159031A Pending CN1802744A (zh) 2003-04-09 2004-04-09 集成电路的电交互连接结构及其制造方法

Country Status (4)

Country Link
US (1) US7294217B2 (zh)
CN (1) CN1802744A (zh)
TW (1) TW200501289A (zh)
WO (1) WO2004093185A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359639B (zh) * 2007-07-31 2012-05-16 欣兴电子股份有限公司 埋入半导体芯片的电路板结构及其制法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4426917B2 (ja) * 2004-07-16 2010-03-03 株式会社ルネサステクノロジ 半導体装置の製造方法
US20070071900A1 (en) * 2005-09-29 2007-03-29 Philippe Soussan Methods for protecting metal surfaces
US20090256245A1 (en) * 2008-04-14 2009-10-15 Yong Liu Stacked Micro-Module Packages, Systems Using the Same, and Methods of Making the Same
US20090315163A1 (en) * 2008-06-20 2009-12-24 Terry Johnson Semiconductor Die Packages with Stacked Flexible Modules Having Passive Components, Systems Using the Same, and Methods of Making the Same
US20090315162A1 (en) * 2008-06-20 2009-12-24 Yong Liu Micro-Modules with Molded Passive Components, Systems Using the Same, and Methods of Making the Same
WO2010010753A1 (ja) * 2008-07-22 2010-01-28 国立大学法人東北大学 配線基板及びその製造方法
US8105937B2 (en) * 2008-08-13 2012-01-31 International Business Machines Corporation Conformal adhesion promoter liner for metal interconnects
US8357998B2 (en) * 2009-02-09 2013-01-22 Advanced Semiconductor Engineering, Inc. Wirebonded semiconductor package
JP5955223B2 (ja) * 2009-12-23 2016-07-20 ヘレウス ノーブルライト アメリカ エルエルシー 小型硬化用ランプ組立体用ｕｖｌｅｄを基礎としたランプ
JP5734581B2 (ja) * 2010-05-21 2015-06-17 シャープ株式会社 半導体発光装置
JP5909852B2 (ja) * 2011-02-23 2016-04-27 ソニー株式会社 半導体装置の製造方法
US8618677B2 (en) 2012-04-06 2013-12-31 Advanced Semiconductor Engineering, Inc. Wirebonded semiconductor package
US8859419B2 (en) 2013-02-01 2014-10-14 Globalfoundries Inc. Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
US8753975B1 (en) 2013-02-01 2014-06-17 Globalfoundries Inc. Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device
US9196591B2 (en) 2014-02-17 2015-11-24 International Business Machines Corporation Chip with shelf life
US9245846B2 (en) 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US11475578B2 (en) 2018-06-19 2022-10-18 Teikyo University Method for analyzing behavior of cell, and use thereof
US11289365B2 (en) * 2019-11-07 2022-03-29 Qualcomm Incorporated Air gap underneath passive devices
US11817420B2 (en) * 2021-07-19 2023-11-14 Micron Technology, Inc. Systems and methods for direct bonding in semiconductor die manufacturing

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6156990A (en) * 1998-06-22 2000-12-05 Kulicke & Soffa Industries, Inc. Long-wearing impervious conductive wire clamp
US6352743B1 (en) * 1998-10-05 2002-03-05 Kulicke & Soffa Investments, Inc. Semiconductor copper band pad surface protection
US6413576B1 (en) * 1998-10-05 2002-07-02 Kulicke & Soffa Investments, Inc. Semiconductor copper bond pad surface protection
EP1190446A1 (de) * 1999-06-28 2002-03-27 Unaxis Balzers Aktiengesellschaft Bauteil und verfahren zu dessen herstellung
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6599561B2 (en) * 2001-11-30 2003-07-29 Kulicke & Soffa Investments, Inc. Method for manufacturing a printed circuit board substrate
US20040155702A1 (en) 2003-02-11 2004-08-12 Siemens Elema Ab Active filter circuit arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359639B (zh) * 2007-07-31 2012-05-16 欣兴电子股份有限公司 埋入半导体芯片的电路板结构及其制法

Also Published As

Publication number Publication date
TW200501289A (en) 2005-01-01
WO2004093185A3 (en) 2005-01-27
WO2004093185A2 (en) 2004-10-28
US7294217B2 (en) 2007-11-13
US20070026574A1 (en) 2007-02-01

Similar Documents

Publication Publication Date Title
CN1802744A (zh) 集成电路的电交互连接结构及其制造方法
US6593160B2 (en) Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power led chip
KR100376955B1 (ko) Rf반응성스퍼터된티타늄텅스텐과금을갖는마이크로회로상호접속용일렉트로마이그레이션방지금속화구조
US3881884A (en) Method for the formation of corrosion resistant electronic interconnections
KR101384467B1 (ko) 태양 전지 및 그 제조 방법
US6380626B1 (en) Semiconductor device for attachment to a semiconductor substrate
CN1112729C (zh) 电子器件中的电连接结构和导体表面材料的形成方法
WO2008021268A1 (en) Led device and back panel of liquid crystal display
GB2300970A (en) Method for fabricating a diffusion barrier metal layer
KR20050087840A (ko) 구리 상호 접속 구조체로의 본딩 구조체 및 방법
CN105103272A (zh) 半导体装置的制造方法
KR20140011686A (ko) 전력 소자 및 전력 소자 모듈
JP2005117035A (ja) フリップチップ型窒化ガリウム系半導体発光素子およびその製造方法
US9461211B2 (en) Method for producing a connection region of an optoelectronic semiconductor chip
US6653215B1 (en) Contact to n-GaN with Au termination
US6191485B1 (en) Semiconductor device
CN100562212C (zh) 用于高温条件的绝缘结构及其制造方法
CN108336207A (zh) 一种高可靠性led芯片及其制作方法
JP4969087B2 (ja) 共晶ボンディング発光装置とその製造方法
JP2004285470A (ja) 貴合金はんだメッキ法
CN108365056A (zh) 一种垂直结构发光二极管及其制造方法
JPS62224048A (ja) ダイヤモンド膜製半導体基板の製造方法
CA1320991C (en) Method of contacting semiconductor cathodes and of manufacturing an electron tube provided with such a cathode
JPH11286773A (ja) スパッタ法及び配線形成法並びにスパッタリングターゲットとその製法
JPH09205092A (ja) 半導体製造方法、および、その装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned
C20 Patent right or utility model deemed to be abandoned or is abandoned