CN1801796B - Frequency synchronization device and its method - Google Patents
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Abstract
Present invention relates to frequency synchronism method and device, in particular relating to frequency synchronism method and device for obtaining pilot tone and estimating frequency offset and timing offset. Said method includes executing multi - pre-filtering to fundamental frequency signal metering fundamental frequency signal power in order to generate first power value, metering output pre-filtering signal power to generate multi - second power value, proceeding normalizing utilizing first power value and the maximal in these second power value to generate first detection value, utilizing fundamental frequency signal sampling value and predetermined related functions to generate second detection value, forming third detection value by combining said first detection value and second detection value, and utilizing third detection judging whether frequency correction signal is received.
Description
Technical Field
The present invention relates to a method and an apparatus for frequency synchronization, and more particularly, to a method and an apparatus for frequency synchronization to acquire a pilot tone (pilot tone) and estimate a frequency offset (frequency offset) and a time offset (timing offset) of the pilot tone.
Background
Conventionally, in a wireless communication system having a pilot channel (pilot channel), a mobile station (mobile station) must synchronize with a base station (base station) through the pilot channel to establish a connection and transmit a message.
In Time Division Multiple Access (TDMA) systems, such as GSM systems, a Frequency Correction Channel (FCCH) is used to synchronize the time and frequency of the mobile station. When the mobile station is turned on or needs to perform a handoff (hand over) operation, the mobile station must use the frequency correction channel for time and frequency synchronization. After completing the synchronization, the mobile station can establish connection with the base station and transmit messages to each other.
Since the time occupied by the frequency calibration channel is relatively short, in practical applications, especially under bad radio channel transmission conditions, such as severe noise interference or frequency offset, the mobile station often needs to detect the frequency calibration channel to maintain or establish a connection with the base station.
Please refer to fig. 1, which is a block diagram of a conventional frequency synchronization apparatus. The frequency synchronization apparatus includes a calibrator 100, a frequency shifter 110, a low-pass filter 120, a phase measurement circuit 130, a phase difference measurer 140, an accumulator 150, a frequency offset estimation circuit 160, and a quality factor estimation circuit 170.
The normalizer 100 is used to normalize the received signal so that the magnitude of the signal can be limited within a certain range, and the normalizer 100 is generally implemented by using a lookup table (lookup table). After normalization, the center frequency (center frequency) of the signal is adjusted back to the fundamental frequency by the frequency shifter 110.
After filtering part of the noise by the low pass filter 120, the phase measurement circuit 130 extracts the phase of the signal. Then, the phase difference measurer 140 compares the phases of the previous and next signals to obtain the phase difference between the signals. After the phase difference values are accumulated by the accumulator 150, the frequency offset estimation circuit 160 estimates a frequency offset value by using the accumulated result. Then, the quality coefficient estimation circuit 170 estimates a quality coefficient by using the frequency offset value to determine whether the estimated frequency offset value is accurate.
However, since the calibrator 100 of the conventional frequency synchronization apparatus is generally implemented by a lookup table, the conventional frequency synchronization apparatus requires a considerable memory capacity for storing the lookup table, which increases the cost greatly, and thus is not practical.
Please refer to fig. 2, which is a flowchart illustrating an operation of another conventional frequency synchronization apparatus. As shown, the frequency synchronization apparatus first uses a first adaptive bandpass filter to filter the baseband signal Xn to generate the signal Yn (S201). Using the signal Yn, the frequency synchronization apparatus can adjust the pole (pole) of the first adaptive bandpass filter (S202) so that it can be consistent with the frequency provided by the frequency correction channel. In addition, the frequency synchronization apparatus may also adjust a gain (gain) of a signal using the signal Yn (S203-S205) to determine whether a frequency correction signal is present (S206), and update a timer (S207).
Furthermore, the baseband signal Xn is stored in a signal buffer (S208), and after the adjustment of the first adaptive bandpass filter is completed, the frequency synchronization device performs formal filtering on the baseband signal Xn by using the first bandpass filter (S210). Thereafter, the frequency synchronization apparatus obtains a frequency offset value by using a frequency offset estimation circuit (S209). Therefore, the frequency synchronization device can completely extract the signal provided by the frequency correction channel to estimate the frequency offset value of the system.
However, the frequency synchronization apparatus introduces some potential problems because the frequency synchronization apparatus uses an adaptive filter to process signals to estimate frequency offset values and perform slot calibration. For example, the time delay caused when adjusting the parameters of the adaptive filter; during the adjustment process, the adaptive filter may cause its parameters to exceed a limit value, so that the frequency synchronization apparatus cannot detect the frequency correction channel at all.
Disclosure of Invention
The main objective of the present invention is to provide a method and apparatus for frequency synchronization, which obtains a pilot tone (pilot tone) and estimates a frequency offset (frequency offset) and a time offset (timing offset) of the pilot tone.
Another objective of the present invention is to provide a method and apparatus for frequency synchronization, which does not require a large amount of memory to store additional lookup tables during normalization.
It is still another object of the present invention to provide a method and apparatus for frequency synchronization, which can reduce the time delay and the failure to detect the frequency calibration channel without dynamically adjusting the pre-filter according to the location or the input signal.
To achieve the above object, the present invention provides a method for frequency synchronization to detect whether a frequency calibration signal exists, comprising:
receiving a second predetermined number of clock signals, wherein the second predetermined number of clock signals are divided into a plurality of signal groups, and each signal group comprises a first predetermined number of clock signals;
processing each signal group to obtain an average power value of each signal group on different frequency bands;
selecting a maximum one from the average power values of all the signal groups as a second power average value;
the method generates a first detection value by using the second power average value, and determines whether the frequency correction signal exists through the first detection value.
In order to achieve the above object, the present invention provides a frequency synchronization apparatus, for detecting whether a frequency correction signal exists, the frequency synchronization apparatus comprising:
a plurality of signal power generators for receiving a first predetermined number of the frequency signals and calculating average power values of the first predetermined number of the frequency signals in different frequency bands;
a maximum signal selector connected to the signal power generators for receiving the average power values of the frequency signals to select the maximum one of the average power values as a second power average value;
the frequency synchronization device generates a first detection value by using the second power average value, and determines whether the frequency correction signal exists through the first detection value.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1 is a block diagram of a conventional frequency synchronization apparatus;
FIG. 2 is a flowchart illustrating an operation of another conventional frequency synchronization apparatus;
FIGS. 3A-3C are system block diagrams of the frequency synchronization apparatus of the present invention;
FIG. 4A is an internal block diagram of a first embodiment of a power meter according to the present invention;
FIG. 4B is an internal block diagram of a second embodiment of a power meter according to the present invention;
FIG. 4C is an internal block diagram of a third embodiment of a power meter according to the present invention;
FIG. 5 is a spectral distribution diagram of a prefilter of the present invention;
FIG. 6 is a schematic diagram of the constellation of samples of the baseband signal according to the present invention;
FIG. 7 is a diagram illustrating a relationship between a third detection value and time;
FIGS. 8A-8C are flow charts illustrating operation of a preferred embodiment of the frequency synchronization method according to the present invention;
fig. 9 is a flowchart of a method for calculating a first detection value according to the present invention.
[ description of main reference symbols ]
Standardizing device 100
Phase difference measuring device 140
Accumulator 150
Frequency offset estimation circuit 160
Quality coefficient estimation circuit 170
Reduced sampler 411
Squarer 413
Detailed Description
Please refer to fig. 3A, which is a system block diagram of a frequency synchronization apparatus according to a first embodiment of the present invention. As shown, the frequency synchronization apparatus of the present invention includes a plurality of pre-filters 3011, 3031, 3051, a plurality of power meters 3111, 3131, 3151, 3171, a plurality of signal averagers 3211, 3231, 3251, 3271, a maximum signal selector 3301, a power calibrator 3401, and a signal processor 3501.
In practice, the present invention may have a plurality of signal power generators (each including a pre-filter, a power measurer and a signal averager), and the number of the signal power generators is not limited, and the larger the number of the signal power generators, the more accurate the frequency offset value estimated by the present invention is. In addition, the input signal of the frequency synchronization apparatus of the present invention is a base-band signal samples (samples) of the baseband signal received and demodulated by the mobile station from the wireless channel.
First, the frequency synchronization apparatus of the present invention uses these pre-filters 3011, 3031, and 3051 to perform pre-filtering on the demodulated baseband signal. Then, the frequency synchronization apparatus uses the power measuring devices 3111, 3131, 3151, 3171 to measure the power of each pre-filtered signal, and uses the signal averagers 3211, 3231, 3251, 3271 to obtain the average power value of the signal of each path.
The power meters 3111, 3131, 3151, 3171 can be implemented in many different ways, and the implementation of the power meters 3111, 3131, 3151, 3171 is not limited in the present invention. To make the disclosure of the present invention more clear, please refer to fig. 4A-4C, which are possible implementations of the power meter of the present invention.
FIG. 4A is an internal block diagram of a power meter according to a first embodiment of the present invention. The power meter has a squarer 401, an accumulator 403, and a decimator 405. The squarer 401 is used to calculate the square value of each baseband signal sample; the accumulator 403 is used to add the square values of two consecutive samples of the baseband signal; the down sampler 405 is used to perform down sampling (down sampling) to reduce the amount of operation of the system. With this embodiment, a real-time power value is obtained for every two samples.
FIG. 4B is an internal block diagram of a power meter according to a second embodiment of the present invention. Wherein the power meter has a reduced sampler 411 and a squarer 413. The down sampler 411 is used to perform down sampling (down sampling) to reduce the amount of computation of the system; the squarer 413 is used for calculating the square value of the baseband signal samples to obtain the real-time power value.
FIG. 4C is an internal block diagram of a power meter according to a third embodiment of the present invention. The power meter has an accumulator 421, a reduced sampler 423, and a squarer 425. The accumulator 421 is used to add two consecutive samples of the baseband signal; the down sampler 423 is used for performing down sampling (down sampling) to reduce the amount of calculation of the system; the squarer 425 is used to calculate the square of the accumulated samples of the baseband signal to obtain the real-time power value.
After calculating the real-time power values and averaging the power values of the paths, the frequency synchronization apparatus of the present invention uses the maximum signal selector 3301 to compare the average power values of the signals of the paths to find a signal with the maximum power, and transmits the signal to the signal power calibrator 3401. The power normalizer 3401 normalizes the signal with the maximum power to make the signal size fall between 0 and 1To generate a first detection value PnTo determine whether the frequency calibration channel sends a frequency calibration signal.
In GSM, for example, various logical channels (logical channels) are used for transmitting user information and control signals, and these logical channels actually utilize time slots (slots) of physical channels (physical channels) for transmitting signals. The frequency correction channel is one of the logical channels, and the frequency correction channel sends out the frequency correction signal to perform frequency synchronization.
Since the signal modulation is gmsk (gaussian minimum shift keying) and the content of the frequency correction signal is a series of "0", after demodulation, the frequency correction signal forms a sine wave with a frequency of about 66.7 kHz.
In addition, the frequency generated by the frequency synthesizer (frequency synthesizer) of the mobile station of the GSM system, such as a mobile phone, is generally less accurate due to cost considerations. Furthermore, since the frequency generated by the frequency synthesizer is affected by temperature, the generated frequency generally changes with temperature.
The frequency generated by the mobile station is usually shifted by a frequency offset, such as 20kHz, compared to the carrier frequency generated by the base station. Therefore, when the mobile station is turned on or needs to perform a handoff (hand over) operation, the mobile station must use the frequency correction channel for time and frequency synchronization.
However, since the frequency offset value is unknown, the mobile station of the GSM system may shift the base frequency of the received frequency correction signal during demodulation (i.e., the frequency of the frequency correction signal may deviate from 66.7kHz after demodulation). Therefore, the present invention uses the pre-filters 3011, 3031, and 3051 with different center frequencies to perform filtering operation on the baseband signal to detect the frequency correction signal and find the offset value of the frequency correction signal.
In the present invention, since the pre-filters 3011, 3031, and 3051 have specific frequency bands, the present invention can detect a wider frequency band as a whole. Furthermore, since the frequency band detectable by the present invention is increased or the resolution of the signal detection of the present invention is increased when the number of the pre-filters used is increased, the frequency correction signal detection capability and the frequency correction capability of the present invention can be enhanced by increasing the number of the pre-filters. In practice, the number of these pre-filters may be increased or decreased as needed or cost considerations dictate.
In addition, since the pre-filter used in the present invention does not need to be dynamically adjusted according to the location or the input signal, compared with the prior art using an adaptive filter, the present invention is less likely to cause the problems of time delay and the inability to detect the frequency correction channel.
In practice, these pre-filters 3011, 3031, 3051 may be implemented using IIR filters (infinite impulse response filters) or FIR filters (finite impulse response filters). In the present invention, these pre-filters 3011, 3031, 3051 are IIR filters using a first-order (first-order).
To make the disclosure of the present invention clearer, please refer to fig. 5, which is a spectrum distribution diagram of the prefilter of the present invention. The spectral distributions of these pre-filters 3011, 3031, 3051 are respectively marked by H0～2To indicate. In this embodiment, it is assumed that the frequency of the frequency correction signal after being demodulated mainly falls within the frequency band of the pre-filter 3011 (the frequency correction signal may also fall within the frequency band of the pre-filter 3031 or 3051), wherein the frequency correction signal is represented by an arrow.
It is obvious that in this case, the power of the output signal of the pre-filter 3011 is greater than that of the output signal of the pre-filter 3031 or 3051. Therefore, after the processing by the power meters 3131, 3151, 3171 and the signal averagers 3231, 3251, 3271, the maximum signal selector 3301 selects the signal output by the path using the pre-filter 3011, i.e., the signal output by the signal averager 3231, for subsequent processing.
Furthermore, in order to provide a reference value for the power calibrator 3401 to perform normalization, the frequency synchronization apparatus of the present invention directly measures the power of the frequency calibration signal by the power meter 3111, and obtains the average power value by the signal averager 3211 to serve as the reference value for the power calibrator 3401.
Then, using the reference value, the power normalizer 3401 makes the magnitude of the signal output by the signal averager 3231 fall between 0 and 1 to generate the first detection value Pn. In the present invention, the power normalizer 3401 is implemented by dividing the average power value output by the signal averager 3231 by the average power value output by the signal averager 3211 to normalize the signal.
Since the path of the signal averager 3211 does not use a pre-filter (in general, the power of the signal is reduced by passing through a filter), the average power value outputted by the path is larger than that outputted by other paths, and the power normalizer 3401 makes the magnitude of the outputted signal fall between 0 and 1.
In practice, the power normalizer 3401 is not limited to make the magnitude of the signal fall between 0 and 1, but only needs to make the magnitude of the signal fall within a fixed range to meet the requirement of the present invention.
It is noted that, for the purpose of normalizing the signal by using the power normalizer 3401, the first detection value P is used to reduce the effect of fading effect (fading effect) caused by the wireless channel on the frequency synchronization apparatus of the present inventionnCan fall within a fixed range and cannot fluctuate along with the position of the mobile machine.
In addition, the present invention achieves the signal normalization by dividing the average power value outputted from the signal averager 3231 by the average power value outputted from the signal averager 3211. Therefore, in the normalization process of the present invention, a large amount of memory is not required to store additional lookup tables, so that the present invention can greatly reduce the cost compared with the prior art.
After obtaining the first detection value PnThen, the power calibrator 3401 of the present invention will detect the first detection value PnTo the signal processor 3501. The signal processor 3501 utilizes the first detection value PnTo determine whether the frequency calibration channel sends a frequency calibration signal, when the first detection value PnWhen the frequency is greater than a first preset threshold, it is determined that the frequency correction channel has sent a frequency correction signal. Otherwise, the frequency calibration channel is considered not to send a frequency calibration signal. In practice, the first threshold is preset between 0.75-0.8, but the invention is not limited thereto, and the setting of the first threshold can be changed according to the actual application.
When the signal processor 3501 determines that the frequency correction channel has sent a frequency correction signal, it calculates an estimate of the frequency offset value using the signal sent by the maximum signal selector 3301 through the power normalizer 3401. Taking fig. 5 as an example, the frequency band in which the frequency correction signal falls is H0Therefore, the signal output by the pre-filter 3011 has the largest power, and the largest signal selector 3301 sends a signal to the signal processor 3501 that the signal output by the pre-filter 3011 is the largest signal. Thus, the signal processor 3501 can know that the frequency of the frequency correction signal falls within the frequency band of the pre-filter 3011, and calculate the difference between the operating frequency of the frequency synchronization device itself and the center frequency of the pre-filter 3011 to obtain the frequency offset value.
Please refer to fig. 3B, which is a system block diagram illustrating a frequency synchronization apparatus according to a second embodiment of the present invention. As shown, the frequency synchronization apparatus of the present invention has a plurality of pre-filters 3012, 3032, 3052, a plurality of power meters 3132, 3152, 3172, a plurality of signal averagers 3232, 3252, 3272, a maximum signal selector 3302 and a signal processor 3502.
Since the pre-filters 3012, 3032, 3052, the power meters 3132, 3152, 3172, the signal averagers 3232, 3252, 3272, and the maximum signal selector 3302 have the same functions and embodiments as the same devices in the first embodiment, they are not described again here.
The main difference between the second embodiment and the first embodiment is that the signal processor 3502 samples the baseband signal at different time points, compares the baseband signal at different time points, and generates a second detection value by using a predetermined correlation function.
Since the sampled values of the fundamental frequency signal can be expressed in mathematical form when transmitting the frequency correction signal:
wherein, wnSample values, s, of ambient noisenRefers to the value, V, of the demodulated and sampled signal from the base stationnReferring to received power, θ is a phase difference value caused by a local oscillator (local oscillator), and
refers to the phase difference caused by the wireless channel. Therefore, the sampled values of four consecutive base frequency signals can be represented by the constellation diagram shown in fig. 6.
As shown in fig. 6, since snAnd sn+2And sn+1And sn+3The difference between them is the largest, so to obtain a larger detection value, the correlation function of the signal processor 3502 is set as:
An＝(rn+2-rn)×(rn+3-rn+1)，
wherein,r n -r n+3 for samples of the fundamental frequency signal at different time points, A n As a function of the value of the correlation functionThe symbol "x" shown in the above formula represents an outer product.
After the values obtained by the correlation function are accumulated and normalized, the second detected value Q can be generatedn. First, the signal processor 3502 generates two accumulated values by using the values obtained by the correlation function and the k-th power of the absolute value thereof, as shown in the following formula 2:
wherein, k is an odd number, and the invention makes k equal to 1 so as to reduce the operation amount; and N is the size of a preset moving window, which is used for representing the number of accumulations each time.
Then, the signal processor 3502 performs a normalization operation to generate the second detection value QnThe operation is shown as the following formula:
Qn＝S1/S2
thus, the second detection value QnAlso has a numerical value ofBetween 0 and 1.
The signal processor 3502 uses the second detection value QnTo determine whether the frequency calibration channel sends a frequency calibration signal, when the second detection value QnIf the value is greater than a second threshold, it is determined that the frequency calibration channel has sent a frequency calibration signal. Otherwise, the frequency calibration channel is considered to not send a frequency calibration signal. In practice, the second threshold is preset between 0.75-0.8, but the invention is not limited thereto, and the setting of the second threshold can be changed according to the actual application.
When the signal processor 3502 determines that the frequency correction channel has sent a frequency correction signal, it calculates an estimate of the frequency offset value using the signal sent by the maximum signal selector 3302. Taking fig. 5 as an example, the frequency band in which the frequency correction signal falls is H0Therefore, the signal output by the pre-filter 3012 has the largest power, and the maximum signal selector 3302 sends a signal to the signal processor 3502 that the signal output by the pre-filter 3012 is the largest signal. Thus, the signal processor 3502 can know that the frequency of the frequency correction signal falls within the frequency band of the pre-filter 3012, and calculate the difference between the operating frequency of the frequency synchronization device itself and the center frequency of the pre-filter 3012 to obtain the frequency offset value.
Please refer to fig. 3C, which is a block diagram of a frequency synchronization apparatus according to a third embodiment of the present invention. As shown, the frequency synchronization apparatus of the present invention includes a plurality of pre-filters 3013, 3033, 3053, a plurality of power meters 3113, 3133, 3153, 3173, a plurality of signal averagers 3213, 3233, 3253, 3273, a maximum signal selector 3303, a power calibrator 3403, and a signal processor 3503.
Since the pre-filters 3013, 3033, 3053, the power meters 3113, 3133, 3153, 3173, the signal averagers 3213, 3233, 3253, 3273, the maximum signal selector 3303, and the power calibrator 3403 have the same functions and embodiments as the same devices in the first embodiment, further description is omitted here.
Like the first embodiment, the maximum signal selector 3303 compares the average power values of the signals from the signal averagers 3233, 3253, 3273 to find a signal with the maximum power, and sends the signal to the signal power normalizer 3403. The power normalizer 3403 normalizes the signal with the maximum power to make the magnitude of the signal fall between 0 and 1 to generate a first detection value Pn. Wherein the frequency synchronization device can be based on the first detection value PnTo determine whether the frequency calibration channel sends a frequency calibration signal.
After obtaining the first detection value PnThen, the power calibrator 3403 of the present invention will detect the first detection value PnTo the signal processor 3503. The signal processor 3503 utilizes the first detection value PnTo determine whether the frequency calibration channel sends a frequency calibration signal, when the first detection value PnWhen the frequency is greater than a first preset threshold, it is determined that the frequency correction channel has sent a frequency correction signal. Otherwise, the frequency calibration channel is considered not to send a frequency calibration signal.
Similar to the second embodiment, the signal processor 3503 generates a second detection value Q by using the sampled values of the baseband signal at different time points and a predetermined correlation functionn. Wherein the frequency synchronization device can be based on the second detection value QnTo determine whether the frequency calibration channel sends a frequency calibration signal. When the second detection value QnIf the value is greater than a second threshold, it is determined that the frequency calibration channel has sent a frequency calibration signal. Otherwise, the frequency calibration channel is considered to not send a frequency calibration signal.
As described above, signal processor 3503 can utilize the first detection value P alonenOr a second detected value QnTo determine whether the frequency calibration channel sends a frequency calibration signal, and when the first detection value PnOr a firstTwo detected values QnIf the value is greater than the first threshold or the second threshold, the signal processor 3503 determines that the frequency correction channel has sent a frequency correction signal. At this time, the signal processor 3503 can determine which pre-filtered band the fundamental frequency of the frequency correction signal falls within (i.e. the one outputting the maximum power) through the information provided by the maximum signal selector 3303, and thereby perform the frequency synchronization.
In the third embodiment, the signal processor 3503 combines the first detection value PnAnd a second detection value QnTo determine whether the frequency calibration channel sends a frequency calibration signal, the combination of the frequency calibration signal and the frequency calibration signal is as follows:
Rn＝λ·Qn+(1-λ)·Pn
wherein λ is set between 0 and 1, as required. Thus, the first detection value P is, as a whole, the valuenAnd a second detection value QnThe third detection value R generated by the bindingnAlso between 0 and 1.
Due to the first detection value PnDerived from the power value of the signal and therefore less disturbed by the amount of phase error of the signal itself. However, since the baseband signal must first pass through the pre-filter before the first detection value P is performednSo that there is a loss of energy, so that generally the first detection value PnIs compared with the second detection value QnThe peak value of (a) is low.
Furthermore, since the second detection value QnDerived from the baseband signals of different phases taken at different time points, so that the second detection value QnMay be more susceptible to interference by the amount of phase error in the signal itself. However, since the signal processor directly uses the sampled values of the baseband signal to derive the second detected value QnSo that the peak value thereof is compared with the first detection value PnIs high.
Therefore, the present invention combines the first detection value PnAnd a second detected valueQnTo generate the third detection value RnTo minimize instability due to loss of phase error and energy.
It is noted that when λ is 0, Rn＝PnAnd when λ is 1, Rn＝QnThese two extreme examples are the case where either of the detection values is used alone as described above.
Please refer to fig. 7, which is a diagram illustrating a relationship between a third detection value and time. Wherein the horizontal axis of the graph represents time, and the vertical axis represents the third detection value RnThe size of (d); the first and second threshold values are respectively TH1And TH2And (4) showing. As shown in the figure, the third detection value R is at the beginning of receiving the frequency correction signalnThe third detection value R increases with time at the later stage of receiving the frequency correction signalnWill decrease over time.
The above-mentioned phenomenon is caused mainly by the first detection value PnDerived from an accumulated value of the power of the signal, and the second detection value QnIs derived from the accumulated value of the correlation function values generated by signal processor 3503. At the beginning of receiving the frequency correction signal, the frequency correction signal inputted to the frequency synchronization device is gradually increased, so that the third detection value RnWill gradually increase; on the contrary, in the later period of receiving the frequency correction signal, the frequency correction signal inputted to the frequency synchronization device is gradually decreased, so that the third detection value RnWill gradually decrease.
The frequency synchronization device of the present invention utilizes this phenomenon to detect the frequency correction signal. When the third detection value RnWhen the first threshold value is exceeded, it can be determined that the frequency synchronization device has received a frequency correction signal, and when the third detection value R is exceedednIf the second threshold value is exceeded, the frequency synchronization device can be confirmed to receive the frequency correction signal; otherwise, the frequency synchronization device is considered not to receive the frequency correction signal. In practice, the first threshold is preset at 0.75, and the second threshold is preset at 0.8,however, the invention is not limited. In addition, the setting of the first and second thresholds may be changed according to actual requirements, but the second threshold needs to be larger than the first threshold.
When the frequency synchronization device confirms that the frequency correction signal is received, it can find out the pre-filter of the output signal with the maximum power to estimate the frequency offset value of the system. In addition, the frequency synchronization device also utilizes the third detection value RnTo estimate the time offset value of the system. When the signal processor 3503 determines that the frequency correction channel has sent a frequency correction signal, it calculates an estimate of the frequency offset value using the signal sent by the maximum signal selector 3303 through the power normalizer 3403. Taking fig. 5 as an example, the frequency band in which the frequency correction signal falls is H0Therefore, the signal output by the pre-filter 3013 has the largest power, and the maximum signal selector 3303 sends a signal to the signal processor 3503 that the signal output by the pre-filter 3013 is the largest signal. Therefore, the signal processor 3503 can know that the frequency of the frequency correction signal falls within the frequency band of the pre-filter 3013, and calculate the difference between the operating frequency of the frequency synchronization device itself and the center frequency of the pre-filter 3013 to obtain the frequency offset value.
To make the disclosure of the present invention clearer, please refer to fig. 8A, which is a flowchart illustrating the operation of the first preferred embodiment of the frequency synchronization method according to the present invention. The method comprises the following steps:
step 8011: executing an initialization program;
step 8031: calculating a first detection value Pn；
Step 8051: determining whether there are N continuous signals to make the first detection value PnGreater than a first threshold value TH1Is there a If yes, entering a step 8111, otherwise, jumping to a step 8131;
step 8111: find out the time offset and the frequency offset and determine whether these offsets are within a predetermined range? If yes, entering a step 8151, otherwise, jumping to a step 8131;
step 8131: determine whether a predetermined value of a receive window (RX window) is reached? If yes, go to step 8011, otherwise, go to step 8031; and
step 8151: and (6) ending.
As shown in fig. 9, step 8031 further includes:
step 901: using a plurality of pre-filters to perform a filtering action on a fundamental frequency signal of the frequency correction signal;
step 903: measuring the power of the baseband signal by using a first power measuring device to generate a first power value; using a plurality of second power measuring devices to respectively measure the power of the signals output by the prefilters so as to generate a plurality of second power values; the number of the second power measurers is equal to that of the prefilters and corresponds to that of the prefilters one by one; and
step 905: calculating an average value of a predetermined number of first power values by using a first signal averager to generate a first power average value; calculating the average value of a predetermined number of second power values by using a plurality of second signal averagers respectively, wherein the number of the second signal averagers is equal to the number of the second power measuring devices and corresponds to the second signal averagers one by one; selecting the largest one of the average power values output by the second signal averagers by using the maximum signal selector to generate a second average power value; and using a power calibrator to divide the second power average value by the first power average value to perform normalization operation to generate the first detection value Pn。
To make the disclosure of the present invention clearer, please refer to fig. 8B, which is a flowchart illustrating an operation of the frequency synchronization method according to the second preferred embodiment of the present invention. The method comprises the following steps:
step 8012: executing an initialization program;
step 8072: calculating a second detected value Qn(please refer to the above calculation method);
step 8092: judging whether there are M continuous signals to make the second detection value QnGreater than a second threshold value TH2And the second detection value Q is madenRise and fall? If yes, entering a step 8112, otherwise, jumping to a step 8132;
step 8112: find out the time offset and the frequency offset and determine whether these offsets are within a predetermined range? If yes, go to step 8152, otherwise, go to step 8132;
step 8132: determine whether a predetermined value of a receive window (RX window) is reached? If yes, go to step 8012, otherwise, go to step 8072; and
step 8152: and (6) ending.
To make the disclosure of the present invention clearer, please refer to fig. 8C, which is a flowchart illustrating an operation of the frequency synchronization method according to the third preferred embodiment of the present invention. The method comprises the following steps:
step 8013: executing an initialization program;
step 8033: calculating a first detection value Pn；
Step 8053: determining whether there are N continuous signals to make the first detection value PnGreater than a first threshold value TH1Is there a If yes, go to step 8073, otherwise, go to step 8133;
step 8073: calculating a second detected value Qn(please refer to the above-mentioned calculation method), and by combining the first detection value PnAnd a second detection value QnTo generate a third detection value Rn(please refer to the above combination);
step 8093: determining whether there are M continuous signals to make the third detection value RnGreater than a second threshold value TH2And the third detection value R is usednRise and fall? If yes, go to step 8113, otherwise, go to step 8133;
step 8113: find out the time offset and the frequency offset and determine whether these offsets are within a predetermined range? If yes, go to step 8153, otherwise, go to step 8133;
step 8133: determine whether a predetermined value of a receive window (RX window) is reached? If yes, go to step 8013, otherwise, go to step 8033; and
step 8153: and (6) ending.
Step 8033 has the steps shown in fig. 9, which are the same as those in the first embodiment, and are not described again here.
In summary, the present invention has the following features and advantages:
(1) in the normalization process, a large amount of memory is not needed to store additional lookup tables, so that compared with the prior art, the cost can be greatly reduced.
(2) Since the pre-filter used in the present invention does not need to be dynamically adjusted according to the location or the input signal, the present invention is less likely to cause the problems of time delay and the inability to detect the frequency correction channel, compared to the prior art using an adaptive filter.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (62)
1. A frequency synchronization apparatus for detecting whether a frequency correction signal is present, the frequency synchronization apparatus comprising:
a plurality of signal power generators for receiving a first predetermined number of the frequency signals and calculating average power values of the first predetermined number of the frequency signals in different frequency bands;
a maximum signal selector connected to the signal power generators for receiving the average power values of the frequency signals to select the maximum one of the average power values as a second power average value;
the frequency synchronization device generates a first detection value by using the second power average value, and determines whether the frequency correction signal exists through the first detection value.
2. The frequency synchronization apparatus of claim 1, wherein the frequency signal is a baseband signal.
3. The frequency synchronization apparatus of claim 2, further comprising:
a first power measurer for measuring the power of a second predetermined number of the clock signals to generate a first power value of the second predetermined number, wherein the second predetermined number is the number of the plurality of signal power generators multiplied by the first predetermined number;
a first signal averager connected to the first power measurer for receiving the second predetermined number of first power values and calculating an average of the second predetermined number of first power values to generate a first power average.
4. The frequency synchronization apparatus of claim 3, further comprising:
a power calibrator connected to the first signal averager and the maximum signal selector for receiving the first power average value and the second power average value and normalizing the second power average value by the first power average value to generate the first detection value;
the frequency synchronization device uses the first detection value to determine whether the frequency correction signal exists.
5. The frequency synchronization apparatus of claim 3, wherein the first power meter further comprises:
a squarer for calculating the square value of the sampling point of the base frequency signal;
an accumulator for adding two successive square values;
a down sampler for performing the down sampling operation.
6. The frequency synchronization apparatus of claim 2, wherein each of the plurality of signal power generators comprises:
a pre-filter for performing a filtering operation on the frequency signal;
a second power measurer connected to the pre-filter for measuring the power of the signal output by the pre-filter to generate a second power value;
a second signal averager, connected to the second power measurer, for receiving the second power value and calculating an average of a predetermined number of the second power values.
7. The frequency synchronization apparatus of claim 6, wherein the second power meter further comprises:
a down-sampler for performing down-sampling on the baseband signal samples;
a squarer for calculating the square value of the sampled points of the down-sampled baseband signal.
8. The apparatus of claim 6, wherein the pre-filters have different center frequencies and different frequency bands.
9. The apparatus of claim 6, wherein the pre-filter is an IIR filter or an FIR filter.
10. The apparatus of claim 4, wherein the power normalizer divides the second power average by the first power average to perform the normalization and generates the first detection value.
11. The apparatus of claim 4, wherein the time offset of the system is estimated by using a time point of occurrence of a peak value of the first detection value.
12. The apparatus of claim 4, wherein the frequency synchronization apparatus determines that the frequency correction signal has been received when the first detected value is greater than a first threshold value.
13. The apparatus of claim 12, wherein the first threshold is in a range of 0.75-0.8.
14. The apparatus of claim 8 further comprising a signal processor having a function of estimating a frequency offset of the frequency synchronization apparatus.
15. The apparatus of claim 14, wherein the signal processor estimates the frequency offset value by using a difference between a center frequency of the pre-filters and an operating frequency of the frequency synchronization apparatus.
16. The apparatus of claim 15 wherein the signal processor estimates the frequency offset value by selecting a center frequency of a pre-filter that outputs a maximum average power value.
17. A frequency synchronization apparatus for detecting whether a frequency correction signal is present, the frequency synchronization apparatus comprising:
a plurality of signal power generators for receiving a first predetermined number of the frequency signals and calculating average power values of the first predetermined number of the frequency signals in different frequency bands;
a maximum signal selector connected to the signal power generators for receiving the average power values of the frequency signals to select the maximum one of the average power values as a second power average value;
a signal processor, which uses the sampling values of the frequency signal at different time points and a preset correlation function to generate a second detection value;
the frequency synchronization device generates a first detection value by using the second power average value, and combines the first detection value and the second detection value to generate a third detection value, and determines whether the frequency correction signal exists or not by the third detection value.
18. The apparatus of claim 17, wherein the frequency signal is a baseband signal.
19. The frequency synchronization apparatus of claim 18, further comprising:
a first power measurer for measuring the power of a second predetermined number of the clock signals to generate a first power value of the second predetermined number, wherein the second predetermined number is the number of the plurality of signal power generators multiplied by the first predetermined number;
a first signal averager connected to the first power measurer for receiving the second predetermined number of first power values and calculating an average of the second predetermined number of first power values to generate a first power average.
20. The frequency synchronization device of claim 19, further comprising:
a power calibrator connected to the first signal averager and the maximum signal selector for receiving the first power average value and the second power average value and normalizing the second power average value by the first power average value to generate the first detection value;
wherein the signal processor generates a third detection value by using the first detection value and combining the second detection value, and determines whether the frequency correction signal exists or not by the third detection value.
21. The frequency synchronization device of claim 19, wherein the first power measurement device further comprises:
a squarer for calculating the square value of the sampling point of the base frequency signal;
an accumulator for adding two successive square values;
a down sampler for performing the down sampling operation.
22. The frequency synchronization device of claim 18, wherein each of the plurality of signal power generators comprises:
a pre-filter for performing a filtering operation on the frequency signal;
a second power measurer connected to the pre-filter for measuring the power of the signal output by the pre-filter to generate a second power value;
a second signal averager, connected to the second power measurer, for receiving the second power value and calculating an average of a predetermined number of the second power values.
23. The frequency synchronization device of claim 22, wherein the second power meter further comprises:
a down-sampler for performing down-sampling on the baseband signal samples;
a squarer for calculating the square value of the sampled points of the down-sampled baseband signal.
24. The apparatus of claim 22, wherein the pre-filter has different center frequencies and different frequency bands.
25. The apparatus of claim 22, wherein the pre-filter is an IIR filter or an FIR filter.
26. The apparatus of claim 20 wherein the power normalizer divides the second power average by the first power average to perform the normalization and generates the first detection value.
27. The apparatus of claim 20, wherein a time offset of the system is estimated by using a time point of occurrence of a peak value of the third detection value.
28. The apparatus of claim 20, wherein the frequency synchronization apparatus initially determines that the frequency correction signal has been received when the third detected value is greater than a first threshold.
29. The apparatus of claim 20, wherein the frequency synchronization apparatus determines that the frequency correction signal has been received when the third detected value is greater than a second threshold value.
30. The frequency synchronization device of claim 17, wherein the correlation function in the signal processor is
An＝(rn+2-rn )×(rn+3-rn+1)，
Wherein r isn～n+3For samples of the fundamental frequency signal at different time points, AnIs the correlation function value and the symbol x represents the outer product.
31. The frequency synchronization device of claim 30, wherein the signal processor accumulates a predetermined number of correlation function values to generate a first accumulated value; and the signal processor accumulates the absolute values of the predetermined number of correlation function values to generate a second accumulated value; then, the signal processor divides the first accumulation value by the second accumulation value to generate the second detection value.
32. The apparatus of claim 30 wherein the signal processor calculates odd power values of the correlation function values to generate first sub-squares and accumulates a predetermined number of the first sub-squares to generate first accumulated values; the signal processor calculates the odd power value of the absolute value of the correlation function value to generate a second power value, and accumulates a predetermined number of the second power values to generate a second accumulated value; then, the signal processor divides the first accumulation value by the second accumulation value to generate the second detection value.
33. The apparatus of claim 20, wherein the third detection value is formed as follows:
Rn＝λ·Qn+(1-λ)·Pn，
wherein λ is set between 0-1, PnIs the first detected value, QnIs the second detected value, and RnIs the third detected value.
34. The apparatus of claim 28, wherein the first threshold is 0.75.
35. The frequency synchronization device of claim 29, wherein the second threshold is 0.8.
36. The apparatus of claim 17 wherein the signal processor has a function of estimating a frequency offset value of the frequency synchronization apparatus.
37. The apparatus of claim 36, wherein the signal processor estimates the frequency offset value by using a difference between a center frequency of the pre-filters and an operating frequency of the frequency synchronization apparatus.
38. The apparatus of claim 37 wherein the signal processor estimates the frequency offset value by selecting a center frequency of a pre-filter that outputs a maximum average power value.
39. A frequency synchronization method for detecting whether a frequency correction signal exists includes:
receiving a second predetermined number of frequency signals, wherein the second predetermined number of frequency signals are divided into a plurality of signal groups, and each signal group comprises a first predetermined number of frequency signals;
processing each signal group to obtain an average power value of each signal group on different frequency bands;
selecting a maximum one from the average power values of all the signal groups as a second power average value;
the method generates a first detection value by using the second power average value, and determines whether the frequency correction signal exists through the first detection value.
40. The method according to claim 39, wherein the frequency signal is a baseband signal.
41. The method for frequency synchronization of claim 40, further comprising:
measuring the power of the second predetermined number of frequency signals to generate a first power value;
calculating the average value of the second predetermined number of the first power values to generate a first power average value.
42. The frequency synchronization method of claim 41, further comprising:
performing a filtering operation on the first predetermined number of frequency signals in each of the signal groups;
measuring the power of the filtered frequency signal to generate a second power value of the first predetermined number;
an average of the first predetermined number of second power values is calculated.
43. The method for frequency synchronization of claim 42, further comprising:
normalizing the second power average value by the first power average value to generate a first detection value;
the method determines whether the frequency correction signal exists by using the first detection value.
44. The method for frequency synchronization of claim 43, wherein the step of operating on the filter is performed using a plurality of pre-filters.
45. The method of claim 44, wherein the pre-filter is an IIR filter or an FIR filter.
46. The method of claim 44, wherein the prefilters have distinct center frequencies and distinct frequency bands.
47. The method according to claim 43, wherein the step of generating the first power value is performed by a first power meter.
48. The method of claim 43, wherein the step of measuring the power of the filtered frequency signal is performed by a second power meter.
49. The frequency synchronization method of claim 43, further comprising:
when a predetermined number of first detection values are continuously greater than a first threshold value, it is determined that the frequency correction signal has been received.
50. The method of claim 43, wherein a time offset of the system is estimated by using a time point of occurrence of a peak of the first detection value.
51. A frequency synchronization method for detecting whether a frequency correction signal exists includes:
receiving a second predetermined number of clock signals, wherein the second predetermined number of clock signals are divided into a plurality of signal groups, and each signal group comprises a first predetermined number of clock signals;
processing each signal group to obtain an average power value of each signal group on different frequency bands;
selecting a maximum one from the average power values of all the signal groups as a second power average value;
measuring the power of the second predetermined number of frequency signals to generate a first power value;
calculating the average value of the second preset number of the first power values to generate a first power average value;
normalizing the second power average value by using the first power average value to generate a first detection value;
generating a second detection value by using a predetermined number of samples of the frequency signal at different time points and a predetermined correlation function;
combining the first detection value and the second detection value to form a third detection value;
the method determines whether the frequency correction signal exists by using the third detection value.
52. The method for frequency synchronization of claim 51, wherein the frequency signal is a baseband signal.
53. The method of claim 51, wherein the third detection value is formed as follows:
Rn＝λ·Qn+(1-λ)·Pn，
wherein λ is set between 0-1, PnIs the first detected value, QnIs the second detected value, and RnIs the third detected value.
54. The method according to claim 51, wherein the step of obtaining the average power value of each signal group further comprises the steps of:
performing a filtering operation on the first predetermined number of frequency signals in each of the signal groups;
measuring the power of the filtered frequency signal to generate a second power value of the first predetermined number;
an average of the first predetermined number of second power values is calculated.
55. The frequency synchronization method of claim 51, further comprising:
when a predetermined number of first detection values are continuously greater than a first threshold value, it is preliminarily determined that the frequency correction signal has been received.
56. The method for frequency synchronization of claim 52, wherein the predetermined correlation function is
An＝(rn+2-rn)×(rn+3-rn+1)，
And rn～n+3For samples of the fundamental frequency signal at different time points, AnIs the correlation function value and the symbol x represents the outer product.
57. The method for frequency synchronization of claim 56, wherein the baseband signal samples are expressed as baseband signal samples
Wherein, wnSample values, s, of ambient noisenRefers to the value, V, of the demodulated and sampled signal from the base stationnMeans received power, theta is a phase difference value caused by a local oscillator, and
refers to the phase difference caused by the wireless channel.
58. The frequency synchronization method of claim 57, further comprising:
accumulating a predetermined number of correlation function values to generate a first accumulated value;
accumulating the absolute values of the predetermined number of correlation function values to generate a second accumulated value;
the first accumulation value is divided by the second accumulation value to generate the second detection value.
59. The frequency synchronization method of claim 57, further comprising:
calculating the odd power value of the correlation function value to generate a first quadratic value, and accumulating a predetermined number of the first quadratic values to generate a first accumulated value;
calculating the odd power value of the absolute value of the correlation function value to generate a second quadratic value, and accumulating a predetermined number of the second quadratic values to generate a second accumulated value;
the first accumulation value is divided by the second accumulation value to generate the second detection value.
60. The frequency synchronization method of claim 51, further comprising:
when a predetermined number of third detection values are continuously greater than a predetermined threshold value, it is determined that the frequency correction signal has been received.
61. The frequency synchronization method of claim 51, further comprising:
when a preset first number of third detection values continuously rise and a preset second number of third detection values continuously fall, the frequency correction signal is judged to be received.
62. The method of claim 51, wherein a time offset of the system is estimated by using a time point of occurrence of a peak of the third detection value.
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| US8803546B2 (en) * | 2011-11-27 | 2014-08-12 | Mediatek Singapore Pte. Ltd. | Method for performing power detection, and associated apparatus |
| KR101333824B1 (en) * | 2012-03-05 | 2013-11-29 | (주)에프씨아이 | Method for Coarse Frequency Synchronization in OFDM Receiver |
| CN103716261B (en) * | 2012-09-29 | 2017-04-19 | 电信科学技术研究院 | Frequency-offset estimation method and device |
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| CN1477889A (en) * | 2002-07-19 | 2004-02-25 | ӡ�����Ƽ��ɷ�����˾ | Frequency synchronization method for digital transmissio network and its equipment |
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| US6498822B1 (en) * | 1998-04-24 | 2002-12-24 | Nec Corporation | Frequency and timing synchronization circuit making use of a chirp signal |
| CN1477889A (en) * | 2002-07-19 | 2004-02-25 | ӡ�����Ƽ��ɷ�����˾ | Frequency synchronization method for digital transmissio network and its equipment |
| CN1482740A (en) * | 2002-09-13 | 2004-03-17 | 联发科技股份有限公司 | Phase-locked loop having phase detector error signal reshaping and method thereof |
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