CN1797379A - Method of data transmission by using mode of direct memory access - Google Patents
Method of data transmission by using mode of direct memory access Download PDFInfo
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- CN1797379A CN1797379A CNA2004101025356A CN200410102535A CN1797379A CN 1797379 A CN1797379 A CN 1797379A CN A2004101025356 A CNA2004101025356 A CN A2004101025356A CN 200410102535 A CN200410102535 A CN 200410102535A CN 1797379 A CN1797379 A CN 1797379A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a method for making data transmission in a direct memory accessing (DMA) mode. And the method configures a ring link list composed of items of two link lists which are interconnected through link address index, a processor loads items of a link list to a DMA controller, the DMA controller transmits data from source address to destination address according to data transmission quantity configured in channel transmission control and loads items of the other link list according to the link address index after the data transmission is completed, to make data transmission until all data is transmitted. The invention gives full play to the DMA efficiency, and makes the whole system able to operate at lower frequency and reduces system power consumption.
Description
Technical field
The present invention relates to the method that a kind of data transmit, relate in particular to a kind of direct memory access mode that adopts and carry out the method that data transmit.
Background technology
The development trend of portable terminal requires portable terminal to have longer stand-by time and littler volume.Longer stand-by time requires portable terminal to satisfy lower power consumption in the design of chip, and software is more simplified, and efficient is higher; Littler volume needs the employed chip of portable terminal microminiaturized more.
The CPU of portable terminal (Central Processing Unit, central processing unit) adopts DMA (DirectMemory Access, the direct memory visit) mode writes and read operation peripheral hardware, dma mode is a kind of high-speed data transmission operation, permission is the direct read data between peripheral hardware and internal memory, promptly not by CPU, also do not need CPU to intervene, whole data transfer operation carries out under the control of dma controller.CPU is except doing in the beginning of data transmission with when finishing some handle, and CPU can carry out other work in transmission course.Like this, in the most of the time, CPU and input and output all are in the state of parallel work-flow.DMA generally has a plurality of passages independent of each other, allows to carry out different access control, can carry out the DMA transmission of different content, and DMA can carry out data throughput with the speed of cpu clock, has the higher data throughput.
Method when adopting at present dma mode that the data in several in the address space internal memories are transmitted is: CPU at first sets the DMA transport property of this passage in the interrupt service routine of DMA passage or application program, comprise source address, destination address and control characteristic etc. in the transport property, DMA initiates channel transfer, transmit and finish back triggering interruption, in the interrupt service routine of this passage or application program, reset this DMA passage DMA transport property (comprising source address, destination address and control characteristic etc.) next time, and then start this passage.This mode needs end repeatedly and opens the DMA passage, CPU needs frequent intervening, wherein the end of DMA passage is controlled according to the transmission size of initial setting in the control characteristic by the hardware of DMA, the startup of DMA passage need realize by software under the control of CPU, frequent end and startup DMA passage can bring certain software overhead, in the too much processing time that takies CPU, cause the decline of system performance.
The transmission of adopting dma mode to carry out all is an one-way transmission at present, because peripheral hardware all is an energy while transceive data, therefore outer being located at just need take two DMA passages when carrying out the data double-way transmitting-receiving, a DMA passage is used for receiving the outer data that are set to internal memory, and another DMA passage is used for sending the data of internal memory to peripheral hardware.Two passages can be thought separately independently, reception of finishing separately or sending function.Because the resource of DMA passage is limited, therefore when DMA need connect a plurality of peripheral hardware, the not enough situation of channel resource just might appear.
Summary of the invention
The object of the present invention is to provide a kind of direct memory access mode that adopts to carry out the method that data transmit, solved the available technology adopting dma mode and carried out needing end repeatedly when data transmit and open the problem of DMA passage and adopt dma mode need take the problem of two DMA passages simultaneously during transceive data.
For addressing the above problem, the invention provides following technical scheme:
A kind of direct memory access mode that adopts is carried out the method that data transmit, and may further comprise the steps:
The annular chain meter that A, setting are made of two chained list list items, the content in the chained list list item comprise source address, destination address, link address index and channel transfer control, interlink by the link address index between two chained list list items;
B, processor are loaded into the direct memory access controller with a chained list list item in described two chained list list items;
C, direct memory access controller are according to the transmission data volume that disposes in the channel transfer control, data are sent to destination address from source address, and transmit in this data and to finish the back and load another chained list list item according to the link address index and carry out data and transmit, transmit end up to all data.
Described step C specifically may further comprise the steps:
C1, direct memory access controller are sent to destination address with data from source address according to the transmission data volume that disposes in the channel transfer control;
After C2, data transmit and finish, the direct memory access controller sends look-at-me to processor, and the result that the minute book secondary data transmits in the status register of passage, successfully then carries out step C3 if transmit, then finish transport process if transmit failure, and the notice upper layer software (applications);
C3, interrupt service routine are removed this look-at-me, and the direct memory access controller carries out the data transmission according to the content that the link address index in the chained list list item loads another chained list list item, transmits up to all data and finishes.
Described annular chain meter can be configured to one-way transmission pattern or bidirectional transmit-receive pattern.
In the one-way transmission pattern, when data be by internal memory when peripheral hardware transmits, processor transmits pairing linked list data for the last time and is set to sky in step C, data transmit to finish; When data be by peripheral hardware when internal memory transmits, in step C,, then trigger overtime interruption if the peripheral hardware register is not received the data of peripheral hardware in the time of setting, the peripheral hardware register cuts out peripheral hardware and direct memory access path after remaining data transmission is finished.
In the bidirectional transmit-receive pattern, if from outside be set to internal memory Data Receiving send FEFO than the data from the internal memory to the peripheral hardware, then with the exchange of the source address in the pairing chained list list item of Data Receiving direction and destination address, annular chain meter is configured to one-way transmission pattern from the internal memory to the peripheral hardware; If data from the internal memory to the peripheral hardware send than from outside be set to the Data Receiving FEFO of internal memory, then with source address and the destination address exchange of data receiver in pairing chained list list item, with annular chain meter be configured to from outside be set to the one-way transmission pattern of internal memory.
Because the present invention has adopted above technical scheme, so have following beneficial effect:
The present invention has disposed an annular chain meter and has finished the data of dma mode and transmit, by the different configurations of content to two chained list list items in the annular chain meter, can be at the one-way transmission or the bidirectional transmit-receive of an enterprising line data of DMA passage, under the one-way transmission pattern, can carry out continuous fast DMA transmits, under the bidirectional transmit-receive pattern, DMA can connect more peripheral hardware, thereby fully played the usefulness of DMA, the less processing time that has taken CPU, total system can be operated under the lower frequency, reduce the power consumption of system, can make portable terminal have longer stand-by time.
Description of drawings
Fig. 1 carries out the process flow diagram that data transmit for the present invention adopts dma mode;
Fig. 2 is carrying out the synoptic diagram of data when receiving continuously for the present invention;
Fig. 3 is an annular chain meter synoptic diagram of the present invention;
Fig. 4 is carrying out the synoptic diagram of data when sending continuously for the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
Figure 1 shows that the present invention adopts dma mode to carry out the process flow diagram that data transmit, its process is as follows:
One annular chain meter that is made of two chained list list items is set, and the content of chained list list item comprises source address, destination address, link address index and channel transfer control, interlinks by the link address index between two chained list list items; In dma controller, the transmission data volume according to configuration in the control of the channel transfer in the chained list list item is sent to destination address with data from source address with the load content of one of them chained list list item; Behind the Data Transfer Done, dma controller loads the content of another chained list list item according to the link address index in the chained list list item, carries out data and transmits, and the content in two chained list list items of CYCLIC LOADING transmits up to data and to finish.
Above-mentioned data transfer procedure can be configured to one-way transmission pattern or bidirectional transmit-receive pattern as required, DMA transmission under the one-way transmission pattern can be carried out unidirectional continuous transmission with data between peripheral hardware and internal memory, the DMA transmission under the bidirectional transmit-receive pattern can utilize single DMA passage to carry out the bidirectional transmit-receive of data.
DMA transmission course under the one-way transmission pattern can be divided into from outside be set to the DRP data reception process of internal memory and the data transmission procedure from the internal memory to the peripheral hardware, respectively it is illustrated below:
(1) from outside be set to the DRP data reception process of internal memory
Figure 2 shows that from outside be set to data stream and control stream the DRP data reception process of internal memory, wherein dotted line is represented control stream, solid line is represented data stream, control stream expression CPU is to the configuration information of peripheral hardware and DMA, DMA feeds back to the interrupting information of CPU etc., and data stream represents that DMA moves into internal memory to data from peripheral hardware.
Figure 3 shows that the annular chain meter that is disposed, in annular chain meter, the parameters of chained list list item 1 is set to: source address 1 is the address of the data register of peripheral hardware among Fig. 2, destination address 1 is the address of the RAM piece 1 among Fig. 2, what LLI1 pointed to is the memory address of chained list list item 2 in internal memory, channel transfer control 1 configuration be control word when this time transmitting, wherein set this moving data size, the moving data size that sets in the control word is exactly the size in RAM piece 1 space among Fig. 2.
The parameters of chained list list item 2 is set to: source address 2 is the address of the data register of peripheral hardware among Fig. 2, destination address 2 is the address of the RAM piece 2 among Fig. 2, what LLI2 pointed to is the memory address of chained list list item 1 in internal memory, channel transfer control 2 configurations be control word when this time transmitting, wherein set this moving data size, the moving data size that sets in the control word is exactly the size in RAM piece 2 spaces among Fig. 2.
After the annular chain meter configuration is finished, CPU with the load content in the chained list list item 1 in dma controller, a LLI (Linked List Item is arranged in the dma controller, the link address index) control register, LLI1 in the chained list list item 1 is loaded in the LLI control register, what pointed in the LLI control register this moment is the address of chained list list item 2, start this DMA passage and carry out moving of data, according to the destination address in the chained list list item 11, DMA arrives RAM piece 1 with data-moving, because the moving data size that the control word in the channel transfer control 1 sets just in time equals the size in RAM piece 1 space, therefore when having removed data designated, just fills DMA RAM piece 1.Dma controller sends a look-at-me to CPU, and reflects this result who moves in the status register of respective channel.
Interrupt service routine is removed the look-at-me that dma controller sends, dma controller according to the address of LLI1 chained list list item 2 pointed automatically with the load content in the chained list list item 2 in dma controller, according to the destination address 2 in the chained list list item 2 that is loaded, DMA arrives RAM piece 2 with data-moving, because the moving data size that the control word in the channel transfer control 2 sets just in time equals the size in RAM piece 2 spaces, therefore when having removed data designated, just fills DMA RAM piece 2.Dma controller sends a look-at-me to CPU, and reflects this result who moves in the status register of passage.Interrupt service routine is removed the look-at-me that dma controller sends, dma controller according to the address of LLI2 chained list list item 1 pointed automatically with the load content in the chained list list item 1 in dma controller and start DMA and move.
According to the content CYCLIC LOADING chained list list item 1 and the chained list list item 2 of annular chain meter, finish up to whole transmission of data.When not receiving data in the time that the data register of peripheral hardware is being set, then trigger overtime Interrupt Process, can finish data transmission remaining at present in the data register of peripheral hardware this moment, and close peripheral hardware and this DMA passage.
Can be by the size (generally can be set to identical size) that RAM1 and RAM2 reasonably are set, make from peripheral hardware to the process that one of them RAM piece is moved, can leave adequate time to CPU and handle data in another RAM piece, thereby when new data arrived, old data had been handled and have been over.
(2) data transmission procedure from the internal memory to the peripheral hardware
Figure 4 shows that from outside be set to data stream and control stream the DRP data reception process of internal memory, wherein dotted line is represented control stream, solid line is represented data stream, control stream expression CPU is to the configuration information of peripheral hardware and DMA, DMA feeds back to the interrupting information of CPU etc., and data stream represents that DMA moves peripheral hardware to data from internal memory.
Each parameter of the chained list list item 1 of annular chain meter shown in Figure 3 is set to: source address 1 is the address of internal memory RAM piece 1, destination address 1 is the address of the receive data register of peripheral hardware, what LLI1 pointed to is the address of chained list list item 2, channel transfer control 1 configuration be control word when this time transmitting, comprise size of data of moving etc., the moving data size that sets in the control word is exactly the size in RAM piece 1 space.Each parameter of chained list list item 2 is set to: source address 2 is the address of internal memory RAM piece 2, destination address 2 is the address of the receive data register of peripheral hardware, what LLI2 pointed to is the address of chained list list item 1, and the moving data size that sets in the channel transfer control 2 is exactly the size in RAM piece 2 spaces.
After the annular chain meter configuration was finished, in the DMA channel controller, moved data the data register of peripheral hardware from RAM piece 1 by the DMA passage with the load content in the chained list list item 1 for CPU, and the size of data of being moved equals the size in RAM piece 1 space.After data-moving in RAM piece 1 is finished, DMA can trigger an interruption, and whether reflection this time moves successful in the status register of passage, interrupt service routine is removed the look-at-me that dma controller sends, simultaneously dma controller according to the address of LLI1 chained list list item 2 pointed automatically with the load content in the chained list list item 2 in dma controller, content according to the chained list list item 2 that is loaded, in the data register of peripheral hardware, the size of data of being moved equals the size in RAM piece 2 spaces to the DMA passage with the data-moving in the RAM piece 2.When move finish after, can load the content of chained list list item 1 in the DMA channel controller again according to the address of LLI2 chained list list item 1 pointed automatically, beginning that the data in the RAM piece 1 are carried out DMA moves, in this manner, what data just can be gone round and begun again moves, thereby realizes that minimum CPU intervenes.
Because CPU is the transmit leg of data, the DMA passage just assists to carry out corresponding data-moving, therefore CPU clearly knows the core position at last blocks of data place, and the linked list data of correspondence was set to sky when the last DMA of CPU transmitted, and can finish whole DMA transmission.
DMA under the bidirectional transmit-receive pattern transmits the situation that the speed that is mainly used in the receiving-transmitting sides data is fixed rate, utilize a DMA passage that the data in two memory blocks are intersected read-write operation, adopt the annular chain meter mode that the control information of read operation and the write operation form with chained list is coupled together, after a chained list list item transmission in the annular chain meter finishes, dma controller can send a look-at-me to CPU, and preserves result's (success or failure) of this transmission in corresponding status register.Simultaneously, dma controller can load another chained list list item automatically according to the content in the current LLI control register from the space of RAM.Load the pairing chained list list item of read operation and write operation so repeatedly, can realize utilizing a DMA passage that the data in two memory blocks are intersected read-write operation.
Move with a DMA who is set to the data transmit-receive process of internal memory outward below and be example, the process that adopts single DMA passage to carry out the data double-way transmitting-receiving is described.
Each parameter of the chained list list item 1 of annular chain meter shown in Figure 3 is set to: source address 1 is the address of the data register of peripheral hardware, destination address 1 is the address of RAM piece 1, what LLI1 pointed to is the address of chained list list item 2, channel transfer control 1 configuration be control word when this time transmitting, wherein set the size of data of moving, the moving data size that sets in the control word just in time equals the size in RAM piece 1 space.
Each parameter of chained list list item 2 is set to: source address 2 is the address of RAM piece 2, destination address 2 is the address of the data register of peripheral hardware, what LLI2 pointed to is the address of chained list list item 1, channel transfer control 2 configurations be control word when this time transmitting, wherein set the size of data of moving, the moving data size that sets in the control word just in time equals the size in RAM piece 2 spaces.
After the annular chain meter configuration is finished, CPU with the load content in the chained list list item 1 in dma controller, start this DMA passage then and carry out moving of data, according to source address in the chained list list item 11 and destination address 1, DMA with the data-moving in the data register of peripheral hardware to RAM piece 1, because the moving data size that the control word in the channel transfer control 1 sets just in time equals the size in RAM piece 1 space, therefore when DMA has removed data designated, the space of RAM piece 1 just is filled, dma controller sends to CPU and reflects in a look-at-me and the status register at passage whether this result who moves is successful, if failure, end of transmission (EOT) is also notified upper layer software (applications), interrupt if success, interrupt service routine are removed this, dma controller loads chained list list item 2 automatically according to the chain table address among the LL1 simultaneously.
According to source address 2 in the chained list list item 2 that is loaded and destination address 2, the DMA passage is moved data the data register of peripheral hardware from RAM piece 2, the size of data of being moved just in time equals the size in RAM piece 2 spaces, dma controller sends this result who moves of reflection in a look-at-me and the status register at passage to CPU, interrupt service routine will be removed this look-at-me, withdraw from interruption.When DMA sent interruption, dma controller can be loaded in the controller of DMA once more according to the automatic just content of chained list list item 1 in the address of the chained list list item 1 among the LLI2, starts DMA and moves, and once more RAM piece 1 is carried out write operation.
Content CYCLIC LOADING chained list list item 1 and chained list list item 2 according to annular chain meter, finish up to either party data-moving that RAM piece 1 is carried out write operation and RAM piece 2 is carried out in the read operation, for transmission, because CPU is the initiator of data, what therefore CPU can be clear and definite knows when send last blocks of data, can indicate by an end mark position is set in internal memory, in interrupt service routine, all check the state of end mark position earlier at every turn, just can know whether that transmission will be through with.
For reception, can interrupt deciding according to this peripheral hardware receive time-out, promptly in the time that this peripheral hardware is set, peripheral port no longer includes new data and has arrived, and then thinks to receive to be through with, and finishes receiving operation by interrupt service routine.
A remaining side reconfigures annular chain meter this moment, and the bidirectional transmit-receive mode switch is become the one-way transmission pattern, is through with if send, and then can use that block RAM that was used to originally send as receiving RAM again, carries out data-moving.Be through with if receive, then can use that block RAM piece that was used to originally receive as sending RAM again, carry out data-moving.
If the one-way transmission pattern after the conversion is from the data transmission procedure of internal memory to peripheral hardware, then need each parameter of chained list list item 1 in the annular chain meter to be set to: source address 1 is the address of RAM piece 1 in the internal memory, destination address 1 is the address of the data register of peripheral hardware, what LLI1 pointed to is the address of chained list list item 2, channel transfer control 1 configuration be control word when this time transmitting, wherein set the size of data of moving, the moving data size that sets is exactly the size in RAM1 space, and the content of chained list list item 2 is constant.
If the one-way transmission pattern after the conversion is from the DRP data reception process of peripheral hardware to internal memory, then need each parameter of chained list list item 2 in the annular chain meter to be set to: source address 2 is the address of the receive data register of peripheral hardware, the address of RAM piece 2 in the destination address 2 expression internal memories, what LLI2 pointed to is the address of chained list list item 1, channel transfer control 2 configurations be control word when this time transmitting, wherein set the size of data of moving, set the size that the size of data of moving is exactly the RAM2 space, the content of chained list list item 1 is constant.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (10)
1, a kind of direct memory access mode that adopts is carried out the method that data transmit, and it is characterized in that may further comprise the steps:
The annular chain meter that A, setting are made of two chained list list items, the content in the chained list list item comprise source address, destination address, link address index and channel transfer control, interlink by the link address index between two chained list list items;
B, processor are loaded into the direct memory access controller with a chained list list item in described two chained list list items;
C, direct memory access controller are according to the transmission data volume that disposes in the channel transfer control, data are sent to destination address from source address, and transmit in this data and to finish the back and load another chained list list item according to the link address index and carry out data and transmit, transmit end up to all data.
2, employing direct memory access mode according to claim 1 is carried out the method that data transmit, and it is characterized in that: described step C specifically may further comprise the steps:
C1, direct memory access controller are sent to destination address with data from source address according to the transmission data volume that disposes in the channel transfer control;
After C2, data transmit and finish, the direct memory access controller sends look-at-me to processor, and the result that the minute book secondary data transmits in the status register of passage, successfully then carries out step C3 if transmit, then finish transport process if transmit failure, and the notice upper layer software (applications);
C3, interrupt service routine are removed this look-at-me, and the direct memory access controller carries out the data transmission according to the content that the link address index in the chained list list item loads another chained list list item, transmits up to all data and finishes.
3, employing direct memory access mode according to claim 1 is carried out the method that data transmit, and it is characterized in that: described annular chain meter can be configured to the one-way transmission pattern.
4, employing direct memory access mode according to claim 3 is carried out the method that data transmit, it is characterized in that: in described one-way transmission pattern, when data be by internal memory when peripheral hardware transmits, processor transmits pairing linked list data for the last time and is set to sky in described step C, and data transmit and finish.
5, employing direct memory access mode according to claim 3 is carried out the method that data transmit, it is characterized in that: in described one-way transmission pattern, when data be by peripheral hardware when internal memory transmits, in described step C, in the time of setting, do not receive the data of peripheral hardware as if the peripheral hardware register, then trigger overtime interruption, the peripheral hardware register cuts out peripheral hardware and direct memory access path after remaining data transmission is finished.
6, employing direct memory access mode according to claim 1 is carried out the method that data transmit, and it is characterized in that: described annular chain meter can be configured to the bidirectional transmit-receive pattern.
7, employing direct memory access mode according to claim 6 is carried out the method that data transmit, it is characterized in that: in described bidirectional transmit-receive pattern, if from outside be set to internal memory Data Receiving send FEFO than the data from the internal memory to the peripheral hardware, then with the exchange of the source address in the pairing chained list list item of Data Receiving direction and destination address, annular chain meter is configured to one-way transmission pattern from the internal memory to the peripheral hardware.
8, employing direct memory access mode according to claim 7 is carried out the method that data transmit, and it is characterized in that: if the peripheral hardware register is not received the data of peripheral hardware in the time of setting, then from outside be set to internal memory Data Receiving finish.
9, employing direct memory access mode according to claim 6 is carried out the method that data transmit, it is characterized in that: in described bidirectional transmit-receive pattern, if data from the internal memory to the peripheral hardware send than from outside be set to the Data Receiving FEFO of internal memory, then with source address and the destination address exchange of data receiver in pairing chained list list item, with annular chain meter be configured to from outside be set to the one-way transmission pattern of internal memory.
10, employing direct memory access mode according to claim 9 is carried out the method that data transmit, and it is characterized in that: judge according to the state of the end mark position of setting in internal memory whether the data transmission from the internal memory to the peripheral hardware finishes.
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| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
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| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN102314400B (en) * | 2011-09-27 | 2014-12-24 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN103309841A (en) * | 2012-03-16 | 2013-09-18 | 英飞凌科技股份有限公司 | Method and system for timeout monitoring |
| US9727400B2 (en) | 2012-03-16 | 2017-08-08 | Infineon Technologies Ag | Method and system for timeout monitoring |
| US10191795B2 (en) | 2012-03-16 | 2019-01-29 | Infineon Technologies Ag | Method and system for timeout monitoring |
| CN105243026A (en) * | 2014-05-30 | 2016-01-13 | 展讯通信（上海）有限公司 | Memory access control method and apparatus for terminal device |
| CN105243026B (en) * | 2014-05-30 | 2018-06-22 | 展讯通信（上海）有限公司 | The memory access control method and device of terminal device |
| CN106126442A (en) * | 2016-06-17 | 2016-11-16 | 北京京坤倍益科技发展有限公司 | A kind of data store organisation and remote sensing satellite data-storage system |
| CN106339338A (en) * | 2016-08-31 | 2017-01-18 | 天津国芯科技有限公司 | Data transmission method and device capable of improving system performance |
| CN106339338B (en) * | 2016-08-31 | 2019-02-12 | 天津国芯科技有限公司 | A kind of data transmission method and device that system performance can be improved |
| CN108334464A (en) * | 2017-01-18 | 2018-07-27 | 恩智浦美国有限公司 | Multichannel DMA system with the command queue's structure for supporting three DMA modes |
| CN107769901A (en) * | 2017-10-19 | 2018-03-06 | 中国科学院寒区旱区环境与工程研究所 | A kind of method and apparatus of field inspection data transfer |
| CN107665409A (en) * | 2017-11-01 | 2018-02-06 | 飞友科技有限公司 | A kind of front and rear sequence flight structure and fault-tolerant method |
| CN107665409B (en) * | 2017-11-01 | 2021-02-26 | 飞友科技有限公司 | Method for constructing and fault-tolerant front-and-back flight |
| CN111258937A (en) * | 2020-01-23 | 2020-06-09 | 烽火通信科技股份有限公司 | Transmission method and system of ring type linked list DMA |
| CN114679381A (en) * | 2022-03-24 | 2022-06-28 | 芯河半导体科技(无锡)有限公司 | Rapid table-flushing method based on hardware DMA |
| CN114679381B (en) * | 2022-03-24 | 2023-11-24 | 芯河半导体科技(无锡)有限公司 | Quick table brushing method based on hardware DMA |
| CN115658351A (en) * | 2022-12-27 | 2023-01-31 | 北京象帝先计算技术有限公司 | 2D copying method, device, electronic equipment and computer readable storage medium |
| CN116775524A (en) * | 2023-06-19 | 2023-09-19 | 无锡摩芯半导体有限公司 | Lli dynamic writing method of dma linked list mode |
| CN116775524B (en) * | 2023-06-19 | 2024-02-02 | 无锡摩芯半导体有限公司 | Lli dynamic writing method of dma linked list mode |
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