CN1790888A - Inversion system and control method - Google Patents
Inversion system and control method Download PDFInfo
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- CN1790888A CN1790888A CNA2005100480777A CN200510048077A CN1790888A CN 1790888 A CN1790888 A CN 1790888A CN A2005100480777 A CNA2005100480777 A CN A2005100480777A CN 200510048077 A CN200510048077 A CN 200510048077A CN 1790888 A CN1790888 A CN 1790888A
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Abstract
The invention relates to a inversion system, which comprises: an electric power conversion circuit with a power conversion and a power filter circuit to supply dc-ac convert path, and a control system to realize control algorithm, information management and exchange and control other parts. Wherein, the control system comprises: a central-control module, multiplex data detection and collection module, a hierarchy communication management module, multiplex power drive module, and a hierarchy alarm management module. This invention ensures the amplification and narrow-impulse limit, can feedback the alarm information accuracy in time, has strong communication function, and the software has strong real-time and specialty.
Description
Technical field
The invention belongs to power electronics and power conversion system and device technique field, particularly a kind of inversion system and control method.
Background technology
Along with new electronic device, electromagnetic material, converter technique, control theory and the new chip and the continuous appearance of software, power electronics and power converter technology obtain significant progress, and the Related product performance is significantly increased.
In recent years, along with the construction of second generation energy resource system, actively applied in the world with heat, electricity, clod cogeneration system that the micro fuel engine power generation unit is formed.Inversion system (direct current is converted to alternating current) has obtained extensive concern as micro fuel engine power generation system and the assurance of power supply with the final output quality of power supply of inversion system.
In the three-phase four-wire system inversion electric power system that provides at present, generally adopt to add the scheme of transformer, this systems bulky, complex process, efficient are lower, and there is leakage inductance in transformer, so the symmetry of output voltage can't be protected; Three half-bridge structures, when the serious imbalance of load, the electric capacity that connects central point bears big electric current, has increased the possibility that system breaks down.
Summary of the invention
The present invention is directed to the problem that exists in the three-phase four-wire system inversion electric power system, a kind of inversion system and control method are provided.
The present invention comprises inversion system and realizes the control method of invert function.Described inversion system is made of power transformation circuit and control system.Fig. 1 is a system configuration schematic diagram of the present invention.Power transformation circuit provides electric power by the passage of direct current to exchange conversion, and it comprises power inversion circuit and power filter circuit; Control system is used to realize control algolithm, information management and exchange, and to switching device in the power transformation circuit (IGBT) enforcement control, to realize three-phase and four-line inversion output, it includes central control module, multichannel data detection and acquisition module, classification communication management module, multichannel power driver module and classifying alarm administration module.Power transformation circuit comprises power inversion circuit and power filter circuit.
1, power inversion circuit
Power inversion circuit adopts the three-phase four-arm structure, and Fig. 2 is a power inversion circuit.It among Fig. 2 impressed DC voltage, circuit is made of eight switching devices (IGBT), eight fly-wheel diodes and four noninductive electric capacity, per two switching devices (IGBT) of cross-over connection and diode constitute a unit (i.e. brachium pontis) by the realization of a biswitch device (IGBT) module between PN, the surge voltage when inserting noninductive electric capacity with the shutoff of absorption device on module.Circuit is made of four biswitch devices (IGBT) module (i.e. four brachium pontis) altogether.The sort circuit structure is on traditional three-phase three brachium pontis architecture basics, increases by the 4th brachium pontis, with direct control centre point voltage, and produces neutral line current inflow load.A controllable degrees of freedom of this increase makes three-phase four-leg inverter can produce three independent voltages, thereby realizes decoupling zero control, keeps the symmetry of three-phase output phase voltage.This particular structure provides the foundation on hardware based on the independent fuzzy control scheme of decoupling zero control thought for realizing.
2, power filter circuit
The power filter circuit adopts three symmetrical filtering, and filter circuit is connected across the alternate of each phase.Fig. 3 is the power filter circuit, and circuit adopts inductance, resistance and electric capacity to form.Fig. 3 (a) is the three-phase filter circuit, and the three-phase circuit structure is in full accord.Fig. 3 (b) is that a phase filter circuit is illustrated, because typical second-order filter circuit only is made of electric capacity and inductance, oscillatory occurences can occur near cut-off frequency, and this is should be avoided on the engineering as far as possible.In order to weaken the amplitude that vibration occurs, in filter circuit, add resistance, increased the damping of system, change system dynamic characteristic, system transter becomes like this
Wherein: U
OBe output voltage; U
IBe input voltage; R, L, C are respectively resistance, inductance, capacitance; S is the Laplace transformation operator.
This circuit structure can effectively keep first-harmonic composition and filtering high order harmonic component.
Control system
Control system is made of multichannel data detection and acquisition module, central control module, classification communication management module, multichannel power driver module and classifying alarm administration module, and Fig. 4 is the circuit theory diagrams of control system.IC101 is a central processing unit, in have memory space to be used for stored program and data; IC201, IC202, IC203, IC204, IC205 are for realizing the voltage matches chip of 3.3V to 5V; IC102 is used for system reset; IC206 is the dedicated serial communication chip; IC207 is a CAN bus communication chip.
Control system is a core with IC101, has expanded memory circuit, voltage matches circuit, system reset circuit, serial communication circuit, CAN bus communication circuit, warning passage, has driven passage, data acquisition channel, I/O passage, crystal oscillating circuit.Wherein the D0-D15 of (1) IC101 provides data signal interfaces (data channel is to output to memory cell by 1B1-1B8, the 2B1-2B8 of IC201 again from 1A1-1A8,2A1-2A8 that the D0-D15 of IC101 is connected to IC201 in turn), and this data channel provides data message for memory cell; (2) A0-A15 of IC101 provides address (the address transfer passage is to output to memory cell by 1B1-1B8, the 2B1-2B8 of IC204 again from 1A1-1A8,2A1-2A8 that the A0-A15 of IC101 is connected to IC204 in turn), gives memory cell; (3) W/R of IC101 connects 1DIR and the 2DIR of IC201, in order to the data transfer direction of control store unit; (4) DS of IC101, RD, IS, PS, WE, IOPC2 form the control signal interface and link to each other (passage is that 1A7,1A8, the 2A1-2A4 that DS, RD, IS, PS, WE, the IOPC2 from IC101 is connected to IC205 in turn outputs to memory cell by 1B7,1B8, the 2B1-2B4 of IC205 again) with memory cell, and the chip selection signal of each chip of memory cell is provided; (5) RS of IC101, WDI link to each other with reset circuit, and system reset function (passage is that the 2B7 of the 2A3, the IC205 that are connected to IC203 in turn of RS, the WDI from IC101 is connected to 11 pin of IC103, the WDI output of IC102 by the 2A7 of 2B3, the IC205 of IC203 again) is provided; (6) SCITXD of IC101 provides the data-interface of serial communication with SCIRXD and has linked to each other (passage is that the 2A6 of the 2A6, the IC203 that are connected to IC205 in turn of SCITXD, the SCIRXD from IC101 outputs to terminal by T1OUT, the R1IN of IC206 at last by T1IN, the R1OUT that the 2B6 of 2B6, the IC203 of IC205 is connected to IC206 again) with the dedicated serial communication chip; (7) CANTX of IC101, CANRX provide the data-interface of CAN bus communication and have linked to each other (passage is that the 2A7 of 2A8, the IC203 of CANTX, the corresponding IC205 of being connected to of CANRX from IC101 outputs to terminal by CANL, the CANH of IC207 at last by TXD, the RXD that the 2B7 of 2B8, the IC203 of IC205 is connected to IC207 again) with special-purpose CAN communication chip; (8) PDPINTA of IC101 the introducing interface of danger warning is provided and link to each other with driver element (passage be the PDPINTA from IC101 be connected to IC203 1A2 again by the 1B2 output of IC203); (9) PWM1-PWM8 of IC101 provides the signal of driving power device and has linked to each other (passage is that the 1A1-1A8 that the PWM1-PWM8 from IC101 is connected to IC202 in turn outputs to driver element by the 1B1-1B8 of IC202 again) with driver element; (10) ADCIN00-ADCIN09 of IC101 links to each other with circuit among Fig. 5, in order to gather each physical quantity; (11) IOPA3 of IC101, IOPA4, IOPE3-IOPE6, IOPFO, IOPF1, IOPF5, IOPF6 provide special I/O communication interface and link to each other (passage is the 1A2-1A5 of the 1A3, the 1A4 that are connected to IC203 in turn of IOPA3, IOPA4, IOPE3-IOPE6, IOPFO, IOPF1, IOPF5, the IOPF6 from IC101,1A6-1A8,2A1, IC205, the 1B2-1B5 of the 1B3 of IC203,1B4,1B6-1B8,2B1, IC205) with special I/O line; (12) TCK of IC101, TDO, TDI, TMS, TRST, EMU1, EMU0 link to each other with socket, are used to connect simulator, can be used for debugging routine and program is write the flash memory of IC101; (13) PLLF2 of IC101, PLLF, XTAL1, XTAL2 link to each other with crystal oscillating circuit, are used to provide the clock reference of system; (14) VSSO of IC101 links to each other with the ground wire of system with VSS; (15) VDDO of IC101 links to each other with 3.3V with VDD, and the working power of IC101 is provided.
1, multichannel detects and acquisition module
The multichannel detection module is gathered multichannel analog signals, comprises three-phase voltage, three-phase current, neutral line current and DC bus-bar voltage.The processing mode that module adopts software and hardware to combine is handled each road feedback signal, and Fig. 5 is channel hardware circuit of module.Multiplexer channel is some single channel passages formations in parallel.Acquired signal comes from transducer, carry out analog by the level Four operational amplifier, with transducer output be converted into Fig. 4 in the 0-3.3V signal that is complementary of IC101, the ADCIN00-ADCIN09 that passes to IC101 (wherein has two passages as reservation, the ADCIN of IC101 is the input of the built-in A/D converter of central processing unit), conversion forms digital signal through A/D, adopts the mode of software processes to guarantee the true and reliable of acquired signal again.Fig. 6 handles flow chart for measuring, and its workflow is as follows:
(1) reads each road sampled signal;
(2) call number filtering subprogram;
(3) call the numerical computations subprogram;
(4) signal processing finishes.
Wherein digital filtering algorithm is by formula Y
(n)=0.6Y
(n-1)+ 0.208X
(n)+ 0.192X
(n-1)Realize, wherein X
(n)Be input now, X
(n-1)Be the input in a last moment, Y
(n)Be the output valve that calculates now, Y
(n-1)Be the output valve in a last moment, 0.6,0.208 and 0.192 is coefficient.The digital filtering subprogram has realized this algorithm, its workflow following (Fig. 7 is the digital filter program block diagram):
A) beginning;
B) determine the address dma of corresponding history table according to asking project;
C) read current input value X (n) to the dma-1 unit;
D) X (n-1) is carried out product (multiply by coefficient of correspondence in the formula), add up (so that realizing add operation in the formula), data move (depositing X (n-1) in the dma+1 unit);
E) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
F) X (n) is carried out product, add up, data move (depositing X (n) in the dma unit as the X (n-1) that calculates next time);
G) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
H) Y (n-1) carries out product, adds up, data move;
I) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
J) Y (n) is deposited in the dma-2 unit as Y (n-1) next time;
K) output Y (n);
L) return.
The workflow of numerical computations subprogram following (Fig. 8 is a numerical computations subprogram block diagram):
A) beginning;
B) determine the first address of this item record one-period tables of data according to asking project, and determine address offset amount A in the table in the position of current sinusoidal period according to current time (having the cycle rate counter count value to determine);
C) determine address offset amount in the table;
D) XZ=XZ-XA (XZ is an one-period numerical value summation, and A is a current count value);
E) read in currency and deposit register XA in;
f)XZ＝XZ+XA；
G) X=XZ*K*1.11 (COEFFICIENT K=1/96);
H) return.
2, central control module
Central control module is mainly used in the realization of control logic.The present invention is a core with IC101 among Fig. 4, expansion crystal oscillating circuit (among Fig. 4 RS101 etc.), outer watchdog circuit (among Fig. 4 IC102 etc.), outer extension memory (memory address line is provided by 1B1-8, the 2B1-8 of IC204 among Fig. 4, and data wire is provided by 1B1-8,2B1-8 among the IC201 among Fig. 4) and multichannel level translator (IC201-IC205 among Fig. 4) formation central control module hardware circuit.
Central control module software is not only realized control logic, and information is managed, and is mainly judged, moves and shut down control by service conditions to constitute.
Service conditions judge software respectively by initialize routine, self-check program, accept power-on command and DC bus-bar voltage normal judge constitute, wherein CCU is the last machine that is, Fig. 9 is a service conditions determining program block diagram.
Moving and shut down control program is called and is constituted by startup and shutdown judgement, the control logic of powering, invertor operation control, communication.Figure 10 is for operation and shut down the control program block diagram, and its workflow is as follows:
(1) waits for regularly interruption;
(2) timing arrives, and enters interrupt handling routine, each road feedback signal is measured, and judgment task state whether normal (calling the warning subprogram);
(3) after interruption is returned, call the invertor operation control program, make inverter work;
(4) the inverter work state information is transmitted by communication program;
(5) judge whether to start for the first time? if start for the first time, count, change the 7th step (guarantee to export stable back and give self system's power supply) over to; If not starting for the first time, self system's power supply realizes, changes next step over to;
(6) judge whether externally power supply and execution corresponding operating;
(7) judged whether halt command? no, return the first step; Have, change next step over to;
(8) shut down;
(9) work state information is transmitted by communication program;
(10) forward the starting position of service conditions determining program to.
The invertor operation control program is moved and is shut down control program with the subprogram form and called in the invention, in order to realize the expection control logic.
By to the three-phase four-arm Analysis of Topological Structure, can reach a conclusion: as long as the control of the 4th brachium pontis is appropriate, can reach the effect of decoupling zero control fully by three-phase independent regulation scheme, the control of the 4th brachium pontis is the key that realizes decoupling zero.Three-phase control is owing to the control logic basically identical, so only provide a facies-controlled program description.Figure 11 is a phase control program block diagram, and its workflow is as follows:
(1) carries out cycle count (standard sine wave is separated into 96 points and exists in the numerical table, and the purpose of cycle count is to read the value of corresponding sine wave in the table as the control reference with count value);
(2) carry out the adjusted value of PID regulating and controlling according to control is given with value of feedback;
(3) regulated value is suitably handled as correction factor;
(4) in sine table, find sine value as the control reference with count value as pointer;
(5) sine value be multiply by the departure correction factor that obtains in the 3rd step, obtain the working control amount.
Because central processing unit is supported the sinusoidal pulse width modulation algorithm on hardware, promptly as long as deposit the three phase sine controlled quentity controlled variable in corresponding comparand register, central processing unit PWM interface hardware can generate the control logic of driving switch device automatically, so, and insert driver module and can realize predetermined control as long as the PWM1-6 of IC101 among Fig. 4 is exported through level match.
The 4th brachium pontis is regulated with the three-phase adjusting essential distinction, is the key that realizes decoupling zero control, and Figure 12 is the 4th brachium pontis control program block diagram, and its workflow is as follows:
(1) reads neutral line current;
(2) neutral line current is carried out Filtering Processing (electric current be multiply by first order inertial loop) and deposit feedback register FK in, and, carry out PID and regulate, pass through amplitude limiting processing again as controlled quentity controlled variable KZ with 0 as given controlled target (GD is given register) as feedback;
(3) controlled quentity controlled variable is deposited in the 4th brachium pontis comparand register.
Because central processing unit is supported pulse width modulation algorithm on hardware,, and insert driver module and can realize predetermined control so the PWM7,8 that needs only IC101 among Fig. 4 exports the process level match.
It is similar that the control of B, C two-phase and A control mutually, and the pointer of just reading sine table will embody three-phase mutual deviation 120 and spend (being that B phase pointer is that count value+32, C phase pointer are count value+64).
Whole invertor operation control program is carried out A, B, C phase and the 4th brachium pontis control program in proper order, and last counter adds 1, provides the counting pointer for carrying out next step control, and returns main program.
3, multichannel power driver module
The multichannel power driver module is based on the special-purpose drive plate (SKHI23/17) of outsourcing Xi Menkang company, it (is that drive signal is passed to power circuit by control system that module adopts the information bidirectional flow pattern, danger alarm signal is passed to control system by power circuit), increased the burst pulse limitation function.The control logic of the 1B1-8 of IC202 output among Fig. 4 after the restriction of programmable array (CPLD) realization burst pulse, inserts 4 special-purpose drive plates (drive plate drives two switching device IGBT of a brachium pontis), realizes the control to switching device.The burst pulse limitation function is implanted among the CPLD with the programming form, and the burst pulse drive signal that the filtering time is too short is eliminated invalid devices switch action.Figure 13 is a burst pulse limiting program block diagram, and its workflow is as follows:
(1) counter O reset, the flag bit zero clearing;
(2) do you judge incoming level? high level enters next step; Low level changed for the 5th step over to;
(3) do you judge that count value is not to the burst pulse limits value? be that the output high level also changed for second step over to; Not to change next step over to;
(4) counter adds 1, and output low level changed for second step over to;
Is (5) the judgement symbol position 1? be to change for the 7th step over to; Not to change next step over to;
(6) do you judge that count value is not to the burst pulse limits value? be mark position 1; Not counter O reset;
(7) do you judge that count value is zero? be flag bit zero clearing and output low level; Not that counter subtracts 1 and export high level;
(8) changed for second step over to.
4, classifying alarm administration module
The classifying alarm administration module adopts three grades of designs of reporting to the police.The superlative degree is a danger warning, and the CE end from IGBT shows that switching device faces the damage edge, and system is in the hole.Alarm signal is imported the 1B2 of IC203 among Fig. 4 into by the drive plate backward channel, and then imports the PDPINTA of IC101 among Fig. 4 into, causes the hardware interrupts request.Drive plate obtains blocking driving pulse automatically after the alarm signal, but along with device turn-offs, the disappearance of alarm signal, blockade may be opened by the driving pulse of central processing unit, think the thorough elimination that guarantees the system failure, be necessary to carry out shutdown,, eliminate fault by artificial mode check system by the software of central processing unit.The interrupt routine block diagram that Figure 14 causes for danger warning, its workflow is as follows:
(1) system closedown (closing all drivings) to inverter;
(2) disconnect all relays;
(3) by working state of system before communication program transmission warning message and the shutdown;
Does (4) inquiry have or not further communication request? have, will send for information about;
(5) returned for the 4th step.
It is to form on each physical quantity basis of analytical system that I and II is reported to the police, and one-level is reported to the police and shown that system is in the failure operation state, should notify related system to shut down processing.Operation irregularity appears in secondary warning expression system, and judges the unusual duration, if the duration is longer, illustrative system is irrecoverable unusually, upgrades to one-level and reports to the police.I and II is reported to the police and is appeared at (promptly in operation and shutdown control program) among Figure 10 with the subprogram form.Figure 15 is an I and II warning subprogram block diagram, and its workflow is as follows:
(1) will gather three-phase current and ask for maximum (IAn, IBn, ICn are respectively the three-phase electricity flow valuve);
(2) transfer three-phase current warning subprogram;
(3) input neutral line current (IO is leading current value);
(4) the alert subprogram of zeroing report from a liner;
(5) three-phase voltage of gathering is asked for maximum and minimum value (UAN, UBN, UCN are respectively the three-phase voltage value);
(6) call the voltage alarm subprogram;
(7) call DC bus-bar voltage warning subprogram (UD is a d-c bus voltage value).
Figure 16, Figure 17, Figure 18, Figure 19 are respectively electric current warning subprogram, voltage alarm subprogram, the workflow block diagram that DC bus-bar voltage warning subprogram and one-level alarm software interrupt.
M1 is used to judge current type among Figure 16, and explanation judges that electric current is a three-phase current during M1=0, and corresponding one-level alarm setting value is A1=310A, and the secondary alarm setting value is A2=260A; Explanation judges that electric current is a neutral line current during M1=1, and corresponding one-level alarm setting value is A1=50A, and the secondary alarm setting value is A2=30A.When the one-level warning occurring, cause software interrupt; When secondary occurring and reporting to the police, calculate the secondary continuous occurrence number of reporting to the police, report to the police if number of times, then upgrades to one-level greater than 96 by counter TABJ.
Umax, Umin are respectively maximum, the minimum value of three-phase output voltage among Figure 17.When output voltage exceeds the 208V-254V scope, be defined as one-level and report to the police; Report to the police when output voltage exceeds the 220V-245V scope but do not reach one-level, be defined as secondary and report to the police.When the one-level warning occurring, cause software interrupt; When secondary occurring and reporting to the police, calculate the secondary continuous occurrence number of reporting to the police, report to the police if number of times, then upgrades to one-level greater than 96 by counter TUBJ.During the inversion system initial start-up, output voltage exceeds the 208V-254V scope and is considered to normally, but can not surpass a specified time (TQC counter realized initial start-up voltage overflow timing).If surpass the regulation time limit, cause one-level and report to the police.
UD is a DC bus-bar voltage among Figure 18.When voltage exceeds the 648V-792V scope, be defined as one-level and report to the police; Report to the police when voltage exceeds the 684V-756V scope but do not reach one-level, be defined as secondary and report to the police.When the one-level warning occurring, cause software interrupt; When secondary occurring and reporting to the police, calculate the secondary continuous occurrence number of reporting to the police, report to the police if number of times, then upgrades to one-level greater than 5000 by counter TUDBJ.Fluctuation occurs for initial start-up voltage, be not considered to normal but reach the one-level high alarm setting.
The function that the one-level warning is interrupted among Figure 19 is that reporting to the police appears in the notice host computer, and uploads data by calling communication program.The configuration state position is that the one-level warning appears in the notification communication program; Put alarm bit set and make communication program judge warning reason, and related data is uploaded host computer.
5, classification communication management module
Classification communication management module requires to carry out communication by the data communication passage of different priorities according to the information real-time.Each interchannel is a relation in parallel.Communication channel is divided three classes: (1) special I/O mouth, its hardware circuit passage for the IOPF0,1,5 of IC101 shown in Fig. 4,6 with IOPE3,4,5,6 be connected in turn IC205 1A2,3,4,5 and 1A6,7,8, the 2A1 of IC203 again by the 1B2,3,4 of IC205,5 and 1B6,7,8, the 2B1 of IC203 be connected to terminal; (2) dedicated serial communication interface, its hardware circuit passage connect 2A6, the IC203 of IC205 for SCITXD, the SCIRXD of IC101 among Fig. 4 is corresponding 2A6 outputs to terminal by T1OUT, the R1IN of IC206 at last by T1IN, the R1OUT that the 2B6 of 2B6, the IC203 of IC205 is connected to IC206 again; (3) CAN bus interface, its hardware circuit passage connect 2A8, the IC203 of IC205 for CANTX, the CANRX of the IC101 of Fig. 4 2A7 is connected to terminal by CANL, the CANH of IC207 at last by TXD, the RXD that the 2B7 of 2B8, the IC203 of IC205 connects IC207 again.
Bitcom realizes that in central processing unit Figure 20 is the communication program block diagram, and its workflow is as follows:
(1) reads the host computer input information;
(2) do you judge that dangerous warning is not? have, by special I/O police that transmits messages;
(3) do you judge have one-level to report to the police not? no, changed for the 5th step over to;
(4) physical quantity of alarm code and initiation warning is pressed the serial protocol packing, and send by the dedicated serial passage;
(5) each physical quantity is pressed the packing of CAN bus protocol, and send by the CAN bus;
(6) do you judge have further communication need not? have, on request information is sent by the CAN bus;
(7) return.
Use inversion system of the present invention, its control method comprises step:
Whether step 2, check system be normal;
Step 3, central control module are waited for the power transformation circuit work order;
Step 4, receive and wait for after the order detecting and enter stable with acquisition module input DC bus-bar voltage by multichannel data;
Step 5, central control module are waited for the arrival of regularly interrupting;
Do step 6, classifying alarm administration module judge whether each physical quantity that detects normal? undesired, enter the operation of reporting to the police;
Step 7, detection information and the controlled target control power transformation circuit gathered according to multichannel data detection and acquisition module move;
Step 8, classification communication management module and other system and upper machine communication;
Step 9, central control module decision are according to circumstances powered to self unit with to external user;
Step 10, central control module inquiry halt command do not have halt command then to return step 5;
Step 11, there is halt command then to carry out stopping process, and detects and the determining program head before returning operation.
The present invention has guaranteed the amplification and the burst pulse restriction of drive signal, and timely, the accurate feedback of warning message; And have powerful communication function, adopt special I/O mouth, the rating information interactive mode of dedicated serial communication interface and general CAN bus has guaranteed the unit independent operating of system, again can with the host computer remote monitoring; Native system and device software adopt and work out based on the special-purpose assembler language of DSP320F240 family chip, have powerful real-time and specificity.
Description of drawings:
Fig. 1 system configuration schematic diagram of the present invention;
Power inversion circuit in Fig. 2 power transformation circuit of the present invention;
Fig. 3 (a) is a phase filter circuit for three-phase filter circuit (b);
The circuit theory diagrams of Fig. 4 control system;
Channel hardware circuit of Fig. 5 multi pass acquisition module;
Fig. 6 measures the processing flow chart;
Fig. 7 digital filtering subprogram block diagram;
Fig. 8 numerical computations subprogram block diagram;
Before moving, Fig. 9 detects and the determining program block diagram
Figure 10 operation and shutdown control program block diagram;
Figure 11 inverter one-phase control flow chart;
Figure 12 inverter the 4th brachium pontis control program block diagram;
Figure 13 burst pulse limiting program block diagram;
Figure 14 danger warning interrupt handling routine block diagram;
Figure 15 I and II alert program block diagram;
Figure 16 electric current warning subprogram block diagram;
Figure 17 voltage alarm subprogram block diagram;
Figure 18 DC bus-bar voltage warning subprogram;
Figure 19 one-level alarm software interrupts;
Figure 20 communication program block diagram.
Embodiment:
Embodiment: micro fuel engine power generation unit inversion system
Micro fuel engine sends electric energy and handles and can form direct current, and direct current need carry out inversion and form the three-phase four-wire system alternating current and offer the user.
A kind of inverse control system of the present invention and method can be finished this function well at this requirement.System is made of power transformation circuit and control system.Fig. 1 provides system of systems schematic diagram of the present invention.Power transformation circuit is made of power inversion circuit and power filter circuit; It includes central control module, multichannel data detection and acquisition module, classification communication module, multichannel power driver module and classifying alarm module control system.
One, power transformation circuit
1, power inversion circuit
Power inversion circuit adopts the three-phase four-arm structure, and Fig. 2 has provided power inversion circuit.Circuit is made of eight IGBT, eight fly-wheel diodes and four noninductive electric capacity, and per two IGBT of cross-over connection and diode constitute a unit (i.e. brachium pontis) by a two IGBT modules realization between PN.Circuit is made of four IGBT modules (i.e. four brachium pontis) altogether, and the IGBT module adopts German Xi Menkang company product, and specification is 500A/1700V; It is the noninductive electric capacity of 1uF/1200V that four electric capacity adopt specification.
2, power filter circuit
The power filter circuit adopts three symmetrical filtered version, is made up of inductance, resistance and electric capacity, and Fig. 3 has provided circuit structure.It is the cement structures resistance of 1 ohm/100W that resistance adopts specification; It is the polarity free capacitor of 33uF/900V that electric capacity adopts specification; It is the 1mH iron-core inductance that inductance adopts specification, the permalloy material that adopts unshakable in one's determination, and magnetic circuit has air gap to prevent magnetic saturation.
Two, control system
Control system is made of multichannel data detection and acquisition module, central control module, classification communication module, multichannel power driver module and classifying alarm module, and Fig. 4 has provided the hardware circuit of control system.IC101 is a central processing unit, the TMS320LF2407 chip that adopts American TI Company to produce, in have memory space to be used for stored program and data; IC201-IC205 adopts the SN74LVC164245 chip for realizing the voltage matches chip of 3.3V to 5V; System reset circuit comprises that IC102, IC103, resistance and electric capacity constitute, and IC102 adopts the MAX6374 chip, and IC103 adopts 4093 NAND gate chips; IC206 is the dedicated serial communication chip, adopts the MAX232 chip; IC207 is a CAN bus communication chip, adopts the PCA82C250T chip.
1, multichannel detects and acquisition module
The multichannel detection module is gathered multichannel analog signals, comprises three-phase voltage, three-phase current, neutral line current and DC bus-bar voltage.The processing mode that module adopts software and hardware to combine is handled each road feedback signal.Acquired signal comes from transducer, carry out analog by level Four operational amplifier shown in Figure 5, pass to the built-in A/D converter of central processing unit, be converted to digital signal and deposit corresponding registers in by A/D converter, again through offering central control module as the reference that forms control logic after software filtering processing and the numerical computations.
Fig. 6 handles flow chart for measuring, and its workflow is as follows:
(1) reads each road sampled signal;
(2) call number filtering subprogram;
(3) call the numerical computations subprogram;
(4) signal processing finishes.
Fig. 7 is a digital filtering subprogram block diagram, and its workflow is as follows:
A) beginning;
B) determine the address dma of corresponding history table according to asking project;
C) read current input value X (n) to the dma-1 unit;
D) X (n-1) is carried out product (multiply by coefficient of correspondence in the formula), add up (so that realizing add operation in the formula), data move (depositing X (n-1) in the dma+1 unit);
E) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
F) X (n) is carried out product, add up, data move (depositing X (n) in the dma unit as the X (n-1) that calculates next time);
G) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
H) Y (n-1) carries out product, adds up, data move;
I) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry;
J) Y (n) is deposited in the dma-2 unit as Y (n-1) next time;
K) output Y (n);
L) return.
Fig. 8 is a numerical computations subprogram block diagram, and its workflow is as follows:
A) beginning;
B) determine the first address of this item record one-period tables of data according to asking project, and determine address offset amount A in the table in the position of current sinusoidal period according to current time (having the cycle rate counter count value to determine);
C) determine address offset amount in the table;
D) XZ=XZ-XA (XZ is an one-period numerical value summation, and A is a current count value);
E) read in currency and deposit register XA in;
f)XZ＝XZ+XA；
G) X=XZ*K*1.11 (COEFFICIENT K=1/96);
H) return.
Module software is packed into the subprogram form in the flash memory of DSP.
2, central control module
Central control module is mainly used in the realization of control logic, is core with IC101, expansion crystal oscillating circuit, system reset circuit, outer extension memory and multichannel level translator construction system platform, and realize control logic by software based on this.
Central control module software is not only realized control logic, and information is managed, and is mainly judged, moves and shut down control by service conditions to constitute.Service conditions judge software respectively by initialize routine, self-check program, accept power-on command and DC bus-bar voltage normal judge constitute; Moving and shut down control program is called and is constituted by startup and shutdown judgement, the control logic of powering, invertor operation control, communication.
Figure 10 is for operation and shut down the control program block diagram, and its workflow is as follows:
(1) waits for regularly interruption;
(2) timing arrives, and enters interrupt handling routine, each road feedback signal is measured, and judgment task state whether normal (calling the warning subprogram);
(3) after interruption is returned, call the invertor operation control program, make inverter work;
(4) the inverter work state information is transmitted by communication program;
(5) judge whether to start for the first time? if start for the first time, count, change the 7th step (guarantee to export stable back and give self system's power supply) over to; If not starting for the first time, self system's power supply realizes, changes next step over to;
(6) judge whether externally power supply and execution corresponding operating;
(7) judged whether halt command? no, return the first step; Have, change next step over to;
(8) shut down;
(9) work state information is transmitted by communication program;
(10) forward the starting position of service conditions determining program to.
Figure 11 is a phase control program block diagram, and its workflow is as follows:
(1) carries out cycle count (standard sine wave is separated into 96 points and exists in the numerical table, and the purpose of cycle count is to read the value of corresponding sine wave in the table as the control reference with count value);
(2) carry out the adjusted value of PID regulating and controlling according to control is given with value of feedback;
(3) regulated value is suitably handled as correction factor;
(4) in sine table, find sine value as the control reference with count value as pointer;
(5) sine value be multiply by the departure correction factor that obtains in the 3rd step, obtain the working control amount.
Above program is packed into the main program form in the flash memory of DSP, and wherein the invertor operation control program is moved and shuts down in the flash memory that control program called and deposited in DSP, in order to realize the expection control logic with the subprogram form.
3, multichannel power driver module
The multichannel power driver module has increased the burst pulse limitation function based on the special-purpose drive plate (specification is SKHI23/17) of outsourcing Germany Xi Menkang company.The burst pulse limitation function is implanted among the CPLD with the programming form, and the burst pulse drive signal that the filtering time is too short is eliminated invalid devices switch action.
Figure 13 is a burst pulse limiting program block diagram, and its workflow is as follows:
(1) counter O reset, the flag bit zero clearing;
(2) do you judge incoming level? high level enters next step; Low level changed for the 5th step over to;
(3) do you judge that count value is not to the burst pulse limits value? be that the output high level also changed for second step over to; Not to change next step over to;
(4) counter adds 1, and output low level changed for second step over to;
Is (5) the judgement symbol position 1? be to change for the 7th step over to; Not to change next step over to;
(6) do you judge that count value is not to the burst pulse limits value? be mark position 1; Not counter O reset;
(7) do you judge that count value is zero? be flag bit zero clearing and output low level; Not that counter subtracts 1 and export high level;
(8) changed for second step over to.
4, classifying alarm administration module
The classifying alarm administration module adopts three grades of designs of reporting to the police.Danger warning utilizes the PDPINTA pin to be incorporated into the real-time that module guarantees warning; The feedback information of I and II warning by monitoring forms on analytical system operating state basis.
The interrupt routine block diagram that Figure 14 causes for danger warning, its workflow is as follows:
(1) system closedown (closing all drivings) to inverter;
(2) disconnect all relays;
(3) by working state of system before communication program transmission warning message and the shutdown;
Does (4) inquiry have or not further communication request? have, will send for information about;
(5) returned for the 4th step.
Figure 15 is an I and II warning subprogram block diagram, and its workflow is as follows:
(1) will gather three-phase current and ask for maximum (IAn, IBn, ICn are respectively the three-phase electricity flow valuve);
(2) transfer three-phase current warning subprogram;
(3) input neutral line current (IO is the neutral line current value);
(4) the alert subprogram of zeroing report from a liner;
(5) three-phase voltage of gathering is asked for maximum and minimum value (UAN, UBN, UCN are respectively the three-phase voltage value);
(6) call the voltage alarm subprogram;
Call DC bus-bar voltage warning subprogram (UD is a d-c bus voltage value).Danger warning is packed into the interrupt routine form in the flash memory of DSP; I and II is reported to the police and to be packed in the flash memory of DSP with the subprogram form.
5, classification communication management module
Classification communication management module requires to carry out communication by different passages according to the information real-time.
Figure 20 is the communication program block diagram, and its workflow is as follows:
(1) reads the host computer input information;
(2) do you judge that dangerous warning is not? have, by special I/O police that transmits messages;
(3) do you judge have one-level to report to the police not? no, changed for the 5th step over to;
(4) physical quantity of alarm code and initiation warning is pressed the serial protocol packing, and send by the dedicated serial passage;
(5) each physical quantity is pressed the packing of CAN bus protocol, and send by the CAN bus;
(6) do you judge have further communication need not? have, on request information is sent by the CAN bus;
(7) return.
Because therefore inversion system and host computer close together in the micro fuel engine power generation unit utilize special I/O interface fault message to be transmitted the real-time that exchanges with guarantee information; The dedicated serial interface is used to transmit higher control command of real-time and the coordination information relevant with control; Adopt the CAN bus to transmit for a large amount of video datas.Module software is packed into the subprogram form in the DSP flash memory.
Use inversion system of the present invention, its control procedure peace following steps are carried out:
Whether step 2, check system be normal;
Step 3, central control module are waited for the power transformation circuit work order;
Step 4, receive and wait for after the order detecting and enter stable with acquisition module input DC bus-bar voltage by multichannel data;
Step 5, central control module are waited for the arrival of regularly interrupting;
Do step 6, classifying alarm administration module judge whether each physical quantity that detects normal? undesired, enter the operation of reporting to the police;
Step 7, detection information and the controlled target control power transformation circuit gathered according to multichannel data detection and acquisition module move;
Step 8, classification communication management module and other system and upper machine communication;
Step 9, central control module decision are according to circumstances powered to self unit with to external user;
Step 10, central control module inquiry halt command do not have halt command then to return step 5;
Step 11, there is halt command then to carry out stopping process, and detects and the determining program head before returning operation.
Claims (8)
1, a kind of inversion system is characterized in that being made of power transformation circuit and control system, and power transformation circuit provides electric power by the passage of direct current to exchange conversion, comprises power inversion circuit and power filter circuit; Control system is used to realize control algolithm, information management and exchange, and to switching device enforcement control in the power transformation circuit, it includes central control module, multichannel data detection and acquisition module, classification communication management module, multichannel power driver module and classifying alarm administration module.
2, inversion system as claimed in claim 1, it is characterized in that power inversion circuit adopts the three-phase four-arm topological structure, circuit is made of eight switching devices, eight fly-wheel diodes and four noninductive electric capacity, per two switching devices of cross-over connection and diode constitute a unit between PN, promptly a brachium pontis is realized by a biswitch device blocks, inserts noninductive electric capacity on module, circuit adopts four biswitch device blocks altogether, and promptly four brachium pontis constitute.
3, inversion system as claimed in claim 1, it is characterized in that control system is made of central control module, multichannel data detection and acquisition module, classification communication management module, multichannel power driver module and classifying alarm administration module, IC101 is a central processing unit, in have memory space to be used for stored program and data; IC201, IC202, IC203, IC204, IC205 are for realizing the voltage matches chip of 3.3V to 5V; IC102 is used for system reset; IC206 is the dedicated serial communication chip; IC207 is a CAN bus communication chip, with IC101 is core, expanded memory circuit, voltage matches circuit, system reset circuit, serial communication circuit, CAN bus communication circuit, warning passage, driven passage, data acquisition channel, I/O passage, crystal oscillating circuit, wherein the D0-D15 of (1) IC101 provides data signal interfaces; (2) A0-A15 of IC101 provides the address; (3) the W/ R of IC101 connects 1DIR and the 2DIR of IC201; (4) DS of IC101, RD, IS, PS, WE, IOPC2 form the control signal interface and link to each other with memory cell; (5) RS of IC101, WDI link to each other with reset circuit; (6) SCITXD of IC101 provides the data-interface of serial communication with SCIRXD and has linked to each other with the dedicated serial communication chip; (7) CANTX of IC101, CANRX provide the data-interface of CAN bus communication and have linked to each other with special-purpose CAN communication chip; (8) PDPINTA of IC101 provides the introducing interface of danger warning and has linked to each other with driver element; (9) PWM1-PWM8 of IC101 provides the signal of driving power device and has linked to each other with driver element; (10) channel hardware circuit of the ADCIN00-ADCIN09 of IC101 and multi pass acquisition module links to each other; (11) IOPA3 of IC101, IOPA4, IOPE3-IOPE6, IOPF0, IOPF1, IOPF5, IOPF6 provide special I/O communication interface and link to each other with special I/O line; (12) TCK of IC101, TDO, TDI, TMS, TRST, EMU1, EMU0 link to each other with socket; (13) PLLF2 of IC101, PLLF, XTAL1, XTAL2 link to each other with crystal oscillating circuit; (14) VSSO of IC101 links to each other with the ground wire of system with VSS; (15) VDD0 of IC101 links to each other with 3.3V with VDD, and the working power of IC101 is provided.
4, inversion system as claimed in claim 1, it is characterized in that described multichannel data detects to combine with acquisition module employing hardware filtering circuit and software filtering algorithm handles each road feedback signal, hardware filtering circuit multichannel is some single channels formations in parallel, and the software processes flow process is as follows:
(1) read each road sampled signal,
(2) call number filtering subprogram,
(3) call the numerical computations subprogram,
(4) signal processing finishes; Wherein the workflow of digital filtering subprogram is as follows:
A) beginning,
B) determine the address dma of corresponding history table according to asking project,
C) read current input value X (n) to the dma-1 unit,
D) X (n-1) is carried out product (multiply by coefficient of correspondence in the formula), add up (so that realizing add operation in the formula), data move (depositing X (n-1) in the dma+1 unit),
E) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry,
F) X (n) is carried out product, adds up, data move (depositing X (n) in the dma unit as the X (n-1) that calculates next time),
G) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry,
H) Y (n-1) carries out product, add up, data move,
I) judge that no-carry is arranged, handle that no-carry directly changes next step over to if there is carry will carry out carry,
J) Y (n) is deposited in the dma-2 unit as Y (n-1) next time,
K) output Y (n),
L) return;
The workflow of numerical computations subprogram is as follows:
A) beginning,
B) determine the first address of this item record one-period tables of data according to asking project, and determine address offset amount A in the table in the position of current sinusoidal period according to current time (having the cycle rate counter count value to determine),
C) determine address offset amount in the table,
D) XZ=XZ-XA (XZ is an one-period numerical value summation, and A is a current count value),
E) read in currency and deposit register XA in,
f)XZ＝XZ+XA，
G) X=XZ*K*1.11 (COEFFICIENT K=1/96),
L) return.
5; inversion system as claimed in claim 1 is characterized in that described central control module hardware circuit is core with IC101; the expansion crystal oscillating circuit; outer watchdog circuit; outer extension memory and multichannel level translator constitute; service conditions judges that software is respectively by initialize routine; self-check program; accept power-on command and DC bus-bar voltage and normally judge formation; operation and shutdown control program are by starting and shutting down and judge; the power supply control logic; invertor operation control; formation is called in communication
The workflow of operation and shutdown control program is as follows:
(1) wait for regularly interruption,
(2) timing arrives, and enters interrupt handling routine, each road feedback signal is measured, and judgment task state whether normal (calling the warning subprogram),
(3) after interruption is returned, call the invertor operation control program, make inverter work,
(4) the inverter work state information is transmitted by communication program,
(5) judge whether to start for the first time? if start for the first time, count, changed for the 7th step over to; If not starting for the first time, self system's power supply realizes, changes next step over to,
(6) judge whether externally power supply and execution corresponding operating,
(7) judged whether halt command? no, return the first step, have, change next step over to,
(8) shut down,
(9) work state information is transmitted by communication program,
(10) forward the starting position of service conditions determining program to;
The control logic basically identical of three-phase control, the workflow of a phase control program is as follows:
(1) carry out cycle count (standard sine wave is separated into 96 points and exists in the numerical table, and the purpose of cycle count is to read the value of corresponding sine wave in the table as the control reference with count value),
(2) carry out the adjusted value of PID regulating and controlling according to control is given with value of feedback,
(3) regulated value is suitably handled as correction factor,
(4) in sine table, find sine value as the control reference with count value as pointer,
(5) sine value be multiply by the departure correction factor that obtains in the 3rd step, obtain the working control amount;
The 4th brachium pontis is regulated with the three-phase adjusting essential distinction, and the workflow of the 4th brachium pontis control program is as follows:
(1) read neutral line current,
(2) neutral line current is carried out Filtering Processing (electric current be multiply by first order inertial loop) and deposits feedback register FK in, and, carry out PID and regulate, pass through amplitude limiting processing again as controlled quentity controlled variable KZ with 0 as given controlled target (GD is given register) as feedback,
(3) controlled quentity controlled variable is deposited in the 4th brachium pontis comparand register.
6, inversion system as claimed in claim 1 is characterized in that the multichannel power driver module adopts the burst pulse restriction strategy, and its limit procedure is controlled according to the following steps:
(1) counter O reset, the flag bit zero clearing,
(2) do you judge incoming level? high level enters next step; Low level changed for the 5th step over to,
(3) do you judge that count value is not to the burst pulse limits value? be that the output high level also changed for second step over to, was not to change next step over to;
(4) counter adds 1, and output low level changed for second step over to,
Is (5) the judgement symbol position 1? be, changed for the 7th step over to, be not, change next step over to,
(6) do you judge that count value is not to the burst pulse limits value? be, mark position 1, be not, counter O reset,
(7) do you judge that count value is zero? be, flag bit zero clearing and output low level, be not, counter subtracts 1 and export high level,
(8) changed for second step over to.
7, inversion system as claimed in claim 1 is characterized in that described hierarchical communication module adopts the data communication of different priorities, and communication channel is divided three classes:
(1) special I/O mouth, (2) dedicated serial communication interface, (3) CAN bus interface;
The workflow of communication program is as follows:
(1) read the host computer input information,
(2) do you judge that dangerous warning is not? have, by special I/O police that transmits messages,
(3) do you judge have one-level to report to the police not? no, changed for the 5th step over to,
(4) physical quantity of alarm code and initiation warning is pressed the serial protocol packing, and sends by the dedicated serial passage,
(5) each physical quantity is pressed the packing of CAN bus protocol, and sends by the CAN bus,
(6) do you judge have further communication need not? have, on request information sent by the CAN bus,
(7) return.
8, the control method of the described inversion system of claim 1 is characterized in that comprising following steps:
Step 1, each register of central control module initialization;
Whether step 2, check system be normal;
Step 3, central control module are waited for the power transformation circuit work order;
Step 4, receive and wait for after the order detecting and enter stable with acquisition module input DC bus-bar voltage by multichannel data;
Step 5, central control module are waited for the arrival of regularly interrupting;
Do step 6, classifying alarm administration module judge whether each physical quantity that detects normal? undesired, enter the operation of reporting to the police;
Step 7, detection information and the controlled target control power transformation circuit gathered according to multichannel data detection and acquisition module move;
Step 8, classification communication management module and other system and upper machine communication;
Step 9, central control module decision are according to circumstances powered to self unit with to external user;
Step 10, central control module inquiry halt command do not have halt command then to return step 5;
Step 11, there is halt command then to carry out stopping process, and detects and the determining program head before returning operation.
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