CN1787415B - Apparatus for realizing false random code phase deviation and method for forming false random code - Google Patents
Apparatus for realizing false random code phase deviation and method for forming false random code Download PDFInfo
- Publication number
- CN1787415B CN1787415B CN2004100968610A CN200410096861A CN1787415B CN 1787415 B CN1787415 B CN 1787415B CN 2004100968610 A CN2004100968610 A CN 2004100968610A CN 200410096861 A CN200410096861 A CN 200410096861A CN 1787415 B CN1787415 B CN 1787415B
- Authority
- CN
- China
- Prior art keywords
- mask
- output
- noise code
- phase
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
This invention discloses a device for realizing phase offset of a false random code and a method for generating it, in which, said device includes a linear feed back shift register, an AND gate array, a mask storage and an exclusive-OR gate, in which, the register is a general false random code generator, the read address of the mask storage is corresponding to the phase offset value, the stored content is the mask corresponding to the offset value, the bits of the mask are corresponding to the registers in the linear feedback shift register, the output of which and the output of the mask bits of the mask storage are taken as the input of the AND gate array, the output of which as the input of the exclusive-OR gate, the output of which is the false random code necessary for the phase deviation.
Description
Technical field
The present invention relates to data communication field, particularly realize the method and apparatus of pseudorandom (PN) code phase displacement.
Background technology
The communication technology of code division multiple access and Wideband Code Division Multiple Access (WCDMA) standard has obtained using widely at present, and multiple business such as speech, data, multimedia can be provided for people.In the communication of code division multiple access standard, the data of transmitting terminal send after by the scrambling of PN sign indicating number, carry out descrambling at receiving terminal by using same PN sign indicating number.When system realized, frequent needs used the PN sign indicating number after current certain phase deviation of PN sign indicating number.
The implementation structure of PN sign indicating number uses linear feedback shift register usually, and Fig. 1 is the universal circuit structure of PN code generator, is made up of shift register and XOR gate.Each clock of PN code generator generates a PN sign indicating number, if use PN sign indicating number after certain phase deviation, such as 256 phase deviations, then need PN sign indicating number generator is moved 256 clocks earlier, could generate the PN sign indicating number that needs use, and the PN sign indicating number that generates is useless in these 256 clocks, other modules of system are in order to obtain available PN sign indicating number, have to wait for, can cause system to be in idle condition like this, thereby reduce the disposal ability of system.
Summary of the invention
Purpose of the present invention is exactly to propose a kind of unnecessary clock that need not to move, and directly exports the apparatus and method of the PN sign indicating number after the required phase deviation from the PN code generator.
A kind of device of realizing pseudo-random code phases skew, comprise linear feedback shift register A, with gate array B, mask memory C and XOR gate D; Described linear feedback shift register A is a general pseudo-noise code generator; It is corresponding with phase pushing figure that mask memory C reads the address, and the content of storage is the mask of required phase pushing figure correspondence, and each bit of mask is corresponding one by one with each register among the linear feedback shift register A; Each register output of linear feedback shift register A and each the bit output conduct of mask of corresponding mask memory C and the input of gate array B, with the output of the gate array B input as XOR gate D, the output of XOR gate D is the pseudo noise code of required phase deviation.
Utilize said apparatus to generate the method for the pseudo noise code after the phase deviation, comprise the following steps:
The generator polynomial of step 2, the phase deviation of using as required and pseudo noise code is determined the mask of each phase deviation correspondence;
Step 3, all masks that will obtain deposit in the mask memory;
Step 4, read the address, read mask memory, obtain mask according to phase deviation structure;
Step 5, each bit of the mask that obtains in the step 4 is carried out operating with gate array with each register of corresponding linear feedback shift register;
Step 6, will carry out xor operation, promptly obtain the pseudo noise code after the phase deviation with all output bits of gate array.
The apparatus and method that adopt the present invention to propose, compared with prior art, during PN sign indicating number after phase deviation m is used in hope, do not need m unnecessary clock of PN code generator operation earlier, can be directly obtain PN sign indicating number behind the required phase deviation m by the current phase place of PN code generator, saved the time of PN code generator, removed because the PN code generator takies the influence that over head time system is caused.When required mask leaves among the ROM (read-only memory), and required deviant is not for a long time, and the circuitry consumes that this programme compared with prior art increases is considerably less, can ignore for large scale integrated circuit.
Description of drawings
Fig. 1 is the circuit theory diagrams of general pseudo-noise code generator;
Fig. 2 is the circuit theory diagrams of the device of the realization pseudo-random code phases skew that proposes of the present invention;
Fig. 3 is the circuit theory diagrams of the pseudo-noise code generator on one 3 rank;
Fig. 4 is the flow chart of the method that proposes of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Fig. 1 had carried out explanation in background technology.
Before explanation the present invention, briefly bright to one in principle work of the present invention earlier.The linear feedback shift register that generates the PN sign indicating number can be expressed as a generator polynomial G (x) on mathematics, it is output as a m sequence.
For explanation intuitively, get G (x)=x
3+ x+1, i.e. one 3 order polynomial, the cycle of its output sequence is 2
3-1=7.Because the m sequence is a periodic sequence, so the value of phase deviation has 0～6 totally 7 kinds, and its circuit is embodied as shown in Figure 3, it is output as E-1, and the phase deviation of this moment is 0, when the PN sign indicating number after 1 phase deviation of needs output, can directly export E-2, deposit the preceding value of a bat because E-2 is E-1; In like manner, phase deviation is 2 o'clock, can directly export E-3; Phase deviation is 3 o'clock, output E-4, the i.e. XOR of E-1 and E-2; Phase deviation is 4 o'clock, the XOR of output E-2 and E-3; Phase deviation is 5 o'clock, is output as the XOR of E-1, E-2 and E-3; Phase deviation is 6 o'clock, the XOR of output E-1 and E-3.
Comprehensive above various situations, needs are done XOR with which register and are constructed mask in the time of can being offset according to out of phase, use linear feedback shift register therewith mask do with array processing after again XOR export.Register and mask that above-mentioned 7 kinds of situations need be participated in XOR are listed as follows respectively, and the register that will need here to participate in XOR is called tap.
| Phase deviation | Tap | Mask (2 system) |
| 0 | E-1 | 001 |
| 1 | E-2 | 010 |
| 2 | E-3 | 100 |
| 3 | E-2、E-1 | 011 |
| 4 | E-3、E-2 | 110 |
| 5 | E-3、E-2、E-1 | 111 |
| 6 | E-3、E-1 | 101 |
Greater than 6 or less than 0 situation, can determine required mask according to this remainder then for phase pushing figure earlier to 7 complementations, be 12 o'clock such as phase deviation, and remainder is 5, and phase deviation is-3 o'clock, and remainder is 4.
For generator polynomial is the PN code generator of other situations, can obtain the mask of various phase deviation correspondences according to said method.The process of top derivation mask also can calculate by the mathematics polynomial division.
Fig. 2 is the circuit theory diagrams of the device of the realization pseudo-random code phases skew that proposes of the present invention, as shown in Figure 2, the device of the realization pseudo-random code phases skew that the present invention proposes, comprise linear feedback shift register A, with gate array B, mask memory C and XOR gate D; Described linear feedback shift register A is a general pseudo-noise code generator; Mask memory C can be read-only memory or readable and writable memory, it is corresponding with phase pushing figure that it reads the address, the content of storage is the mask of required phase pushing figure correspondence, and each bit of mask is corresponding one by one with each register among the linear feedback shift register A; Each register output of linear feedback shift register A and each the bit output conduct of mask of corresponding mask memory C and the input of gate array B, with the output of the gate array B input as XOR gate D, the output of XOR gate D is the pseudo noise code of required phase deviation.
Fig. 4 is to use the device among Fig. 2 to generate the flow chart of the pseudo noise code after the phase deviation, as shown in the figure, comprises the following steps:
The generator polynomial of step 2, the phase deviation of using as required and pseudo noise code is determined the mask of each phase deviation correspondence.
Step 3, all masks that will obtain deposit in the mask memory.
Step 4, read the address, read mask memory, obtain mask according to phase deviation structure.
Step 5, each bit of the mask that obtains in the step 4 is carried out operating with gate array with each register of corresponding linear feedback shift register; As shown in Figure 2, classify B as with gate array, each register of linear feedback shift register is A-1 ..., A-n, mask memory is output as C-1 ..., C-n, A-1 and C-1 as with the input of door B-1 ..., A-n and C-n as with the input of door B-n.
Step 6, will carry out xor operation with all output bits of gate array, i.e. B-1 ..., xor operation is done in the output of B-n, promptly obtains the pseudo noise code after the phase deviation.
Below in conjunction with Fig. 3, with generator polynomial G (x)=x
3The PN code generator of+x+1 is an example, and the method for using the mathematics polynomial division to obtain mask is described.Its principle is: if required phase pushing figure is n, with x
nBeing dividend, is that divisor is done polynomial division with G (x), obtains residue, obtains the mask of this phase deviation corresponding to G (x) according to remainder, judges that promptly coefficient every in the residue, coefficient are that 0 o'clock mask is 0, and coefficient is that 1 o'clock mask is 1.Be that 4 situation describes with phase deviation below.
If required phase deviation is 4, x
4Divided by x
3The remainder of+x+1 is x
2+ x, then its mask is 110, its derivation formula is as follows:
Phase deviation is 6 o'clock, x
6Divided by x
3The remainder of+x+1 is x
2+ 1, its mask is 101, and phase pushing figure is similar when being other situations, can obtain corresponding mask by the method.
If required phase pushing figure has: 0,2,4,6 totally four kinds, can be with phase deviation 0 as address 0, phase deviation 2 is as address 1, and phase deviation 4 is as address 2, and phase deviation 6 is as the read only memory ROM below 3 structures of address.
| The address | The ROM content |
| 0 | 001 |
| 1 | 100 |
| 2 | 110 |
| 3 | 101 |
If do not use ROM, and when using read-write RAM, can write in the address 0 of RAM 001 earlier, write in the address 1 100, write in the address 2 110, write in the address 3 101, then with phase deviation 0 as address 0, phase deviation 2 is as address 1, and phase deviation 4 is as address 2, and phase deviation 6 is read this RAM as address 3.
Claims (3)
1. device of realizing pseudo-random code phases skew, it is characterized in that comprising linear feedback shift register (A), with gate array (B), mask memory (C) and XOR gate (D); Described linear feedback shift register (A) is a general pseudo-noise code generator; Mask memory (C) to read the address corresponding with phase pushing figure, the content of storage is the mask of required phase pushing figure correspondence, each bit of mask is corresponding one by one with each register in the linear feedback shift register (A); Each register output of linear feedback shift register (A) and each bit output conduct of the corresponding mask of mask memory (C) and the input of gate array (B), with the output of gate array (B) input as XOR gate (D), the output of XOR gate (D) is the pseudo noise code of required phase deviation;
Wherein, when needs use the pseudo noise code of a phase pushing figure, construct the address of reading with the corresponding mask memory of this phase pushing figure (C), with according to the pseudo noise code of the current phase place of linear feedback shift register (A) output and the mask of mask memory (C) output, produce the pseudo noise code of this phase pushing figure at once and do not need the described general pseudo-noise code generator unnecessary clock of operation earlier.
2. device according to claim 1 is characterized in that, described mask memory (C) is read-only memory or readable and writable memory.
3. a method of utilizing the described device of claim 1 to generate the pseudo noise code after the phase deviation is characterized in that comprising the following steps:
All values of step 1, the definite phase deviation that need use;
All values of step 2, the phase deviation of using as required and the generator polynomial of pseudo noise code are determined and the corresponding mask of each phase pushing figure;
Step 3, all masks that will obtain deposit in the mask memory;
Step 4, when needs use the pseudo noise code of a phase pushing figure, according to this phase pushing figure structure and the corresponding mask memory of this phase pushing figure (C) read read mask memory (C) in the address, obtain mask;
Step 5, carry out and operation with the output of each corresponding register of linear feedback shift register (A) with gate array (B) each bit with the mask that obtains in the step 4;
Step 6, XOR gate (D) will be carried out xor operation with all output bits of gate array (B), export the pseudo noise code of this phase pushing figure;
Wherein, in the pseudo noise code process that generates this phase pushing figure, according to the pseudo noise code of the current phase place of linear feedback shift register (A) output and the mask of mask memory (C) output, produce the pseudo noise code of this phase pushing figure at once and do not need the described general pseudo-noise code generator unnecessary clock of operation earlier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2004100968610A CN1787415B (en) | 2004-12-08 | 2004-12-08 | Apparatus for realizing false random code phase deviation and method for forming false random code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2004100968610A CN1787415B (en) | 2004-12-08 | 2004-12-08 | Apparatus for realizing false random code phase deviation and method for forming false random code |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1787415A CN1787415A (en) | 2006-06-14 |
| CN1787415B true CN1787415B (en) | 2011-05-25 |
Family
ID=36784751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2004100968610A Active CN1787415B (en) | 2004-12-08 | 2004-12-08 | Apparatus for realizing false random code phase deviation and method for forming false random code |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1787415B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101098162B (en) * | 2006-06-27 | 2010-08-18 | 中兴通讯股份有限公司 | Method and apparatus for creating long scrambling code and phase offset code |
| CN102130694A (en) * | 2011-02-28 | 2011-07-20 | 浙江大学 | Circuit for parallelly encoding quasi-cyclic low-density parity check code |
| US9143325B2 (en) * | 2012-12-14 | 2015-09-22 | Microsoft Technology Licensing, Llc | Masking with shared random bits |
| CN106160785A (en) * | 2015-04-22 | 2016-11-23 | 宜春市等比科技有限公司 | A kind of pseudorandom number generation method for spread spectrum communication and channel multiplexing |
| CN108896905A (en) * | 2018-07-17 | 2018-11-27 | 龙口盛福达食品有限公司 | A kind of intelligent soy milk grinder AI chip circuit automatic fault selftesting method |
| CN111708513B (en) * | 2020-05-15 | 2023-12-08 | 深圳和而泰智能家电控制器有限公司 | Pseudo-random number seed generation method and related product |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1302495A (en) * | 1999-04-21 | 2001-07-04 | 三星电子株式会社 | Apparatus and method for generating spreading code in CDMA communication system |
| CN1094019C (en) * | 1997-09-02 | 2002-11-06 | 松下电器产业株式会社 | PN code generating device and mobile radio communication system |
| CN1438768A (en) * | 2002-02-14 | 2003-08-27 | 松下电器产业株式会社 | Code generation circuit |
| CN1450745A (en) * | 2003-01-06 | 2003-10-22 | 威盛电子股份有限公司 | Scrambler/descrambler and method theirof |
-
2004
- 2004-12-08 CN CN2004100968610A patent/CN1787415B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1094019C (en) * | 1997-09-02 | 2002-11-06 | 松下电器产业株式会社 | PN code generating device and mobile radio communication system |
| CN1302495A (en) * | 1999-04-21 | 2001-07-04 | 三星电子株式会社 | Apparatus and method for generating spreading code in CDMA communication system |
| CN1438768A (en) * | 2002-02-14 | 2003-08-27 | 松下电器产业株式会社 | Code generation circuit |
| CN1450745A (en) * | 2003-01-06 | 2003-10-22 | 威盛电子股份有限公司 | Scrambler/descrambler and method theirof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1787415A (en) | 2006-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Addabbo et al. | A feedback strategy to improve the entropy of a chaos-based random bit generator | |
| CN101371222B (en) | Apparatus and method for generating scrambling code | |
| JP2004173321A5 (en) | ||
| CN1787415B (en) | Apparatus for realizing false random code phase deviation and method for forming false random code | |
| Patnala et al. | A modernistic way for KEY generation for highly secure data transfer in ASIC design flow | |
| CN104636115A (en) | Post processing device and method for true random numbers | |
| CN105808207A (en) | Chaotic pseudo random number generator, and circuit and system on chip thereby | |
| CN101072098A (en) | Long Scrambling code phase-sequence offset method and device for wideband CDMA system | |
| JP2012516115A5 (en) | ||
| Lan et al. | A random number generator for low power cryptographic application | |
| CN108255464B (en) | Data scrambling method, descrambling method and device thereof | |
| CN111262686A (en) | Security verification method for RSSP-I secure communication | |
| EP2827516B1 (en) | Scrambling code generation method, apparatus and scrambling code processing apparatus | |
| CN104182203A (en) | True random number generating method and device | |
| RU2313125C1 (en) | Generator of pseudo-random series | |
| Khan et al. | Design of 2× 2 vedic multiplier using GDI technique | |
| JP2011123356A (en) | Prime number generating device, prime number generating method, and prime number generating program | |
| Jiteurtragool et al. | True random number generator based on compact chaotic oscillator | |
| US20210191899A1 (en) | Data processing circuit, data storage device including the same, and operating method thereof | |
| CN101262296A (en) | A scrambled code generator for WCDMA system and its realization method | |
| CN105187151B (en) | A kind of production method and system of WCDMA system downlink scrambling code sequence | |
| US20070230695A1 (en) | Apparatus and method for generating a number with random distribution | |
| Peng et al. | A side-channel attack resistant AES with 500mbps, 1.92 pj/bit PVT variation tolerant true random number generator | |
| CN202649995U (en) | Non-linear pseudorandom sequence generator | |
| CN112115508A (en) | Random number generation method and device applied to block chain and random number generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151110 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District, Guangdong high tech Industrial Park, science and Technology Industrial Park, ZTE building, block A, layer 6, layer Patentee before: ZTE Corporation |
|
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20060614 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Apparatus for realizing false random code phase deviation and method for forming false random code Granted publication date: 20110525 License type: Common License Record date: 20190619 |
|
| EE01 | Entry into force of recordation of patent licensing contract |