CN1787385A - Data bus converting device and its RS coder decoder - Google Patents
Data bus converting device and its RS coder decoder Download PDFInfo
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- CN1787385A CN1787385A CN 200410052576 CN200410052576A CN1787385A CN 1787385 A CN1787385 A CN 1787385A CN 200410052576 CN200410052576 CN 200410052576 CN 200410052576 A CN200410052576 A CN 200410052576A CN 1787385 A CN1787385 A CN 1787385A
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Abstract
This invention relates to a data bus line conversion device and its RS coder and decoder, in which, said data buss line conversion device includes two kinds of RS coders and decoders realized at the same time in the system, one is RS(nl,kl) compound code and the other is RS(n2 and k2)code using a data buss line of P*m1 bit width and having the same input and output interface to realize mutual conversion between P*m1 and T*m2 bit bus by the plug and winkle of bit 0 to avoid the generation of incomplete code cells.
Description
Technical field
The data/address bus conversion equipment that the present invention relates to a kind of communications field with and fec arrangement, the device for encoding and decoding of in particular a kind of RS (Reed-Solomon) sign indicating number.
Background technology:
The RS sign indicating number is the abbreviation of Reed-Solomon sign indicating number, is at first proposed in nineteen sixty separately by Reed and Solomon, is Galos territory GF (2
m) on linearity grouping cyclic code.Comprise n code element in the code character (also claiming code word), k information code element (being called information sets), n-k verification code element (being called the verification group) generally used RS[n, k] expression, and can detect n-k mistake, can correct
Individual mistake is the multibit code that a class has very strong error correcting capability.In computer error correction system, particularly storage system,, also adopted the RS sign indicating number in a large number at optical transmission system in recent years as using very generally in CD, disk, the tape.
Present RS device for encoding and decoding is only at a kind of RS sign indicating number, and the input/output bus width is identical with the bit number of code element, but in real application systems, requirement realizes two or more RS sign indicating numbers simultaneously usually.Wherein a kind of is standard RS sign indicating number or its shortening sign indicating number, and another kind of or multiple is the compound key that multichannel interweaves.16 tunnel interweave RS (255,239) and RS (2720,2550) for example, 8 tunnel interweave RS (31,26) and RS (155,131), 8 tunnel interweave RS (15,11) and RS (80,59) etc.Total bit number of the multiple RS sign indicating number code word that realizes simultaneously in same system is identical, but the bit number of code element is different, and the bit number of information sets also may be different.Generally be as the criterion with the information sets least number of bits, the usefulness 0 that surpasses this value is filled.16 tunnel interweave RS (255,239) and RS (2720,2550) for example, both total bit numbers all are 32640, but the former information sets bit number is 16*239*8=30592, the latter's information sets bit number is 2550*12=30600.In order to realize both compatibilities, last 8 bits of each information sets of regulation RS (2720,2550) are fixed as 0.
In real application systems, require to use identical input/output interface usually.Still with 16 tunnel RS (255 that interweave, 239) and RS (2720,2550) be example, at present, 16 tunnel RS (255,239) that interweave are used widely, the general 16*8=128bits data/address bus that adopts during realization, one group of every 8-bits, in order respectively with RS (255, a 239) encoder or decoder correspondence.RS (255,239) encoder or decoder be actual, and what use is the 8-bits data/address bus, and each clock cycle is code element of input and output just.RS (2720,2550) will use and the 16 tunnel identical interfaces of RS (255,239) that interweave, and data/address bus also must be 128 bits.But each code element of RS (2720,2550) comprises 12 bits, 128 is not 12 integral multiple, must comprise incomplete code element in 128 Bit datas of per clock cycle input and output, but existing RS coding and decoding technology all is unit with the code element, can not handle imperfect code element.8 tunnel interweave RS (31,26) and RS (155,131), 8 tunnel interweave RS (15,11) and RS (80,59) etc. have and 16 tunnel interweave RS (255,239) and the same problems of RS (2720,2550).
Therefore, there is defective in prior art, and awaits improving and development.
Summary of the invention
The object of the present invention is to provide a kind of data/address bus conversion equipment and RS coder thereof, imperfect code element problem at foregoing description, insertion by bit 0 and picking out, realize the mutual conversion between P*m1 and the T*m2 bit bus, avoid the generation of imperfect code element, thereby effectively solve the difficult problem of prior art.
Technical scheme of the present invention is:
A kind of data/address bus conversion equipment, wherein, described data/address bus conversion equipment comprises
Two kinds of RS coders in system, realizing simultaneously, these two kinds of RS coders for the P road interweave RS (n1, k1) (these two kinds of RS coders all use the data/address bus of P*m1 bit width, and input/output interface is identical for n2, k2) sign indicating number for compound key and RS;
One interleaving block and a de-interleaving block, the described P road RS (n1 that interweaves, k1) compound key resolves into the data/address bus that the P road independently has the m1 bit width to the data/address bus of P*m1 bit width by this interleaving block and de-interleaving block, offer P separate RS (n1, k1) coder respectively;
One bus conversion module, described RS (n2, k2) coder is realized conversion between P*m1 bit data bus and the T*m2 bit data bus by this bus conversion module, provide T*m2 bit width data/address bus to RS (n2, k2) half parallel encoding and decoding device carries out T road parallel encoding and decoding;
Wherein (n1 k1) represents that the information code element number is k1 to RS, and the verification code element number is (n1-k1), and each code element comprises the RS sign indicating number of m1 bit; RS (n2, k2) expression information code element number is k2, and the verification code element number is (n2-k2), and each code element comprises the RS sign indicating number of m2 bit; T is RS (n2, k2) code element number of half parallel encoding and decoding device parallel processing.
Described data/address bus conversion equipment, wherein, described bus conversion module comprise P*m1 to T*m2 bus conversion module and T*m2 to the P*m1 bus conversion module, described P*m1 is used for receiving data by the P*m1 bit bus to the T*m2 bus conversion module, deposit a shift register group in, be input to buffer memory among the FIFO by the T*m2 bit data bus again, then with the output of T*m2 bit data bus;
One control module, be used to control described shift register group and insert 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of T*m2 bit data bus that converts to and export with the synchronous frame alligning information of P*m1 bit bus that will receive simultaneously.
Described data/address bus conversion equipment, wherein, described T*m2 is used for receiving data by the T*m2 bit bus to the P*m1 bus conversion module, deposits shift register group in, be input to buffer memory among the FIFO by the P*m1 bit data bus again, then with the output of P*m1 bit data bus;
Described control module control shift register group is inserted 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of P*m1 bit data bus that converts to and export with the synchronous frame alligning information of T*m2 bit bus that will receive simultaneously.
A kind of RS coder that uses described data/address bus conversion equipment, wherein, described RS coder comprises
A P road of the Shi Xianing RS (n1 that interweaves simultaneously, k1) compound key and RS (n2, k2) the RS coder of code coding/decoding function, described P road interweave RS (n1, k1) encoder and RS (n2, k2) encoder adopts identical input/output interface, the described P road RS (n1 that interweaves, k1) (highway width all is the P*m1 bit for n2, k2) the identical input/output interface of decoder employing for decoder and RS.
Described RS coder, wherein, described P road interweave RS (n1, k1) coder comprises an interleaving block and a de-interleaving block, is P road RS volume/decoder between this interleaving block and the de-interleaving block; For encoder, the input data enter to be delivered to the P road RS encoder that interweaves after the system and encodes, and the data behind the coding are by the data/address bus output of P*m1 bit width; For decoder, the input data enter to be delivered to the P road RS decoder that interweaves after the system and deciphers, and the data after the decoding are the data/address bus output by the P*m1 bit width equally.
Described RS coder, wherein, described RS (n2, k2) coder comprise a P*m1 to T*m2 bus conversion module and a T*m2 to the P*m1 bus conversion module, at this P*m1 to T*m2 bus conversion module and this T*m2 between the P*m1 bus conversion module being RS (n2, k2) volume/decoder; For encoder, data to be encoded are delivered to described P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit, T*m2 bit width data input RS (n2, k2) half parallel encoder is encoded, and the data behind the coding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width; For decoder, data to decode is at first delivered to P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit width, T*m2 bit width data input RS (n2, k2) half parallel decoder is deciphered, and the data after the decoding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width.
Described RS coder, wherein, described P*m1 bit width bus and T*m2 bit width bus adopt the clock of same frequency, whether the data that indicate on the bus with enable signal are effective simultaneously, if enable signal does not enable, P*m1 on the bus or T*m2 Bit data are invalid, otherwise effectively.
A kind of data/address bus conversion equipment provided by the present invention and RS coder thereof, owing to adopted RS (n1, k1) the input/output bus width of coder is identical with symbol width, RS (n2, k2) the input/output bus width of half parallel encoding and decoding device be symbol width T doubly, do not relate to imperfect code element, can realize with traditional RS coding and decoding method, efficiently solve imperfect code element and can't be applied to the problem of RS coder, unified the input/output interface between the different RS coding and decoding.
Description of drawings
Fig. 1 is that unified interface of the present invention realizes P road interweave RS (n1, k1) compound key and RS (n2, k2) system construction drawing of Ma coder simultaneously;
Fig. 2 is interweave RS (n1, k1) a coder module structure chart of P of the present invention road;
Fig. 3 is interweave RS (n1, k1) a decoder module structure chart of P of the present invention road;
Fig. 4 is RS of the present invention (n2, k2) a coder module structure chart;
Fig. 5 is RS of the present invention (n2, k2) a decoder module structure chart;
Fig. 6 is that P*m1 of the present invention is to T*m2 bus conversion module structure chart;
Fig. 7 is that T*m2 of the present invention is to P*m1 bus conversion module structure chart.
Embodiment:
Below in conjunction with accompanying drawing specific embodiments of the invention are described in detail.
Its core concept of the inventive method is: two kinds of RS coders in system, realizing simultaneously--P road interweave RS (n1, k1) compound key and RS (n2, k2) sign indicating number all uses the data/address bus of P*m1 bit width, input/output interface is identical.The P road interweaves, and (n1, k1) compound key offers P separate RS (n1, k1) coder respectively by interweaving and de-interleaving block resolves into the data/address bus that the P road independently has the m1 bit width to the data/address bus of P*m1 bit width to RS.RS (n2, k2) coder is by the conversion between bus conversion module realization P*m1 bit data bus and the T*m2 bit data bus, and T*m2 bit width data/address bus is provided, and (n2, k2) half parallel encoding and decoding device carries out T road parallel encoding and decoding to RS.
Wherein (n1 k1) represents that the information code element number is k1 to RS, and the verification code element number is (n1-k1), and each code element comprises the RS sign indicating number of m1 bit; RS (n2, k2) expression information code element number is k2, and the verification code element number is (n2-k2), and each code element comprises the RS sign indicating number of m2 bit; T is RS (n2, k2) code element number of half parallel encoding and decoding device parallel processing.Usually, m1 is less than m2, and m1*k1 is smaller or equal to m2*k2, and P*m1 is smaller or equal to T*m2.
As shown in Figure 1, bus conversion module divide P*m1 to T*m2 bus conversion module and T*m2 to P*m1 bus conversion module two parts, P*m1 receives data to the T*m2 bus conversion module by the P*m1 bit bus, deposit shift register group in, be input to buffer memory among the FIFO by the T*m2 bit data bus again, then with the output of T*m2 bit data bus.Control module control shift register group is inserted 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of T*m2 bit data bus that converts to and export with the synchronous frame alligning information of P*m1 bit bus that will receive simultaneously.T*m2 is similar to the T*m2 bus conversion module to P*m1 to the P*m1 bus conversion module, at first receive data by the T*m2 bit bus, deposit shift register group in, be input to buffer memory among the FIFO by the P*m1 bit data bus again, then with the output of P*m1 bit data bus.Control module control shift register group is inserted 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of P*m1 bit data bus that converts to and export with the synchronous frame alligning information of T*m2 bit bus that will receive simultaneously.
RS (n1, k1) the input/output bus width of coder is identical with symbol width, RS (n2, k2) the input/output bus width of half parallel encoding and decoding device be symbol width T doubly, do not relate to imperfect code element, can realize with traditional RS coding and decoding method, efficiently solve imperfect code element problem, unify the input/output interface between the different RS sign indicating numbers.
Realize the P road RS (n1 that interweaves simultaneously, k1) compound key and RS (n2, k2) system configuration of the RS coder of code coding/decoding function as shown in Figure 1, the P road interweave RS (n1, k1) encoder and RS (n2, k2) encoder adopts identical input/output interface, the P road RS (n1 that interweaves, k1) decoder and RS (n2, k2) decoder also adopts identical input/output interface, highway width all is the P*m1 bit.For encoder, the input data enter deliver to after the system P road interweave RS (n1, k1) encoder or RS (n2, k2) encoder is encoded, the data behind the coding are by the data/address bus output of P*m1 bit width.For decoder, the input data enter deliver to after the system P road interweave RS (n1, k1) decoder or RS (n2, k2) decoder is deciphered, the data after the decoding are the data/address bus output by the P*m1 bit width equally.
The P road interweaves, and (n1, k1) structure of encoder as shown in Figure 2 for RS.Data to be encoded are at first delivered to de-interleaving block 210 by P*m1 bit width input bus, deliver to P separate RS (n1 respectively by the data/address bus of P bar m1 bit width after the deinterleaving, k1) encoder is encoded, data behind the coding are delivered to interleaving block 220 and are interweaved, then by the output of P*m1 bit width data/address bus.The P road RS (n1 that interweaves, k1) structure of decoder is similar to encoder, as shown in Figure 3, data to be decoded are at first delivered to de-interleaving block 210 by P*m1 bit width input bus, deliver to P independently RS (n1 respectively by the data/address bus of P bar m1 bit width after the deinterleaving, k1) decoder is deciphered, and the data after the decoding are delivered to interleaving block 220 and interweaved, then by P*m1 bit width data/address bus output decoding back data.
RS (n2, k2) coder structure as shown in Figure 4, data to be encoded are at first delivered to P*m1 to T*m2 bus conversion module 410, insert bit 0 and fill, and the data/address bus of P*m1 bit width are converted to the data/address bus of T*m2 bit.T*m2 bit width data input RS (n2, k2) half parallel encoder is encoded, T code element of every clock parallel processing, each code element comprises the m2 bit, does not have imperfect code element to occur, and still adopts conventional RS encoder to realize.Data behind the coding at first output to T*m2 to P*m1 bus conversion module 420, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width are converted to the data/address bus output of P*m1 bit width.RS (n2, k2) structure of decoder and RS (n2, k2) structural similarity of encoder, as shown in Figure 4, data to decode is at first delivered to P*m1 to T*m2 bus conversion module 410, inserts bit 0 and fills, and the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit width.T*m2 bit width data input RS (n2, k2) half parallel decoder is deciphered, T code element of every clock parallel processing, each code element comprises the m2 bit.Data after the decoding at first output to T*m2 to P*m1 bus conversion module 420, remove the insertion bit in the information sets, the data/address bus of T*m2 bit width are converted to the data/address bus output of P*m1 bit width.Realize that for ease of hardware P*m1 bit width bus and T*m2 bit width bus adopt the clock of same frequency, whether the data that indicate on the bus with enable signal are effective simultaneously.If enable signal does not enable, P*m1 on the bus or T*m2 Bit data are invalid, otherwise effectively.
Usually, (n2, k2) highway width of encoder is RS
Bit, the block length of actual input is
Individual m2 bit symbol.Because insert the value that symbol bits 0 can not change the verification group in the information sets front, generally need before information sets, insert
-k2 symbol bits 0 need be inserted k2*m2-P*k1*m1 bit 0 at the information sets end simultaneously.With 16 tunnel RS (255 that interweave, 239) and RS (2720,2550) be example because RS (2720,2550) interface of encoder will with 16 tunnel RS (255 that interweave, 239) identical, the latter adopts the 128-bits input/output bus, imports 239 128-bits information sets and waits for clock cycle more than 16 later on, the output verification code element, RS (2720,2550) coding module must be finished the calculating of verification group in 239 clock cycle, each clock cycle receives
Individual 12-bits code element, 11 code elements of each clock cycle parallel processing of coding module, a code word needs
The individual clock cycle, actual treatment 232*11=2552 code element.But the information bit of a code element reality is 16*239*8=30592, adds fixing 8 bits of filling, and also needs to fill 2552*12-30592-8=24 bit (i.e. 2 code elements 0) and calculates.24 bits 0 are inserted into the code word front, and RS (2720,2550) code word has just become RS (2722,2552) code word.For with 16 tunnel RS (255, the 239) unanimities that interweave, 24 filling bits that are inserted into the code word front must be removed at the output of encoder, convert RS (2722,2552) code word to RS (2720,2550) code word.The interface of RS (2720,2550) decoder also will with 16 tunnel the identical of RS (255,239) that interweave, 255 clock cycle are received a RS (2720,2550) code word, each clock cycle needs parallel processing
Individual code element, the actual treatment time is
The individual clock cycle, actual treatment 248*11=2728 code element.So, before parallel decoding, need insert 0 (i.e. 6 code elements 0) of 6*12=72 bit in the RS that receives (2720,2550) code word front, convert thereof into RS (2728,2558) code word.
Fig. 6 for the P*m1 bit to T*m2 bit bus modular converter structure chart, FIFO is a wide T*m2 bit, dark
Memory.The register of the shift register group of 2*P*m1 bit is numbered from top to bottom and is followed successively by 0,1 ..., 2*P*m1.Pointer pointer points to the next position of current effective padding data in the bit shift register, and numbering is less than all there being valid data in the register of pointer, and numbering is empty more than or equal to the register of pointer.Pointer=w for example, then register 0 all has valid data in register w.If import valid data this moment, the P*m1 bit-order of input is placed on below the original remaining data, promptly is placed on register w in register w+P*m1-1, and pointer moves down, and points to register w+P*m1.If the valid data in the shift register surpass T*m2 bit (pointer pointer is more than or equal to T*m2), uppermost T*m2 Bit data is shifted out, will move the T*m2 bit on the remaining data simultaneously, pointer moves the T*m2 bit on also.If the data input is arranged when shifting out data, at first shift out data, adjust the remaining data position, the data that will newly import are put into below the remaining data in proper order then, adjust pointer according to new Data Position.Because as long as in the shift register Bit data above T*m2 is arranged, the top data will be shifted out, the data in the shift register can not surpass the 2*P*m1 bit all the time.
Clock cycle input modular converter have only the P*m1 bit at most, that exports modular converter may be the T*m2 bit, even the P*m1 bit data bus is imported continuously, T*m2 Bit data output can gapped (some clock cycle data enable, and expression is output not) yet.If gapped in the middle of the code word, can increase the complexity of coding, decoding greatly, so with FIFO to the data buffer memory, the enough data of first buffer memory a code word begins after, output continuously again, thereby the middle gap of removal code word.If the P*m1 bit data bus is imported (input all is continuous generally speaking) continuously, a code word needs n1 clock cycle, with the output of T*m2 bit data bus, needs continuously
The individual clock cycle, guarantee needs first buffer memory continuously
Bit data.When each code word initialization, shift register is made as 0, pointer is set simultaneously is
Insert
Individual bit 0 is to the information sets front; Behind input P*k1*m1 information bit, also need to add k2*m2-k1*m1 bit 0 to shift register., when shift register need be made as 0 pointer is set and is to the T*m2 modular converter for the P*m1 of decoder
Insert
Individual bit 0 is to the information sets front.Control module is by finishing the insertion of bit 0 to the control of pointer, it also controls FIFO simultaneously, frame alligning information is changed, input walked around and the synchronous frame alignment signal of T*m2 bit width data/address bus with the synchronous frame alignment signal of P*m1 bit width data/address bus.
T*m2 is similar to the T*m2 modular converter to P*m1 bus conversion module and P*m1, uses structure shown in Figure 7.The shift register group that comprises the 2*P*m1 bit is 0,1 with each register number from top to bottom successively ..., 2*P*m1-1.FIFO is that T*m2 bit, the degree of depth are by width
Memory constitute.Pointer pointer points to the next position of current effective padding data in the bit shift register, and numbering is less than all there being valid data in the register of pointer, and numbering is empty more than or equal to the register of pointer.This module at first receives data by the T*m2 bit data bus from coding module or decoding module, deposits among the FIFO.If have in the shift register above T*m2 register and be empty (pointer is less than 2*P*m1-T*m2), from FIFO, read the T*m2 Bit data, be placed in order in the shift register below the data with existing, adjust pointer simultaneously, point to the relevant position that deposits in after the data.If the valid data above the P*m1 bit are arranged in the shift register, by the output of P*m1 bit data bus, simultaneously remaining data is moved on to shift register top, adjust pointer.Usually be simultaneous from the FIFO read data with from the shift register dateout, at this moment at first export the P*m1 Bit data, adjust the remaining data position, order is deposited the data of reading in from FIFO below remaining data then, adjusts pointer.
To the T*m2 modular converter, it is top to lose each code word for the P*m1 of encoder
Bit filling value; To the T*m2 modular converter, it is top to lose each code word for the P*m1 of decoder
Bit filling value.
RS in the system (n1, k1) and RS (n2, k2) per clock cycle of coder is handled one or T code element, does not relate to imperfect code element, is conventional RS coder.
The present invention by bit 0 insertion and pick out, realized the mutual conversion between P*m1 and the T*m2 bit bus, avoided the generation of imperfect code element, solved the inconsistent imperfect code element problem that causes of data/address bus dexterously, realized the identical P of the interface road RS (n1 that interweaves, k1) compound key and RS (n2, k2) Ma coder.
Claims (7)
1, a kind of data/address bus conversion equipment is characterized in that, described data/address bus conversion equipment comprises
Two kinds of RS coders in system, realizing simultaneously, these two kinds of RS coders for the P road interweave RS (n1, k1) (these two kinds of RS coders all use the data/address bus of P*m1 bit width, and input/output interface is identical for n2, k2) sign indicating number for compound key and RS;
One interleaving block and a de-interleaving block, the described P road RS (n1 that interweaves, k1) compound key resolves into the data/address bus that the P road independently has the m1 bit width to the data/address bus of P*m1 bit width by this interleaving block and de-interleaving block, offer P separate RS (n1, k1) coder respectively;
One bus conversion module, described RS (n2, k2) coder is realized conversion between P*m1 bit data bus and the T*m2 bit data bus by this bus conversion module, provide T*m2 bit width data/address bus to RS (n2, k2) half parallel encoding and decoding device carries out T road parallel encoding and decoding;
Wherein (n1 k1) represents that the information code element number is k1 to RS, and the verification code element number is (n1-k1), and each code element comprises the RS sign indicating number of m1 bit; RS (n2, k2) expression information code element number is k2, and the verification code element number is (n2-k2), and each code element comprises the RS sign indicating number of m2 bit; T is RS (n2, k2) code element number of half parallel encoding and decoding device parallel processing.
2, data/address bus conversion equipment according to claim 1, it is characterized in that, described bus conversion module comprise P*m1 to T*m2 bus conversion module and T*m2 to the P*m1 bus conversion module, described P*m1 is used for receiving data by the P*m1 bit bus to the T*m2 bus conversion module, deposit a shift register group in, be input to buffer memory among the FIFO by the T*m2 bit data bus again, then with the output of T*m2 bit data bus;
One control module, be used to control described shift register group and insert 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of T*m2 bit data bus that converts to and export with the synchronous frame alligning information of P*m1 bit bus that will receive simultaneously.
3, data/address bus conversion equipment according to claim 1, it is characterized in that, described T*m2 is used for receiving data by the T*m2 bit bus to the P*m1 bus conversion module, deposit shift register group in, be input to buffer memory among the FIFO by the P*m1 bit data bus again, then with the output of P*m1 bit data bus;
Described control module control shift register group is inserted 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of P*m1 bit data bus that converts to and export with the synchronous frame alligning information of T*m2 bit bus that will receive simultaneously.
4, a kind of RS coder that uses data/address bus conversion equipment as claimed in claim 1 is characterized in that, described RS coder comprises
A P road of the Shi Xianing RS (n1 that interweaves simultaneously, k1) compound key and RS (n2, k2) the RS coder of code coding/decoding function, described P road interweave RS (n1, k1) encoder and RS (n2, k2) encoder adopts identical input/output interface, the described P road RS (n1 that interweaves, k1) (highway width all is the P*m1 bit for n2, k2) the identical input/output interface of decoder employing for decoder and RS.
5, RS coder according to claim 4 is characterized in that, described P road interweave RS (n1, k1) coder comprises an interleaving block and a de-interleaving block, is P road RS volume/decoder between this interleaving block and the de-interleaving block; For encoder, the input data enter to be delivered to the P road RS encoder that interweaves after the system and encodes, and the data behind the coding are by the data/address bus output of P*m1 bit width; For decoder, the input data enter to be delivered to the P road RS decoder that interweaves after the system and deciphers, and the data after the decoding are the data/address bus output by the P*m1 bit width equally.
6, according to claim 4 or 5 described RS coders, it is characterized in that, described RS (n2, k2) coder comprise a P*m1 to T*m2 bus conversion module and a T*m2 to the P*m1 bus conversion module, at this P*m1 to T*m2 bus conversion module and this T*m2 between the P*m1 bus conversion module being RS (n2, k2) volume/decoder; For encoder, data to be encoded are delivered to described P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit, T*m2 bit width data input RS (n2, k2) half parallel encoder is encoded, and the data behind the coding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width; For decoder, data to decode is at first delivered to P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit width, T*m2 bit width data input RS (n2, k2) half parallel decoder is deciphered, and the data after the decoding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width.
7, RS coder according to claim 6, it is characterized in that, described P*m1 bit width bus and T*m2 bit width bus adopt the clock of same frequency, whether the data that indicate on the bus with enable signal are effective simultaneously, if enable signal does not enable, P*m1 on the bus or T*m2 Bit data are invalid, otherwise effectively.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008019611A1 (en) * | 2006-08-11 | 2008-02-21 | Huawei Technologies Co., Ltd. | Forward error correction for 64b66b coded systems |
| WO2009076801A1 (en) * | 2007-12-14 | 2009-06-25 | Zte Corporation | Device and method for interlaced encoding rs code |
| CN104734815A (en) * | 2015-04-08 | 2015-06-24 | 烽火通信科技股份有限公司 | Hardware implementation method and system for FEC in OTN system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008019611A1 (en) * | 2006-08-11 | 2008-02-21 | Huawei Technologies Co., Ltd. | Forward error correction for 64b66b coded systems |
| US8122325B2 (en) | 2006-08-11 | 2012-02-21 | Futurewei Technologies, Inc. | Forward error correction for 64b66b coded systems |
| CN101455019B (en) * | 2006-08-11 | 2012-09-19 | 华为技术有限公司 | Forward error correction for 64b66b coded systems |
| CN102891731A (en) * | 2006-08-11 | 2013-01-23 | 华为技术有限公司 | Forward error correction for 64b66B coded systems |
| CN102891731B (en) * | 2006-08-11 | 2015-03-11 | 华为技术有限公司 | Forward error correction for 64b66B coded systems |
| WO2009076801A1 (en) * | 2007-12-14 | 2009-06-25 | Zte Corporation | Device and method for interlaced encoding rs code |
| US8279741B2 (en) | 2007-12-14 | 2012-10-02 | Zte Corporation | Device and method for interleaved encoding RS code |
| CN104734815A (en) * | 2015-04-08 | 2015-06-24 | 烽火通信科技股份有限公司 | Hardware implementation method and system for FEC in OTN system |
| CN104734815B (en) * | 2015-04-08 | 2018-01-23 | 烽火通信科技股份有限公司 | The Hardware Implementation and system of high-throughput FEC encoder in OTN system |
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