CN1787382A - Method for buffer area read-write by reducing buffer area size of on-line image compression data - Google Patents
Method for buffer area read-write by reducing buffer area size of on-line image compression data Download PDFInfo
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Abstract
This invention provides a method for reducing on-line compressed data buffer regions, in which, line-A data are written in a data buffer region first horizontally, a block process module carries out vertical read, the read small blocks can be organized to a vertical small block to carry out the successive vertical writing in and keep a new line of data, which can reasonably distribute a same buffer region to finish the function in one region which needed by two blocks originally to reduce the final chip area.
Description
Technical field
The present invention relates to a kind of method for buffer area read-write that reduces online image compression data buffering area.
Background technology
Most of still image compression standards (as JPEG, JPEG2000) and in the dynamic image compression standard (as MPEG1, MPEG2, MPEG4, H263 etc.), at first carry out the conversion of time domain to frequency domain to the initial data of image, frequency-region signal are compressed again.Wherein time domain has a common characteristic to the conversion of frequency domain: the piece (as 8 * 8, totally 64 pixels) to a certain size carries out conversion.In addition, in some standard, (Minimum Code Unit MCU), requires the data of each MCU of acquisition, is the piece of 16 * 16 pixels as the image M CU of JPEG YUV4:2:0 to also have the restriction of minimum code unit.Computing or processing module that we claim DCT etc. that a certain size piece in the image is operated successively are " piece processing module ".
The data that digital camera sensor produces are that delegation's transmission is followed by delegation, and JPEG carries out discrete cosine transform (Discrete Cosine Transform, DCT) be to be that unit is operated during conversion, so DCT need use the data of 8 row simultaneously with 8 * 8 fritter.For size is the design that two buffering areas are adopted in the general online DCT packed data buffering area design of 1280 * 1024 1,300,000 pixels image, (each buffering area can be stored the 8 row data of totally 8 * 1280 pixels), the read-write (promptly from a buffering area reading of data that is ready to 8 line data time, need another block buffer to prepare 8 follow-up line data) of rattling provides 8 * 8 data cell for DCT.The table tennis read-write mode of two buffering areas as shown in Figure 1, wherein, → expression " writing " process, and
The process of expression " reading ".
The buffering area that such design needs is big, thereby causes the integrated circuit chip area that designs bigger, thereby cost is also high.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method that reduces the online DCT packed data of mega pixel buffer size, this method can be carried out the reasonable distribution of subregion and read-write cleverly to same block buffer, can store 8 row at one and finish the function that needs two block buffers to finish originally in the buffering area of totally 8 * 1280 pixel datas, reduce final chip area and product cost.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of method for buffer area read-write that reduces online image compression data buffer size is provided, it obtains providing for the piece processing module blocks of data of A * N from line data, wherein A, N can be any natural number, comprise the steps: at first buffering area to be divided into A * A five equilibrium;
Step 1: the input data that the logarithmic code camera sensor obtains are carried out level and are write, and up to writing the capable 1/A line data of A, buffering area can only be write during this period of time, can not be read;
Step 2: digital camera sensor is in writing the capable residual A of A-1/A line data process, and the piece processing module is read away the vertical fritter row of first left.
Step 3-5: the state that buffering area enters vertically from step 2 and writes, vertically reads, through the read-write of A-1 vertical fritter row, to vertically reading away last row;
Step 6: vertically be written in the capable preceding 1/A line data process of 2A when importing data, buffering area can only be write, and can not be read;
Step 7: write in capable remaining (the A-1)/A line data process of 2A when the input data, the piece processing module need be with capable reading away of horizontal fritter of the top;
Step 8-10: buffering area is from step 7 level of entering is write, level is read state.Through A-1 the capable read-write of horizontal fritter, read away last column to level;
Step 11: write in the capable preceding 1/A line data process of 3A when importing data level, buffering area can only be write, and can not be read;
Step 12: the read-write state of buffering area is got back to similar step 2 again, thus finish the 2A line data convert the process of A * A block of pixels data to from line data.
Further, the method for buffer area read-write that the present invention also provides another kind to reduce online image compression data buffer size, it obtains providing for the piece processing module blocks of data of B * N from line data, wherein, B, N can be any natural number, comprises the steps: at first buffering area to be divided into B * C five equilibrium, and B represents line number, C represents columns, wherein C is greater than B, and B and C be the power of S, and S is the natural number greater than 1;
Step 1: the input data that the logarithmic code camera sensor obtains are carried out level and are write, and up to writing the 1st capable fritter of B, buffering area can only be write during this period of time, can not be read;
Step 2: digital camera sensor is after writing the 1st capable fritter of B, and the piece processing module is read away the 1st vertical fritter.Digital camera sensor is after writing the 2nd capable fritter of B, and the piece processing module can be read away by the 2nd vertical fritter row.Before digital camera sensor began to write the 1st fritter of (B+1) row, the piece processing module must be read away the 1st vertical fritter row.
Step 3: after this, the piece processing module is read away vertical fritter row successively, reads away until last vertical fritter row that this B is capable.Whenever read away vertical fritter row, digital camera sensor can vertically write the capable pixel data of B/C, altogether B fritter.For the race-card after remapping, digital camera sensor is the pixel data that level writes the capable image of next B.
Step 4: during digital camera sensor write the 1st capable fritter of 2B, buffering area can only be write, and can not be read;
Step 5: remap race-card, the read-write state of buffering area is got back to similar step 2 again, thus finish the B line data convert the process of B * N block of pixels data to from line data.
The present invention supports online DCT compression, does not improve under the situation of requirement of DCT disposal ability, makes required buffering area be reduced to half of general design.
Description of drawings
Fig. 1 is existing ping-pong buffer read-write schematic diagram;
Fig. 2 is a rotation buffering area partitioned organization of the present invention;
Fig. 3 is a rotation buffer area read-write state transition graph.
Embodiment
As shown in Figure 2: (area is: 8 * 1280) by level and vertical direction difference 8 five equilibriums, form 64 fritters of five equilibrium, each fritter can be stored the data of 160 pixels to buffering area of the present invention.When level write data, 8 fritters of level can be formed a horizontal fritter, preserved data line.After level write 8 line data, DCT carried out vertical reading, and 8 fritters that vertically read can be formed a vertical fritter, can carry out vertically writing of subsequent rows, preserved the new data of delegation.
As shown in Figure 3: the read-write operation method of buffering area of the present invention comprises the steps:
Step 1: the input data that transducer is obtained are carried out level and are write, and up to 1/8 line data that writes eighth row, buffering area can only be write during this period of time, can not be read;
Step 2: digital camera sensor is in writing the remaining 7/8 line data process of eighth row, and the DCT module is read away 8 * 160 pixel datas of the vertical fritter row of first left.
Step 3-5: the rotation buffering area enters vertically the state of writing, vertically reading from step 2, through the read-write of seven vertical fritter row, to vertically reading away last row;
Step 6: vertically be written in the 16th preceding 1/8 line data process of going when importing data, buffering area can only be write, and can not be read;
Step 7: when the input data are write in the remaining 7/8 line data process of the 16th row, what the DCT module was need be with a horizontal fritter of the top capable 8 * 160 reads away;
Step 8-10: the rotation buffering area is from step 7 level of entering is write, level is read state.Through seven capable read-writes of horizontal fritter, read away last column to level;
Step 11: write in the 24th preceding 1/8 line data process of going when importing data level, buffering area can only be write, and can not be read;
Step 12: the read-write state of rotation buffering area is got back to similar step 2 again, thus finish 16 line data convert the process of 8 * 8 block of pixels data to from line data.
Among the figure, the process of → expression " reading ", and
The process of expression " writing ".
Above specific embodiment is set forth a kind of method for buffer area read-write that reduces online image compression data buffering area to be example among the JPEG, but the present invention does not limit to JPEG, is not limited to DCT yet.
Protection scope of the present invention is not limited to above concrete execution mode, such as, the present invention is not limited to 8 * 8 data cells, and the present invention can also be applicable to:
1) obtains providing 16 * 16 data cell (to the image of YUV:2:0, the minimum code unit of JPEG is the fritter of 16 * 16 pixels) from line data for DCT;
In this case, we need one can store the 16 row buffering area of totally 16 * 1280 pixel datas, and every row is divided into 16 fritters (the every data that comprise 80 pixels), totally 16 * 16 fritters.The read-write operation of 16 * 16 fritters, similar 8 * 8 fritters.
2) obtain providing the blocks of data (A, N can be any natural number) of A * N from line data for the piece processing module; Suppose that there be L pixel in delegation, we need one can store the capable buffering area of A * L pixel data altogether of A, and every row is divided into A fritter, altogether A * A fritter (every data that comprise L/A pixel, L must be the integral multiple of A*N).The read-write operation of A * A fritter, similar 8 * 8 fritters.
3) obtain providing the blocks of data (B, N can be any natural number) of B * N from line data for the piece processing module; Suppose that there be L pixel in delegation, we need one can store the capable buffering area of B * L pixel data altogether of B, and every row is divided into C fritter, altogether B * C fritter (every data that comprise L/C pixel, L must be the integral multiple of C*N, and C must be the integral multiple of B).Realize that for the ease of ASIC B and C are 2 power usually.In theory, B and C are that the power of S gets final product (S for greater than 1 natural number).
Following example is: buffering area is divided into 4 * 8 fritters, and so that the data block S0 of 4 * N to be provided, S1 ..., S31 represents 32 fritters.Whenever write the B line data, the position of each fritter in the capable image of B passed through once and remapped.For B among B * C and the equal situation (i.e. the situation of Yi Shang A * A) of C, remapping on figure is that horizontal line is mapped as vertical row, or horizontal line is mapped as vertical row.For B among B * C and the unequal situation of C, because buffering area need just can return initial condition through remapping greater than 2 times, so can't be vertical with buffering area on figure, two kinds of read-write states of level represent.Therefore, our result that will at every turn remap is illustrated in the following form.
Initial order (order 1) is
| S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 |
| S8 | S9 | S10 | S11 | S12 | S13 | S14 | S15 |
| S16 | S17 | S18 | S19 | S20 | S21 | S22 | S23 |
| S24 | S25 | S26 | S27 | S28 | S29 | S30 | S31 |
Table 1: order 1
The input data that transducer is obtained write by the horizontal order of table 1, and then the position of the pixel data of each fritter storage in first 4 row image is just as shown in table 1.Digital camera sensor behind the 1st fritter S24 that writes table 1 the 4th row, the piece processing module can with the 1st the vertical fritter in table 1 left side S0, S8, S16, S24} reads away.Digital camera sensor behind the 2nd fritter S25 that writes table 1 the 4th row, the piece processing module can with the 2nd the vertical fritter row in table 1 left side S1, S9, S17, S25} reads away.
After this, the piece processing module is read away the vertical fritter row of table 1 successively.Whenever read away one, digital camera sensor can vertically write the hemistich pixel data.Hemistich is followed hemistich and is vertically write pixel data in table 1, is equivalent in table 2 to write by horizontal order.So then the position of the pixel data of each fritter storage in second 4 capable image is just as shown in table 2.
When the piece processing module is read away the vertical fritter row of in the table 1 the 8th, digital camera sensor can write the 7th vertical fritter row in the table 1 S6, S14, S22, S30} is equivalent to write the 4th preceding hemistich that horizontal fritter is capable in the table 2.
| S0 | S8 | S16 | S24 | S1 | S9 | S17 | S25 |
| S2 | S10 | S18 | S26 | S3 | S11 | S19 | S27 |
| S4 | S12 | S20 | S28 | S5 | S13 | S21 | S29 |
| S6 | S14 | S22 | S30 | S7 | S15 | S23 | S31 |
Table 2: order 2
Digital camera sensor behind the 1st fritter S6 that writes table 2 the 4th row, the piece processing module can with the 1st vertical fritter of left side table 2 S0, S2, S4, S6} reads away.Digital camera sensor behind the 2nd fritter S14 that writes table 2 the 4th row, the piece processing module can with the 2nd the vertical fritter row in table 2 left side S8, S10, S12, S14} reads away.
After this, the piece processing module is read away the vertical fritter row of table 2 successively.Whenever read away one, digital camera sensor can vertically write the hemistich pixel data.Hemistich is followed hemistich and is vertically write pixel data in table 2, is equivalent in table 3 to write by horizontal order.So then the position of the pixel data of each fritter storage in the 3rd 4 capable image is just as shown in table 3.
When the piece processing module is read away the vertical fritter row of in the table 2 the 8th, digital camera sensor can write the 7th vertical fritter row in the table 2 S17, S19, S21, S23} is equivalent to write the 4th preceding hemistich that horizontal fritter is capable in the table 3.
| S0 | S2 | S4 | S6 | S8 | S10 | S12 | S14 |
| S16 | S18 | S20 | S22 | S24 | S26 | S28 | S30 |
| S1 | S3 | S5 | S7 | S9 | S11 | S13 | S15 |
| S17 | S19 | S21 | S23 | S25 | S27 | S29 | S31 |
Table 3: order 3
By that analogy, the position relation of each fritter of buffering area in 4 row images successively from table 3, table 4, table 5, got back to table 1 again.
| S0 | S16 | S1 | S17 | S2 | S18 | S3 | S19 |
| S4 | S20 | S5 | S21 | S6 | S22 | S7 | S23 |
| S8 | S24 | S9 | S25 | S10 | S26 | S11 | S27 |
| S12 | S28 | S13 | S29 | S14 | S30 | S15 | S31 |
Table 4: order 4
| S0 | S4 | S8 | S12 | S16 | S20 | S24 | S28 |
| S1 | S5 | S9 | S13 | S17 | S21 | S25 | S29 |
| S2 | S6 | S10 | S14 | S18 | S22 | S26 | 30 |
| S3 | S7 | S11 | S15 | S19 | S23 | S27 | S31 |
Table 5: order 5
More than 5 tables have very strong internal relation, can be very easily realize with the bit cyclic shift in the ASIC design.
At first, with the piece N of arbitrary fritter (0,1,2 ..., 31) and be shown the number of 5 bits with binary form
N＝16*n4+8*n3+4*n2+2*n1+n0
(n4 wherein, n3, n2, n1, the n0 value is 1 or 0)
If the coordinate of arbitrary fritter in one 4 capable image be (X, Y), X=0 wherein, 1 ..., 7, Y=0,1 ..., 3.The binary form of X is shown the number of 3 bits, and the binary form of Y is shown the number of 2 bits.
X＝4*x2+2*x1+x0
(the x0 value is 1 or 0 for x2 wherein, x1)
Y＝2*y1+y0
(wherein y1, the y0 value is 1 or 0)
N in the table 1 with (X, corresponding relation Y) can be represented by the formula:
{y1，y0，x2，x1，x0}＝{n4，n3，n2，n1，n0}
2 of cyclic shifts, N and (X, corresponding relation Y) in can table 2
{y1，y0，x2，x1，x0}＝{n2，n1，n0，n4，n3}
2 of recirculation displacements, N and (X, corresponding relation Y) in can table 3
{y1，y0，x2，x1，x0}＝{n0，n4，n3，n2，n1}
2 of recirculation displacements, N and (X, corresponding relation Y) in can table 4
{y1，y0，x2，x1，x0}＝{n3，n2，n1，n0，n4}
2 of recirculation displacements, N and (X, corresponding relation Y) in can table 5
{y1，y0，x2，x1，x0}＝{n1，n0，n4，n3，n2}
N and (X, corresponding relation Y) in the table 1 are got back in 2 of recirculation displacements again
{y1，y0，x2，x1，x0}＝{n4，n3，n2，n1，n0}
As seen, for buffering area being divided into B * C fritter (C must be the integral multiple of B), and B and C be the situation of 2 power, and buffering area remapping logically can be easily realized with the bit cyclic shift of piece number (being the address in the ASIC design).
Usually, for buffering area being divided into B * C fritter (C must be the integral multiple of B), and B and C be the situation of the power (S for greater than 1 natural number) of S, establishes
B=S
b, C=S
c, b wherein, c is a natural number, and b＜c.If b, the greatest common factor (G.C.F.) of c is g.
After then buffering area need pass through (b+c)/g time and remaps, can get back to initial order.
Claims (4)
1, a kind of method for buffer area read-write that reduces online image compression data buffer size, it is characterized in that, obtain providing for the piece processing module blocks of data of AxN from line data, wherein A, N can be any natural number, comprise the steps: at first buffering area to be divided into the AxA five equilibrium;
Step 1: the input data that the logarithmic code camera sensor obtains are carried out level and are write, and up to writing the capable 1/A line data of A, buffering area can only be write during this period of time, can not be read;
Step 2: digital camera sensor is in writing the capable residual A of A-1/A line data process, and the piece processing module is read away the vertical fritter row of first left.
Step 3-5: the state that buffering area enters vertically from step 2 and writes, vertically reads, through the read-write of A-1 vertical fritter row, to vertically reading away last row;
Step 6: vertically be written in the capable preceding 1/A line data process of 2A when importing data, buffering area can only be write, and can not be read;
Step 7: write in capable remaining (the A-1)/A line data process of 2A when the input data, the piece processing module need be with capable reading away of horizontal fritter of the top;
Step 8-10: buffering area is from step 7 level of entering is write, level is read state.Through A-1 the capable read-write of horizontal fritter, read away last column to level;
Step 11: write in the capable preceding 1/A line data process of 3A when importing data level, buffering area can only be write, and can not be read;
Step 12: the read-write state of buffering area is got back to similar step 2 again, thus finish the 2A line data convert the process of AxN block of pixels data to from line data.
2, a kind of method for buffer area read-write that reduces online image compression data buffer size is characterized in that, described A is 8 or 16.
3, a kind of method for buffer area read-write that reduces online image compression data buffer size is characterized in that, the blocks of data of BxN is provided providing for the piece processing module from line data, wherein, B, N can be any natural number, comprise the steps: at first buffering area to be divided into the BxC five equilibrium, B represents line number, and C represents columns, and wherein C is greater than B, and B and C are the power of S, S is the natural number greater than 1, (suppose that there be L pixel in delegation, then L must be the integral multiple of C*N);
Step 1: the input data that the logarithmic code camera sensor obtains are carried out level and are write, and up to writing the 1st capable fritter of B, buffering area can only be write during this period of time, can not be read;
Step 2: digital camera sensor is after writing the 1st capable fritter of B, and the piece processing module is read away the 1st vertical fritter.Digital camera sensor is after writing the 2nd capable fritter of B, and the piece processing module can be read away by the 2nd vertical fritter row.Before digital camera sensor began to write the 1st fritter of (B+1) row, the piece processing module must be read away the 1st vertical fritter row.
Step 3: after this, the piece processing module is read away vertical fritter row successively, reads away until last vertical fritter row that this B is capable.Whenever read away vertical fritter row, digital camera sensor can vertically write the capable pixel data of B/C, altogether B fritter.For the race-card after remapping, digital camera sensor is the pixel data that level writes the capable image of next B.
Step 4: during digital camera sensor write the 1st capable fritter of 2B, buffering area can only be write, and can not be read;
Step 5: remap race-card, the read-write state of buffering area is got back to similar step 2 again, thus finish the B line data convert the process of BxN block of pixels data to from line data.
4, a kind of method for buffer area read-write that reduces online image compression data buffer size is characterized in that, described B, C are 2 power.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158717A (en) * | 2010-02-11 | 2011-08-17 | 原相科技股份有限公司 | Data conversion method and data conversion device |
| CN109933560A (en) * | 2019-03-21 | 2019-06-25 | 南京威翔科技有限公司 | A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory |
| CN112801852A (en) * | 2015-01-22 | 2021-05-14 | 谷歌有限责任公司 | Virtual linebuffer for image signal processor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8414109D0 (en) * | 1984-06-02 | 1984-07-04 | Int Computers Ltd | Data reorganisation apparatus |
| JP3081538B2 (en) * | 1996-08-28 | 2000-08-28 | 三洋電機株式会社 | Digital still camera |
| WO1998037558A2 (en) * | 1997-02-21 | 1998-08-27 | Koninklijke Philips Electronics N.V. | Method of and arrangement for recording and reproducing video images |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158717A (en) * | 2010-02-11 | 2011-08-17 | 原相科技股份有限公司 | Data conversion method and data conversion device |
| CN102158717B (en) * | 2010-02-11 | 2013-09-18 | 原相科技股份有限公司 | Data conversion method and data conversion device |
| CN112801852A (en) * | 2015-01-22 | 2021-05-14 | 谷歌有限责任公司 | Virtual linebuffer for image signal processor |
| CN112801852B (en) * | 2015-01-22 | 2022-05-31 | 谷歌有限责任公司 | Processor and method for image processing |
| CN109933560A (en) * | 2019-03-21 | 2019-06-25 | 南京威翔科技有限公司 | A kind of intermodule flow control communication means based on FIFO in conjunction with random access memory |
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Effective date of registration: 20161201 Address after: 361015 Xiamen Fujian torch hi tech Zone Pioneering Park Cheng Yip Building Room 201 Patentee after: Xiamen Ziguang exhibition Rui Technology Co. Ltd. Address before: 201203 Shanghai City Songtao road Pudong Zhangjiang hi tech Park No. 696 3-5 Patentee before: Zhanxun Communication (Shanghai) Co., Ltd. |