CN1783332A - Reading and writing method of double speed dynamic random access memory - Google Patents
Reading and writing method of double speed dynamic random access memory Download PDFInfo
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Abstract
The read/write method of double speed DRAM in the computer field includes the following steps: constantly judging whether to have data to be written in or read out after the double speed DRAM enters to its normal operation mode; pre-storing the data to be stored in the double speed DRAM in one FIFO buffer memory; always judging whether to have data in the FIFO buffer memory during the write operation on the double speed DRAM and always performing the write operation on the double speed DRAM when there are some data or judging whether to perform read operation when there are no data; performing data reading out operation similarly; and setting the read/write burst length as one fixed number in the double speed DRAM controller. The present invention can raise the access efficiency on double speed DRAM and simplify the control on access of double speed DRAM.
Description
Technical field
The present invention relates to field of data storage, specifically, relate to a kind of method of flexible raising DDRSDRAM access control efficient.
Background technology
DDR SDRAM (Double-Data-Rate SDRAM, double speed dynamic random access memory) is a kind of high speed dram, present amount of capacity has 64Mb, 128Mb, 256Mb, sequence such as 512Mb and 1Gb, its range of application is very extensive, and modal is to be used in the personal computer and the Internet communication system.The raising of PC performance needs the storer that speed is faster, efficient is higher and but the bigger price of capacity is more cheap.In network communication market, provide more performance to need higher data bandwidth equally, still desirability can better storer for this.DDR SDRAM is as pack buffer (usually need store complete bag in storer when network processor sends a header packet information) in the topmost purposes of field of network communication.
The Double Data Rate framework of DDR SDRAM is based on can transmit two data in a clock, thereby the data volume that the same clock period is transmitted is the twice of SDR SDRAM (Single-Data-RateSDRAM), then identical as for addressing with SDR SDRAM with control signal, as can be seen, under same address and order control, DDR SDRAM can provide higher data rate.Single read or write to DDR SDRAM is divided into two parts, Yi Bian be the data of a clock transmission 2n bit wide in control circuit, another side is in twice data with half clock period transmission n bit wide of I/O mouth.The address of DDR SDRAM comprises three aspects: page or leaf (Bank), row (Row) and row (Column).
Bidirectional data strobe signal (DQS) transmits with bi-directional data, is used for obtaining data at receiving end.Send by DDR SDRAM during read operation, send by memory controller during write operation.Bidirectional data strobe signal is alignd with the edge of data when read operation, aligns with the mid point of data during write operation.DDRSDRAM operates (CK and CK, CK uprise and the just jumping that is called CK during the CK step-down along) with a pair of anti-phase clock.Order (address and control signal) is latched on the just jumping edge of CK.Import just jumping edge and negative jump along latch the two edges of output data while reference bi data strobe signal and the two edges of CK of data in bidirectional data strobe signal.Read and write operation to DDR SDRAM all is happen suddenly (Burst), from a certain position, carries out the access of a preseting length continuously.Access then is to read or write order from activating (ACTIVE) order.The address bit of depositing simultaneously with activation command is used for selecting page or leaf and row, and reads (READ) or writes the begin column address that address bit that (WRITE) order deposits simultaneously is used to select page address and burst access.Between two orders of DDR SDRAM, generally need certain time interval, for example to reading or writing the shortest time requirement is arranged the order from activation command, promptly be activated to read-write time delay (' RCD), after sending an activation command, need to satisfy just can send the time delay that is activated to read-write reading or writing order, as Fig. 1, different DDR SDRAM has the different time delay that is activated to read-write.Undoubtedly, these orders that must guarantee in design have reduced the access efficiency of DDR SDRAM interval time.It is 2,4 or 8 that DDR SDRAM provides configurable burst-length.Auto-precharge (AUTO PRECHARGE) function begins precharge to be provided at after burst access finishes automatically.The same with SDR SDRAM, the DDR SDRAM of pipeline system, multipage structure allows parallel work-flow, thereby higher effective bandwidth can be provided by the time of hidden rows precharge and activation.The cost performance that DDR SDRAM is superior makes it obtain use more and more widely, how to obtain higher efficient and just causes great concern.
DDR SDRAM must be through an initialization procedure before normal running.Tell about the details of device initialization, register definitions, command description and device operation below.
Initialization procedure is as follows: clock enable signal (CKE) remains low in the power up, to guarantee that the output of data and bidirectional data strobe signal is in high-impedance state, up to being driven (read operation) by normal mode of operation, after all power supplys and reference power source and clock stable, DDRSDRAM needs the time delay of 200us before receiving order, in case 200us postpones to be met, use DESELECT or NOP (NO OPERATION) order, and draw high the clock enable signal.After the nop command, use PRECHARGE ALL and order, afterwards extended mode register is ordered with MODEREGISTER SET again, enable DLL, again mode register is ordered the DLL that resets, and configures operation parameters with MODE REGISTERSET.
DLL reset and any thereafter executable order between need 200 clock period, use PRECHARGE ALL order, make all pages or leaves of DDR SDRAM be in free time (1DLE) state.In case enter idle condition, must carry out two and refresh (AUTO REFRESH) cycle automatically.In addition, must carry out MODE REGISTER SET order, the DLL position that wherein resets invalid (i.e. configures operation parameters under the situation of the DLL that do not reset) to mode register.Last DDR SDRAM enters normal mode of operation.
Under normal mode of operation, DDR SDRAM is carried out read-write operation, at first need to activate page or leaf and the row of DDRSDRAM, satisfy just can send after the regular hour and read or write order carries out the reading and writing operation to DDRSDRAM, after the reading and writing EO, can close the row of activation at once, also can select to allow this delegation keep activating, but if another row of this one page is carried out the reading and writing operation, just must close the row that has activated.These activate, shutoff operation has reduced the access efficiency of DDR SDRAM, yet but usually has been indispensable in actual applications.
In general design, in order flexibly DDR SDRAM to be carried out the reading and writing operation, usually be made as the reading and writing burst-length configurable, when the data of 4 2n bit wides are arranged, just length is made as 8, when the data of 2 2n bit wides are arranged, just length is made as 4, when the data of 1 2n bit wide are arranged, just length is made as 2.But frequent is configured DDR SDRAM, can reduce the access efficiency of DDR SDRAM, needs holding time because DDR SDRAM is configured, and need be in all pages or leaves and provisional capital and just can carry out when closing.
The read-write burst-length fixedly is made as 8 and can raises the efficiency, but this also has a lot of shortcomings, be not a kind of can blanket method because DDR SDRAM can only stop read command, can not stop write order.So DDR SDRAM is carried out write operation one time, need prepare the data of 4 2n bit wides in advance, if the data of 4 2n bit wides of less than so just must be waited for just and can write DDR SDRAM to remaining data always, this is a cost to sacrifice reaction velocity usually.In addition, we have a look the read-write burst-length are made as the efficient of carrying out a read operation at 8 o'clock.Concerning DDRSDRAM, finish once complete read operation and need three orders: activate, read and precharge (PRECHARGE) order, should precharge command wherein be not all to be essential at every turn, read if can guarantee next time, write data is also in this delegation of this one page, read for twice so, can not need precharge command between the write order, secondary reading, write order can also save activation command, but this situation very desirable a kind of situation of can only saying so in design, can only be as special case, what often run in the design in data communication field is usually to need read/write address ceaselessly at different pages or leaves, conversion in the ranks.
When being operated in 100MHz, the read-write burst-length is made as 8 complete read operation sequential chart as shown in Figure 2, usually, when DDR SDRAM is operated in 100MHz, activation command is to two clock period of the minimum needs of read command, it is two clock period (CL=2) that read command appears at time on the bus minimum to data, and precharge command needs two clock period, so the synoptic diagram of read operation such as Fig. 2.CMD is COMMAND among Fig. 2, and ACT is ACTIVE, and PRE is PRECHARGE, and NOP is the abbreviation of NO OPERATION, and DQ is data.
Can calculate from Fig. 2, the efficient of read operation is: 4/ (4+5)=44.44%, 4 in the following formula are meant the data of 4 2n bit wides of reading, and are equivalent to 4 clock period that D1～D8 of Fig. 2 takies.
In addition, time by hidden rows precharge and activation in design also can provide higher effective bandwidth, this method a row in the page or leaf of DDR SDRAM is sent read or write order after, activate now certain delegation of another page, thereby the time that can save an activation command is so in some cases improved read-write efficiency, but this has increased the complexity and the difficulty of design, because the command interface that DDRSDRAM provides, data-interface and address interface are unique, therefore activating different pages or leaves and row simultaneously need control on sequential in strictness, otherwise will cause the conflict on data bus, this is that we are unwilling to see.Another aspect, this also has higher requirement at the storage policy between same page not to data, and has strengthened the difficulty in checking.Verify that at present the time shared in ASIC and FPGA design is more and more longer, the difficulty of artificial again increasing checking should not be a kind of desirable method.
To the present situation of present DDR SDRAM with on the raising method on the efficient, though DDR SDRAM has very high cost performance, go back more complicated in the use from top, the common method of raising the efficiency also has significant limitation, does not have ubiquity.And in the data communication field, higher efficient means more performance, and therefore, the efficient that improves DDR SDRAM simply and flexibly is the key problem in the DDR SDRAM use always.
Summary of the invention
Technical matters to be solved by this invention is to overcome in the prior art to use that DDR SDRAM efficient is not high, DDR SDRAM control complicated problems, in the hope of proposing a kind of flexible raising DDR SDRAM efficient, simplifying the reading/writing method of the double speed dynamic random access memory of controlling.
The reading/writing method of double speed dynamic random access memory provided by the invention may further comprise the steps:
(1) after DDR SDRAM enters normal mode of operation, judges whether to have the data that need write or read always,, then change step (2), if sense data is then changeed step (3) if write data;
(2) need write among the data in advance FIFO of existence (First_inFirst_out) of DDR SDRAM, DDR SDRAM is being carried out in the process of write operation, judge always whether data are arranged among the FIFO, if data are arranged then DDR SDRAM is carried out write operation always, as there are not data then to judge whether to carry out read operation;
(3) whether DDR SDRAM is being carried out in the process of read operation, judge has data always among the DDR SDRAM, if data are arranged then DDR SDRAM is carried out read operation always, as does not have data then to judge whether to carry out write operation;
It is characterized in that, in the DDR sdram controller, the read-write burst-length is made as a fixed numbers, same when capable when the same one page that is operated in DDR SDRAM, send the reading and writing order continuously according to actual design.
Described fixed numbers is 2.
In practice,, make reading and writing operate in the time that respectively takies half in theory, can the number of times that carry out read operation or write operation continuously be limited for balance reading and writing operation.
Writing data procedures specifically may further comprise the steps:
(1) need write among FIFO of data in advance existence of DDR SDRAM, when data, send write request to DDR SDRAM control module;
(2) receive the write request of FIFO when DDR SDRAM control module, send activation command and page address and row address, activate corresponding page or leaf of DDR SDRAM and row to DDR SDRAM;
(3) activation command that needs through DDR SDRAM itself sends write order and column address to DDR SDRAM after the time delay of read write command;
(4) continuous write operation maximum times or the column address in a row that has not had data among the FIFO or reached setting reaches maximal value, sends the blank operation order to DDR SDRAM, makes DDRSDRAM jump out write operation;
(5) send precharge command to DDR SDRAM, close page or leaf and row that write operation is opened.
The sense data process specifically may further comprise the steps:
(1) judges whether DDR SDRAM exists data, do not have data then not carry out read operation, have data then to change corresponding read operation order over to;
(2) send activation command and page address and row address to DDR SDRAM, activate corresponding page or leaf of DDRSDRAM and row;
(3) send read command and column address to DDR SDRAM after the time delay that is activated to read-write that process DDR SDRAM itself needs;
(4) continuous read operation maximum times or the column address in a row that has not had data among the DDR SDRAM or reached setting reaches maximal value, sends the blank operation order to DDR SDRAM, makes DDR SDRAM jump out read operation;
(5) send precharge command to DDR SDRAM, close page or leaf and row that read operation is opened.
In the method for the invention, DDR SDRAM is carried out read operation continuously or carries out write operation continuously, can save like this and activate and precharge command, compared with prior art, the invention enables to the control of DDRSDRAM is simple more that flexibly, storage efficiency is higher, the number of times of continuous read write command is adjusted into 64, the most effective of DDR SDRAM can reach 92.75% so, and do not increase extra cost.
Description of drawings
Fig. 1 is the time interval relation of activation and activation command and read/write command.
Fig. 2 is that the read-write burst-length is 8 complete read operation sequential chart.
Fig. 3 is the method for the invention schematic flow sheet.
Fig. 4 is that the read-write burst-length is 2, sends the sequential chart of 5 read commands continuously.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The reading/writing method of flexible raising DDR SDRAM efficient of the present invention is as follows:
Core methed is: in the DDR sdram controller, the read-write burst-length fixedly is made as 2, same when capable when the same one page that is operated in DDR SDRAM, send the reading and writing order continuously according to actual design, save and activate and the precharge command time, thus the storage efficiency of raising DDR SDRAM.
In order to realize to send the reading and writing order continuously, need after entering normal mode of operation, DDR SDRAM judge whether to exist the data that need write or read always.The data in advance that need write DDRSDRAM exists among the FIFO (First_in First_out), DDRSDRAM is being carried out in the process of write operation, judge always whether data are arranged among the FIFO, if data are arranged then DDR SDRAM is carried out write operation always, as there are not data then to judge whether to carry out read operation; Whether DDR SDRAM is being carried out in the process of read operation, judge has data always among the DDR SDRAM, if data are arranged then DDR SDRAM is carried out read operation always, as does not have data then to judge whether to carry out write operation.In practice,, make reading and writing operate in the time that respectively takies half in theory, can the number of times that carry out read operation or write operation continuously be limited for balance reading and writing operation.Such as the maximum times of setting continuous write operation is 64, after DDR SDRAM having been carried out continuously 64 write operations, even also have data among the FIFO, also no longer carries out write operation, and goes to judge whether DDR SDRAM needs to carry out read operation so.After DDR SDRAM has been carried out 64 read operations,, also no longer carry out read operation, and go to judge whether DDR SDRAM needs to carry out write operation even also have data among the DDR SDRAM.Complete read-write control operation as shown in Figure 3.
In this method, DDR SDRAM is carried out read operation continuously or carries out write operation continuously, can save like this and activate and precharge command, Fig. 4 is that the read-write burst-length is 2, send the sequential chart of 5 read commands continuously, come out to form a complete read operation from act command data D10 to the end.The efficiency calculation of DDR SDRAM is: 5/ (5+5)=50%.Here can not embody the advantage of algorithm, but continuous read command number of times is when reaching 32 times, the efficient of DDR SDRAM just is: 32/ (32+5)=86.49%, this efficient have been that the read-write burst-length is the twice of 8 efficient.If the number of times of read command continuously is adjusted into 64, the efficient of DDR SDRAM just is 92.75% so.The more important thing is, this method has overcome and the read-write burst-length has been made as some shortcomings of 8, reduced the difficulty of DDR SDRAM control, the read-write burst-length is 8 o'clock, the data that need 4 2n bit wides just can be carried out write operation to DDR SDRAM, as long as present this method has the data of a 2n bit wide, just can carry out write operation to DDR SDRAM, reduced the time of waiting pending data.
Fig. 1 is the time interval relation of activation and activation command and read/write command.ACT is the abbreviation of ACTIVE, and NOP is the abbreviation of NO OPERATION, and RD/WR is the abbreviation of READ/WRITE.The time delay that is activated to read-write of different components may be different.In actual use, this time conversion is become the integral multiple of clock period.Suppose that this clock interval is 20ns, so when DDRSDRAM works under 100MHz clock (clock period is 10ns), it is exactly 2 clock period, when DDR SDRAM works under 133MHz clock (clock period is 7.5ns), be 2.7 clock period, actual during use with 3 clock period.
Fig. 2 is that the read-write burst-length is 8 complete read operation sequential chart.ACT is the abbreviation of ACTIVE, and NOP is the abbreviation of NOOPERATION, and PRE is the abbreviation of PRECHARGE, and D1 is the data of reading to D8.It is 8 o'clock that burst-length is set, and a read command one-time continuous is read 8 data, all sends two data in each clock period.
Fig. 3 is complete read-write operation synoptic diagram.It is 2 that the read-write burst-length is set when initialization, need judge in reception this stage of read-write requests whether DDR SDRAM needs to refresh, because DDR SDRAM itself has a device refresh time at interval, refresh if desired, just send the self-refresh order, receive the request of reading or writing else if, just send activation command and activate corresponding page or leaf and row, begin DDR SDRAM is carried out read-write operation, in read operation, send read command to DDRSDRAM continuously, until the continuous read operation maximum times or the column address in a row that have not had data or reached setting among the DDR SDRAM reach maximal value, send the blank operation order to DDRSDRAM, make DDR SDRAM jump out read operation, close corresponding page or leaf and row then, in write operation, send write order to DDR SDRAM continuously, until do not have data to write or the continuous write operation maximum times or the column address in a row that reach setting reaches maximal value, send the blank operation order to DDR SDRAM, make DDR SDRAM jump out write operation, close corresponding page or leaf and row then.Behind closed page and row, finish once complete read operation or write operation.
Fig. 4 is that the read-write burst-length is 2, sends the sequential chart of 5 read commands continuously.ACT is the abbreviation of ACTIVE, and NOP is the abbreviation of NOOPERATION, and PRE is the abbreviation of PRECHARGE, and D1 is the data of reading to D10.Send 5 read commands continuously, so DDR SDRAM sends 10 data altogether in 5 clock period.
Claims (5)
1, a kind of reading/writing method of double speed dynamic random access memory may further comprise the steps:
(1) after double speed dynamic random access memory enters normal mode of operation, judges whether to have the data that need write or read always,, then change step (2), if sense data is then changeed step (3) if write data;
(2) need write in fifo buffer of data in advance existence of double speed dynamic random access memory, double speed dynamic random access memory is being carried out in the process of write operation, judge always whether data are arranged in the fifo buffer, if data are arranged then double speed dynamic random access memory is carried out write operation always, as there are not data then to judge whether to carry out read operation;
(3) double speed dynamic random access memory is being carried out in the process of read operation, judge always whether data are arranged in the double speed dynamic random access memory, if data are arranged then double speed dynamic random access memory is carried out read operation always, as there are not data then to judge whether to carry out write operation;
It is characterized in that, in the double speed dynamic random access memory controller, the read-write burst-length is made as a fixed numbers, same when capable when the same one page that is operated in double speed dynamic random access memory, send the reading and writing order continuously according to actual design.
2, the reading/writing method of double speed dynamic random access memory according to claim 1 is characterized in that, described fixed numbers is 2.
3, the reading/writing method of double speed dynamic random access memory according to claim 1 and 2 is characterized in that, the number of times that carries out read operation or write operation is continuously limited.
4, the reading/writing method of double speed dynamic random access memory according to claim 1 and 2 is characterized in that, writes data procedures and specifically may further comprise the steps:
(1) need write in fifo buffer of data in advance existence of double speed dynamic random access memory, when data, send write request to the double speed dynamic random access memory control module;
(2) receive the write request of fifo buffer when the double speed dynamic random access memory control module, send activation command and page address and row address to double speed dynamic random access memory, activate corresponding page or leaf of double speed dynamic random access memory and row;
(3) activation command that needs through double speed dynamic random access memory itself sends write order and column address to double speed dynamic random access memory after the time delay of read write command;
(4) continuous write operation maximum times or the column address in a row that has not had data in the fifo buffer or reached setting reaches maximal value, send the blank operation order to double speed dynamic random access memory, make double speed dynamic random access memory jump out write operation;
(5) send precharge command to double speed dynamic random access memory, close page or leaf and row that write operation is opened.
5, the reading/writing method of double speed dynamic random access memory according to claim 1 and 2 is characterized in that, the sense data process specifically may further comprise the steps:
(1) judges whether double speed dynamic random access memory exists data, do not have data then not carry out read operation, have data then to change corresponding read operation order over to;
(2) send activation command and page address and row address to double speed dynamic random access memory, activate corresponding page or leaf of double speed dynamic random access memory and row;
(3) send read command and column address to double speed dynamic random access memory after the time delay that is activated to read-write that process double speed dynamic random access memory itself needs;
(4) continuous read operation maximum times or the column address in a row that has not had data in the double speed dynamic random access memory or reached setting reaches maximal value, send the blank operation order to double speed dynamic random access memory, make double speed dynamic random access memory jump out read operation;
(5) send precharge command to double speed dynamic random access memory, close page or leaf and row that read operation is opened.
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| CN101470678B (en) * | 2007-12-29 | 2011-01-19 | 中国科学院声学研究所 | Outburst disorder based memory controller, system and its access scheduling method |
| CN101520722B (en) * | 2008-02-27 | 2011-12-07 | 奇景光电股份有限公司 | Method for accessing a first-in-first-out (fifo) buffer and a fifo controller therefor |
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| CN102684976A (en) * | 2011-03-10 | 2012-09-19 | 中兴通讯股份有限公司 | Method, device and system for carrying out data reading and writing on basis of DDR SDRAN (Double Data Rate Synchronous Dynamic Random Access Memory) |
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| CN103731313B (en) * | 2012-10-10 | 2017-07-14 | 华为技术有限公司 | Counter and its implementation based on DDR SDRAM |
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| CN102376353B (en) * | 2010-08-18 | 2013-09-18 | 格科微电子（上海）有限公司 | Random storage |
| CN102684976A (en) * | 2011-03-10 | 2012-09-19 | 中兴通讯股份有限公司 | Method, device and system for carrying out data reading and writing on basis of DDR SDRAN (Double Data Rate Synchronous Dynamic Random Access Memory) |
| CN102855925A (en) * | 2011-06-29 | 2013-01-02 | 爱思开海力士有限公司 | Self-refresh control circuit and memory comprising self-refresh control circuit |
| CN102855925B (en) * | 2011-06-29 | 2016-09-21 | 爱思开海力士有限公司 | Self-refreshing control circuit and the memorizer comprising self-refreshing control circuit |
| CN102708059A (en) * | 2012-05-10 | 2012-10-03 | Ut斯达康通讯有限公司 | Method for increasing SDRAM (synchronous dynamic random access memory) data transmission efficiency |
| CN102708059B (en) * | 2012-05-10 | 2014-12-24 | Ut斯达康通讯有限公司 | Method for increasing SDRAM (synchronous dynamic random access memory) data transmission efficiency |
| CN103731313B (en) * | 2012-10-10 | 2017-07-14 | 华为技术有限公司 | Counter and its implementation based on DDR SDRAM |
| TWI588841B (en) * | 2013-06-25 | 2017-06-21 | 晨星半導體股份有限公司 | Memory controller and associated signal generating method |
| CN104461956A (en) * | 2013-09-18 | 2015-03-25 | 华为技术有限公司 | Method, device and system for accessing synchronous dynamic random access memories (SDRAMs) |
| CN104461956B (en) * | 2013-09-18 | 2017-10-24 | 华为技术有限公司 | The method of access synchronized dynamic RAM, apparatus and system |
| CN107133407A (en) * | 2017-05-11 | 2017-09-05 | 成都欧飞凌通讯技术有限公司 | The FPGA implementation method of DDR RAM Interface bandwidth is improved under a kind of high bandwidth |
| CN111158588A (en) * | 2019-12-12 | 2020-05-15 | 北京邮电大学 | Double-rate control method and system |
| CN113299328A (en) * | 2021-05-21 | 2021-08-24 | 深圳市格灵精睿视觉有限公司 | Random addressing read-write control method, control system and storage medium |
| CN113360430A (en) * | 2021-06-22 | 2021-09-07 | 中国科学技术大学 | Dynamic random access memory system communication architecture |
| CN113360430B (en) * | 2021-06-22 | 2022-09-09 | 中国科学技术大学 | Dynamic random access memory system communication architecture |
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