CN1782924B - Counter device and counting method - Google Patents
Counter device and counting method Download PDFInfo
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- CN1782924B CN1782924B CN 200510125638 CN200510125638A CN1782924B CN 1782924 B CN1782924 B CN 1782924B CN 200510125638 CN200510125638 CN 200510125638 CN 200510125638 A CN200510125638 A CN 200510125638A CN 1782924 B CN1782924 B CN 1782924B
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Abstract
A counter device includes: a rewritable counter having a non-volatile memory which requires sector erasure to once turn all data in a sector into high data, prior to changing low data into high data in respective bits; and a control section updating a counter value of the rewritable count by writing in and reading out the data with respect to the rewritable counter using a complement of 1, and thereby controlling writing in and reading out the data of the rewritable counter and updade the counting value.
Description
Technical field
The counter device and the method for counting of nonvolatile memory have been the present invention relates to adopt.
Background technology
Printer and duplicating machine are by nonvolatile memory (flash memories: registered trademark) manage a plurality of counters.Counter is used for counting printing number, also is used for billing purpose etc., thereby requires to have high reliability.Yet, for nonvolatile memory, the bit that frequency of utilization is high more, reliability is just low more.Therefore, the general setting of manufacturer writes the assurance number of times, if surpass this number of times, just the reliability of nonvolatile memory significantly descend (manufacturer does not guarantee) then.
Nonvolatile memory when counter is updated, just can not be rewritten Counter Value according to its equipment energy characteristic on the same position on the nonvolatile memory.Promptly, in nonvolatile memory, this unit divides the memory block by section, for when the Data Update, the bit that is in the pass is transferred to open, and be necessary carrying out the data in the section all in case after converting bit to and opening the section deletion of (" ff " of 0xff:16 system number), write new data.
Generally, as counter, as shown in Figure 7, all writing " 0 " on the bit, when counting, begin to increase progressively one by one in advance than specially counting from the next bit.As mentioned above, in nonvolatile memory,, be necessary to carry out the data in the section are all converted to the section deletion of bit ON (0xff) for the bit that will be in the pass transfers to open.
Therefore, under this occasion, as shown in Figure 8, when the refresh counter value, just carry out the section deletion, be equivalent to writing of counter bit number thus.Therefore, as mentioned above, the reliability of nonvolatile memory will speed up decline.For improving the reliability of Counter Value, preferably reduce and rewrite number of times.
For this reason, in TOHKEMY 2001-118391 communique or the flat 11-110983 communique of TOHKEMY, some kinds of technology of the section deletion number of times when being used to reduce the Counter Value renewal are disclosed.In this prior art, as shown in Figure 9, on whole bits of counter, write " 1 " in advance, and count by making bit close (1 → 0).By transferring bit to pass from opening, can under the situation of the section deletion that is equivalent to byte number of not carrying out counter, count.
Yet, in aforesaid prior art, because bit number=maximum counter value, thereby need be equivalent to the bit number of maximum count value.Such as, under the occasion of the counting that carries out hundreds thousand of units,,, just exist and be difficult to the problem of carrying actually if consider memory span, cost just need hundreds thousand of bits.
Summary of the invention
The present invention is the invention that forms in view of foregoing problems, and its purpose is, provide under a kind of situation that does not increase memory span, do not raise the cost, but the counter device and the method for counting of the reliability of alleviator burden and raising Counter Value.
For solving aforementioned problems, counter device of the present invention has: the counter rewritten that is made of nonvolatile memory, this nonvolatile memory all converts the data in the section to the section deletion of high position data before need be in each bit low data being changed to high position data; Control part, its data of controlling aforementioned counter write and data are read, and wherein, aforementioned control part is that the source number carries out that data write and data are read to aforementioned counter with 1 complement code, and upgrades count value.
In addition, for solving aforementioned problems, method of counting of the present invention, it is the method for counting that data write and data are read of control counter, this counter is the counter rewritten that is made of nonvolatile memory, before this nonvolatile memory need be in each bit changes to high position data with low data, data in the section are all converted to the section deletion of high position data, in this method of counting, is that the source number carries out that data write and data are read to aforementioned counter with 1 complement code, and upgrades count value.
According to the present invention, utilize control part, to the counter rewritten that constitutes by nonvolatile memory, before this nonvolatile memory need be in each bit changes to high position data with low data the data in the section are all converted to the section deletion of high position data, complement code with 1 is that the source number carries out that data write and data are read, and upgrades count value.Like this,, reduce the number of times of section deletion with this owing to be that the source number is counted with 1 complement code, but thereby have do not increase memory span, the alleviator burden that do not raise the cost and improve the strong point of the reliability of Counter Value.
In addition, for solving aforementioned problems, counter device of the present invention has: the counter rewritten that is made of nonvolatile memory, this nonvolatile memory converts the data in the section to the section deletion of high position data before need be in each bit low data being changed to high position data fully; Control part, its data of controlling aforementioned counter write and data are read, and aforementioned counter has: following digit counter, it is made of first bit number, and counts first count value; Last digit counter, it is made of second bit number, and count second count value, wherein, aforementioned control part makes bit become low level from a high position by 1 bit base, upgrade first count value of aforementioned down digit counter thus, and whenever based on the aforementioned first count value circulation primary of aforementioned digit counter down the time, just upgrade aforementioned second count value that goes up digit counter.
In addition, in the counter device of the present invention, when best aforementioned control part all becomes the pass when all bits of aforementioned the next counter, aforementioned all bits of digit counter are down reset to a high position.
In addition, for solving aforementioned problems, method of counting of the present invention, it is the method for counting that data write and data are read of control counter, this counter is the counter rewritten that is made of nonvolatile memory, before this nonvolatile memory need be in each bit changes to high position data with low data, data in the section are all converted to the section deletion of high position data, aforementioned counter is by constituting with the lower part: following digit counter, it is made of first bit number, and counts first count value; Last digit counter, it is made of second bit number, and count second count value, wherein, make bit become low level by 1 bit base from a high position, upgrade first count value of aforementioned down digit counter thus, and whenever based on the aforementioned first count value circulation primary of aforementioned digit counter down the time, just upgrade aforementioned second count value that goes up digit counter.
In addition, in method of counting of the present invention, preferably when all bits of aforementioned the next counter all become the pass, aforementioned all bits of digit counter are down reset to a high position.
According to the present invention, by control part, make bit become low level by 1 bit base from a high position, upgrade first count value of digit counter down thus, and whenever based on the aforementioned first count value circulation primary of following digit counter the time, just upgrade second count value that goes up digit counter.Thereby, but have do not increase memory span, the alleviator burden that do not raise the cost and improve the strong point of the reliability of Counter Value.
In addition, according to the present invention,, when all bits of aforementioned the next counter all become the pass, aforementioned all bits of digit counter are down reset to a high position by aforementioned control part.Therefore, have and to be equal to the counting that guaranteeing in the flash memory write indegree with less memory span, and can not increase cost, alleviator burden, improve the strong point of Counter Value reliability.
Description of drawings
Fig. 1 is the block scheme of expression based on the counter device of first embodiment of the invention.
Fig. 2 is the concept map that is used to illustrate based on the counter device action of first embodiment.
Fig. 3 is the concept map of expression based on the deletion of the section in the counter device of first embodiment occurrence frequency.
Fig. 4 is the block scheme of expression based on the counter device of second embodiment of the invention.
Fig. 5 is the concept map that is used to illustrate based on the counter device action of second embodiment.
Fig. 6 is the concept map of expression based on the deletion of the section in the counter device of second embodiment occurrence frequency.
Fig. 7 is the concept map that is used to illustrate the action of existing general counter.
Fig. 8 is the concept map of the section deletion occurrence frequency in the existing general counter device of expression.
Fig. 9 is the concept map of action that is used to illustrate the counter of existing reduction section deletion occurrence frequency.
Embodiment
Following with reference to accompanying drawing, one embodiment of the present invention are described.
Fig. 1 is the block scheme of expression based on the counter device of first embodiment of the invention.Flash memories 1 is a nonvolatile memory, and has counter 2.Counter 2 is made of the bit number of regulation, and the cumulative number of rewriting is counted.The data of 3 pairs of counters 2 of control part write and data are read and controlled.In addition, below be simplified illustration, the bit number of counter 2 is made as 8 bits (1 byte), but is not limited thereto, as long as suit to guarantee required bit number according to maximum count value.
Next, Fig. 2 is the concept map that is used to illustrate the action of aforementioned counter device.In the present embodiment, Counter Value is managed as 1 complement code.At first, as initial setting, whole bits of counter 2 are made as " 1 " (uppermost bit column " 11111111 " shown in Figure 2).Behind initial setting, carry out actual count.That is, the counting action is carried out at 1 complement code.Expression makes Counter Value from 0 state transitions (from the top down) that becomes 15 hour counters 2 among Fig. 2, can find out that the most the next bit (being positioned at the value of the rightmost side of each bit column) becomes bit 0/ bit 1/ successively ...By increasing progressively counting, bit transfers out (0 → 1) to from the pass situation is per twice generation once (an oblique line part).
At this, Fig. 3 is the concept map of expression based on the deletion of the section in the counter device of present embodiment occurrence frequency.As mentioned above, in flash memories 1, transfer to open from the pass under the occasion of (0 → 1), the section deletion takes place at bit.That is, in the present embodiment, as shown in Figure 3, a section deletion of per twice generation (bold box part).Compare with existing general counter, section deletion number of times has reduced half.In addition, compared with prior art owing to do not in bit base and do not count, if thereby the bit number of being prepared is made as n, then only to count 2
n, thereby can suppress the increase of memory span.
According to present embodiment, owing to can only make bit per transfer to for twice once close (1 → 0) and change count value, thereby rewrite number of times half before can being reduced to based on the device that counter upgrades.That is,, just can make the device burden reduce half, can improve the reliability of Counter Value by the simple software change.
Next, with reference to accompanying drawing second embodiment of the present invention is described.
In the present embodiment, to the additional prosign of the structure identical, omit explanation with aforementioned first embodiment.
Fig. 4 is the block scheme of expression based on the counter device of second embodiment of the invention.
Next, Fig. 5 is the concept map that is used to illustrate the action of aforementioned counter device. in the present embodiment, in following digit counter 2a, same with existing counter, on all bits, write in advance " 1 ", count by making bit close (1 → 0). transfer the pass by making bit to from opening, do not delete under the situation of section, can count " 256 " with 32 bytes. therefore, after all bits become " 0 ", once more all bits are reset to " 1 ", and repeat the action of aforementioned counting. in aforementioned counting action, whole bits of digit counter 2a are when " 0 " resets to " 1 " instantly, make digit counter 2b begin to increase progressively one by one from the next bit, and count resets number of times. therefore, in counter 2, can carry out 2
8* 256=65536 counting.
Here, Fig. 6 is the concept map of expression based on the deletion of the section in the counter device of present embodiment occurrence frequency.As mentioned above, in flash memories 1, transfer to open from the pass under the occasion of (0 → 1), the section deletion takes place at bit.That is, in the present embodiment, as shown in Figure 6, when digit counter 2a is resetted, a section deletion (bold box part) takes place just, promptly per 256 generations once.In addition, in the present embodiment owing to do not in bit base and do not count, if thereby will descend the bit number of digit counter 2a to be made as n, the bit number of last digit counter 2b is made as m, then can only count 2
m* n, thereby can be equal to the counting that guaranteeing in the flash memories write indegree with less memory span.
According to present embodiment, can not increase memory span and situation about not raising the cost under, alleviator burden and improve the reliability of Counter Value.That is,, just can make the device burden reduce half, and improve the reliability of Counter Value by the simple software change.
In addition, in aforementioned first and second embodiment, control part 3 is worked in computer system.Like this,, just can store in the recording medium of embodied on computer readable, and read this program and carried out, carry out aforementioned processing thus by computing machine with program form based on a series of processing procedures of aforementioned control part 3.That is, central arithmetic processing apparatus such as CPU reads into aforementioned program main storage means such as ROM and RAM, and carries out information Processing and calculation process, realizes each processing unit and handling part in the control part 3 thus.
The so-called computer-readable medium storing here means disk, photomagneto disk, CD-ROM, DVD-ROM and semiconductor memory etc.In addition, also can pass through communication line, this computer program is distributed to computing machine, and carry out this program by the computing machine that receives this distributing programs.
Claims (2)
1. counter device is characterized in that having:
By the counter rewritten that nonvolatile memory constitutes, this nonvolatile memory all converts the data in the section to the section deletion of high position data before need be in each bit low data being changed to high position data;
Control part, its data of controlling aforementioned counter write and data are read, wherein,
Aforementioned control part is that the source number carries out that data write and data are read to aforementioned counter with 1 complement code, and upgrades count value.
2. method of counting, the data of its control counter write and data are read, this counter is the counter rewritten that is made of nonvolatile memory, before this nonvolatile memory need be in each bit changes to high position data with low data, the section that data in the section is all converted to high position data is deleted, and this method of counting is characterised in that:
Is that the source number carries out that data write and data are read to aforementioned counter with 1 complement code, and upgrades count value.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004351590 | 2004-12-03 | ||
| JP2004-351591 | 2004-12-03 | ||
| JP2004351591A JP2006164355A (en) | 2004-12-03 | 2004-12-03 | Counter device and counting method |
| JP2004-351590 | 2004-12-03 | ||
| JP2004351591 | 2004-12-03 | ||
| JP2004351590A JP2006164354A (en) | 2004-12-03 | 2004-12-03 | Counter device and counting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1782924A CN1782924A (en) | 2006-06-07 |
| CN1782924B true CN1782924B (en) | 2010-05-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510125638 Expired - Fee Related CN1782924B (en) | 2004-12-03 | 2005-11-30 | Counter device and counting method |
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| Country | Link |
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| JP (1) | JP2006164354A (en) |
| CN (1) | CN1782924B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854259B (en) * | 2010-06-04 | 2014-03-19 | 中兴通讯股份有限公司 | Method and system for counting data packets |
| EP2713519A1 (en) | 2012-09-27 | 2014-04-02 | Nxp B.V. | Electronic counter in non-volatile limited endurance memory |
| JP6155214B2 (en) * | 2014-03-25 | 2017-06-28 | 京セラドキュメントソリューションズ株式会社 | Data storage device and image processing device |
| TWI585366B (en) * | 2016-08-23 | 2017-06-01 | 新唐科技股份有限公司 | Counting device and pedometer device |
| CN111243644B (en) * | 2019-12-30 | 2020-10-20 | 深圳市芯天下技术有限公司 | Counting method of enhanced flash and enhanced flash |
| CN113488098A (en) * | 2021-07-20 | 2021-10-08 | 南京冷火电子科技有限公司 | Counting algorithm based on FALSH memory |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1250905A (en) * | 1998-08-13 | 2000-04-19 | 密克罗奇普技术公司 | Binary counter and method for increasing memory element service life used for counting |
-
2004
- 2004-12-03 JP JP2004351590A patent/JP2006164354A/en active Pending
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2005
- 2005-11-30 CN CN 200510125638 patent/CN1782924B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1250905A (en) * | 1998-08-13 | 2000-04-19 | 密克罗奇普技术公司 | Binary counter and method for increasing memory element service life used for counting |
Non-Patent Citations (1)
| Title |
|---|
| JP平11-110983A 1999.04.23 |
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| Publication number | Publication date |
|---|---|
| CN1782924A (en) | 2006-06-07 |
| JP2006164354A (en) | 2006-06-22 |
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