CN1779852A - Memory chip internal power administrative framework in deep shutdown mode - Google Patents
Memory chip internal power administrative framework in deep shutdown mode Download PDFInfo
- Publication number
- CN1779852A CN1779852A CN 200410095632 CN200410095632A CN1779852A CN 1779852 A CN1779852 A CN 1779852A CN 200410095632 CN200410095632 CN 200410095632 CN 200410095632 A CN200410095632 A CN 200410095632A CN 1779852 A CN1779852 A CN 1779852A
- Authority
- CN
- China
- Prior art keywords
- voltage
- those
- circuit
- shutdown mode
- deep shutdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000725 suspension Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000004913 activation Effects 0.000 claims description 13
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 8
- 240000002853 Nelumbo nucifera Species 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000005086 pumping Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 230000006698 induction Effects 0.000 description 17
- 239000013078 crystal Substances 0.000 description 14
- 238000001994 activation Methods 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Landscapes
- Dram (AREA)
Abstract
A depth turn-off method of memory wafer includes switching off voltage regulator and charge pumping circuit, making suspension joint on memory unit voltage and using voltage obtained by external water voltage to replace internal power supply voltage of supporting circuit i.e. entering all memory units to precharge state before depth turn-off mode is entered and making memory unit be suspension-joint after depth turn-off mode is entered to use depth turn-off signal to control circuit of connecting voltage obtained by external wafer to supporting circuit.
Description
Technical field
The invention relates to memory chip, and particularly relevant for the memory chip that is in deep shutdown mode.
Background technology
The application of low-power computing element (comprising memory body) continues to increase.When the usefulness of memory cell and size increased, the spent power of these elements can increase.This can make the burden of the battery that memory body and other computing element electric power need be provided.Along with the increase of power and usefulness, and produce the more demand of multipotency, produced the new demand of deep shutdown mode.When being in deep shutdown mode, wafer can only permit expending very small amount of standby power, and it requires wafer current to be lower than about 3 μ A.This low current target is difficult for reaching, and needs the internal electric source management framework.The deep shutdown of memory cell with shut down differently, memory cell is when deep shutdown, element-external supply voltage VDD still continues power supply, yet memory cell when shutting down, element-external supply voltage VDD is power supply (VDD=0V) no longer.
At United States Patent (USP) 6,243, among the 315B1 (Goodman), the memory body system is at when not using memory body, can wake the control architecture of low-power mode up, and wherein control device can be isolated memory cell, and makes it be in the self pattern.At United States Patent (USP) 5,197, in 034, be at non-volatility memory with control circuit, it can switch to memory body substantial off-mode when being in three control-state.
So method of the deep shutdown of the memory cell when needing to propose a kind of the use.Then, when memory cell need be carried out normal read-write running, it need get back to normal power.During the rebuliding of stop when entering deep shutdown running, deep shutdown mode and normal power, need not keep the integrality that stores data.
Summary of the invention
A purpose of the present invention is the voltage management framework that proposes the internal power of memory cell, to save power.
Another purpose of the present invention is the deep shutdown mode that proposes to be used for memory cell.
A further object of the present invention is by making logical lock circuit turn-on, keeps the voltage with the incoherent circuit of preliminary filling mnemon, and this logical lock circuit is to make outside wafer voltage be connected to internal circuit, replaces voltage adjuster and electric charge pump circuit.
A more purpose of the present invention is by adjuster and electric charge pump circuit are closed, and makes the relevant circuit suspension joint of preliminary filling mnemon.
Another object of the present invention is that the power consumption when memory chip enters deep shutdown mode is reduced to minimal value.
More another purpose of the present invention is by replacing voltage adjuster and group's pump circuit with the outside wafer voltage by logical lock circuit, and keeps the voltage of the memory body support circuits during the deep shutdown.
Another purpose again of the present invention is during deep shutdown mode, the output that makes electric charge pump circuit and voltage adjuster by clamp to ground connection.
Of the present invention again more another purpose be the output suspension joint that makes all charge pumps and voltage adjuster.
Further purpose of the present invention is by during deep shutdown mode, closes adjuster and charge pump, and makes the mnemon suspension joint.
In the present invention, be a kind of method of narration, by the method, when being in deep shutdown mode, can reduce the wafer power consumption, the wafer current sinking is reduced.Deep shutdown mode is to be used for low-power semiconductor memory element, as portable DRAM and virtual SRAM, to save the power of the equipment (as kneetop computer) that uses battery.
Deep shutdown mode is some special memory body RAM element (as having the movable type of low-down standby power) DRAM and virtual SRAM) unique function.Deep shutdown mode is different with shutdown mode.In deep shutdown mode, all memory body data can be lost.During shutdown mode and deep shutdown mode, renewal is unallowed.In shutdown mode, must preserve all memory body data; Therefore, memory chip time ratio update cycle of not allowing to be in the shutdown mode is long.Yet in deep shutdown mode, not free restriction.
Before entering deep shutdown mode, all mnemons at first can enter precharging state.After entering deep shutdown mode, outside wafer voltage VDD can continue to provide, all voltage adjusters and electric charge pump circuit can be closed, and outside wafer voltage VDD can become the power source with the incoherent interior periphery support circuits of preliminary filling mnemon, wherein VCC (inner support circuits power supply supply voltage) is with VDD or VCC=VDD-Vt, or VCC=VDD-nVt replaces, wherein Vt is the critical voltage of MOS electric crystal, and n is the number that is used for reducing the MOS biased element of VCC voltage.During deep shutdown mode, bit-line voltage VBL, unit plate voltage VPL and unit basic voltage VBB understand suspension joint and are tending towards 0 volt.The bit line voltage VBL of preliminary filling mnemon is the voltage that is lower than VCCSA, and wherein VCCSA is the power supply supply voltage of induction amplifier, and when applying deep shutdown signal DPD, bit line voltage VBL can suspension joint.When applying the DPD signal to memory chip, memory cell plate voltage VPL and unit basic voltage VBB also can suspension joints.When removing the DPD signal, voltage adjuster and electric charge pump circuit can be opened again, and the voltage of mnemon and peripheral circuit can be got back to and applies the previous voltage quasi position of deep shutdown signal.
Can come from wafer external power source supply voltage VDD lotus root and be connected to the memory body support circuits by making with the incoherent internal circuit power of preliminary filling mnemon, replace the current potential that uses charge pump required in the normal operation and voltage adjuster and keep this circuit.Moreover, during deep shutdown mode, the internal power relevant with preliminary filling mnemon can be because close corresponding to group's pump circuit of preliminary filling unit and voltage adjuster suspension joint.Because memory chip is originally as a large capacitor, therefore will enter the deep shutdown mode order continually and jump out the deep shutdown mode order when being sent to memory chip when system, keep the required power consumption in the accurate position of builtin voltage to be less than and do not keep the required power consumption in the accurate position of builtin voltage, can save significant wafer power.In addition, use this deep shutdown mode to reduce, or prevent the leakage current that can not expect in the defective mnemon (as the character line in the short circuit of bit line, and bit line and the short circuit of mnemon storage capacitors plate voltage line).
Description of drawings
Figure 1A is the mnemon voltage that shows when the present invention is in enabled status;
Figure 1B is the mnemon voltage that shows when the present invention is in precharging state;
Fig. 2 A to Fig. 2 E shows that the present invention is used for the sketch plan of the logical lock circuit of deep shutdown mode;
Fig. 3 A shows that the present invention has the sketch plan of the interconnected low-power memory chip of logical lock, voltage adjuster and electric charge pump circuit;
Fig. 3 B shows that the present invention uses the outside that is in the low-power memory body in the deep shutdown mode and the builtin voltage waveform of logical lock circuit;
Fig. 4 A shows that the present invention uses the ground connection lock to replace the sketch plan of the low-power memory chip of logical lock circuit;
Fig. 4 B and Fig. 4 C are the sketch plans of ground connection lock circuit of the present invention shown among the displayed map 4A;
Fig. 4 D shows that the present invention uses the outside that is in the low-power memory body in the deep shutdown mode and the builtin voltage waveform of ground connection lock.
Embodiment
Shown among Figure 1A is the circuit diagram that the present invention has the DRAM memory cell of the voltage that is used for enabled status.Bit line voltage VBL is connected to induction amplifier voltage, and it is to depend on bit line data, and equals VCCSA or 0 volt.The character line voltage VWL that is in the mnemon in the enabled status is VPP, and lotus root is connected to the plate voltage VPL of storage capacitors 10 is the voltage that is lower than bit line induction amplifier supply voltage VCCSA, and is generally half of value of bit line induction amplifier voltage VCCSA.The basic voltage VBB of activation unit 11 is for being lower than 0 volt.
Shown among Figure 1B is the circuit diagram that the present invention has the DRAM memory cell of the voltage that is used for precharging state.Bit line voltage VBL is that lotus root is connected to voltage VEQ (bit line induction amplifier equivalent voltage), and it is lower than bit line induction amplifier supply voltage VCCSA, and is generally half of value of the bit line induction amplifier supply voltage VCCSA of activation mnemon.The character line voltage VWL that is in the mnemon 11 in the precharging state is 0 volt, and the plate voltage VPL that lotus root is connected to storage capacitors 10 is the bit line induction amplifier supply voltage VCCSA that is lower than the activation unit, and is generally half of value of the bit line induction amplifier supply voltage VCCSA of activation unit.When precharging state, the basic voltage VBB of memory cell is lower than 0 volt.
Fig. 2 A shows to use so that outside wafer voltage VDD is sent to the logical lock circuit of VPP when deep shutdown mode of the present invention is opened.Voltage VPP is a character line decoder circuit supply voltage, and is under normal operation, is produced by electric charge pump circuit, and this is because it generally need have the value of the outside wafer of being higher than voltage VDD.When electric charge pump circuit was in the deep shutdown mode and closes, circuit shown among Fig. 2 A can make VDD be connected to VPP via logical lock transistor 30.When deep shutdown signal VDPD put on drop-down electric crystal 31, logical gated transistor 30 can conductings, and make VDD can (by) the VPP power lead.One level shifter Nverter circuit is used, so that short arc VDD becomes high voltage VPP, and the PMOS electric crystal can be closed, and during the normal operation of VDPD=GND, VDD and VPP is isolated.
In Fig. 2 B, be the deep shutdown mode of voltage adjuster after closing that is presented at supply VCC, and VDD is used to provide suitable voltage, with satisfy circuit requirements during, with so that the VDD lotus root is connected to an example of the logical lock circuit 39 of the present invention of VCC.The VDPD signal voltage is the input that puts on phase inverter 40, and during deep shutdown mode, it can make by electric crystal 41 conductings, and can make VDD be connected to inner VCC power lead.
In Fig. 2 C and Fig. 2 D, be to show in order to VDD-Vt and VDD-2Vt are sent to the additional examples of the logical lock circuit of the present invention of interior periphery circuit power voltage VCC.Circuit among Fig. 2 C is and the similarly logical lock circuit 49 of the logical lock circuit of Fig. 2 B, and can use bias plasma crystal element 52, and makes VCC=VDD-Vt, and wherein Vt is the critical voltage of transistor element 52.In Fig. 2 D, be logical lock circuit 59 with extra transistor element 53, it can make VCC=VDD-2Vt.Some extra transistor element 53 series connection can be used to produce VCC=VDD-nVt, and wherein n is the number of transistor element 52 and 53.Causing of the demand of different logical lock circuit by process parameter.Memory chip once only uses a usefulness so that VDD is sent to the specific logical lock circuit 39,49 or 59 of VCC.Deep shutdown signal VDPD is the input that puts on phase inverter 50, and it can make logical gated transistor 51 conductings.Electric crystal 52,53 can reduce VDD because of transistor critical voltage Vt by voltage, so that VDD-nVt meeting (transmission) is to internal peripheral circuits supply voltage VCC.
In Fig. 2 E, be an example that shows in order to the logical lock circuit of the present invention that VCC-Vt is sent to induction amplifier supply voltage VCCSA.Deep shutdown signal VDPD is the input that puts on phase inverter 60, and it can make logical gated transistor 61 conductings.Electric crystal 62 can reduce VCC because of the electric crystal critical voltage by voltage, so that VCC-Vt meeting (transmission) is to induction amplifier supply voltage VCCSA.Application class like VCC by circuit 39,49 or 59 method, electric crystal biased element 52, or some electric crystal biased elements 53 are connected in series to electric crystal 62, and cause VCCSA=VCC-nVt.And the number of the required electric crystal biased element that is determined by variable n is wafer process parameter and the demand that depends on induction amplifier.
Fig. 3 A is the calcspar that shows the first embodiment of the invention of the memory array 78 on the memory chip 69 with character line code translator 77, a line decoder 79 and bit line induction amplifier 80.Connecting so far, the peripheral circuit of array is the various connections that voltage adjuster 73,74,75 and 82, charge pump 70 and 81 reach logical lock circuit 71,72 and 76, it is during deep shutdown mode, can be controlled, and provide resulting voltage by VDD, wherein the voltage adjuster on charge pump and the wafer is to cut off control by deep shutdown controlling signal VDPD.Should be noted that the calcspar among Fig. 3 A is an example of circuit and connection, and not mean the complete DPD circuit of demonstration.
Before entering the DPD pattern, all mnemons in this array can enter the preliminary filling pattern by other peripheral circuit 68.During the activation of the deep shutdown mode DPD of VDPD when 0 volt rises to VDD, the charge pump 70 and the voltage adjuster 74 and 75 that are positioned at memory chip 69 inside can be closed, and simultaneously, logical lock circuit 71,72 and 76 meeting conductings are to provide extremely respectively this support circuits of voltage bias.The outside of memory chip 69 supply voltage VDD is used for during deep shutdown mode, provide to be biased into necessary circuitry, or with Fig. 2 E in shown similar, by a plurality of Vt (critical voltage of transistor element), and provide the voltage that is lower than VDD.Depending on the number as employed series electrical crystal in the logical lock as shown among Fig. 2 C, is as VCC=VDD-Vt or VCC=VDD-2Vt as shown among Fig. 2 E.Equational general type by circuit is VCC=VDD-nVt, wherein is the number of the transistor element that is connected in series with P passage electric crystal 51 and 61 for n.
Continue with reference to figure 3A, after entering deep shutdown mode, plate voltage adjuster 73 and bit line induction amplifier equivalent voltage VEQ adjuster 82 can be closed immediately, it can make plate voltage VPL and bit line induction amplifier equivalent voltage VEQ suspension joint and be tending towards 0 volt, and after entering the DPD pattern, VBB charge pump 81 also can be closed immediately, and makes memory body basic voltage VBB suspension joint and be tending towards ground connection.When deep shutdown mode finishes, VDPD can get back to 0 volt of logical lock circuit 71,72 and 76 and can close, plate voltage generator 73, bit line induction amplifier equivalent voltage generator 82, electric charge pump circuit 70 and voltage adjuster 74 and 75, all all can open with VBB charge pump 81, and make the low-power memory chip get back to the normal operation state.
If when memory chip is in the activation pattern, memory chip receive from the memory chip outside system sent enters the deep shutdown mode order, then memory chip at first will enter the preliminary filling pattern, just enters deep shutdown mode then.If when memory chip is in the preliminary filling pattern, memory chip receives and enters the deep shutdown mode order, and then memory chip will directly enter deep shutdown mode.If when memory chip is in deep shutdown mode, memory chip receives and leaves the deep shutdown mode order, and then memory chip will directly enter the preliminary filling pattern.
Fig. 3 B is presented at after precharging state enters deep shutdown mode 20, up to the waveform of the various voltages of first embodiment that leaves DPD pattern 21.DPD signal VDPD can rise to VDD from 0 volt, and makes memory chip 69 enter the DPD pattern, and it can make the power consumption of memory chip reduce.When the VDPD signal was got back to 0 volt, memory chip 69 can leave the DPD pattern.Before deep shutdown mode, during and after, the external voltage VDD that is connected to memory chip can keep its value, and originates for the power supply of logical lock.During the DPD pattern, the inside character line voltage VPP of activation unit can be reduced to VDD.During the DPD pattern, normally the character line voltage VPP that is supplied by charge pump 70 replaces by the VDD that leads to lock 71.
Continue with reference to figure 3B, the builtin voltage VCC of peripheral circuit is the value (as VCC=VDD-nVt) that is maintained at the value of VCC=VDD or is lower than VDD, and it is after entering the DPD pattern, generation immediately.During the DPD pattern, induction amplifier internal electric source supply voltage VCCSA can be reduced to the voltage that is lower than VCC.The inside bit line voltage VBL of preliminary filling unit (it is coupled to VEQ) is lower than VCCSA, and is generally VCCSA half.When wafer enters the DPD pattern, VEQ meeting suspension joint, and before the end of DPD pattern, can be tending towards 0 volt.Unit plate voltage VPL is lower than VCCSA, and is generally VCCSA half.During the DPD pattern, plate voltage VPL is a suspension joint, and before the end of DPD pattern, can be tending towards 0 volt, and unit basic voltage VBB (it is to be lower than 0 volt) meeting suspension joint, and before the end of DPD pattern, can be tending towards 0 volt.Before entering the DPD pattern, all memory cells must be in precharging state.During the DPD pattern, all adjusters and charge pump (it can produce internal wafer voltage) can be closed, to save standby power.During the activation of DPD pattern, the voltage as VEQ, VPL and VBB relevant with the power of preliminary filling unit is suspension joint, and can be tending towards 0 volt, as shown among Fig. 3 B.Voltage (it is directly not relevant with the preliminary filling memory cell, and is to obtain from voltage adjuster or charge pump) as VPP, VCC and VCCSA can replace with resulting voltage from memory chip external voltage VDD.As Fig. 2 A those shown logical lock circuit in Fig. 2 E is that the voltage that is used for the outside is obtained is connected to support circuits internal electric source supply line.When memory chip leaves deep shutdown mode, because logical lock circuit is to be used for the keeping voltage on the charge pump output line to also have the voltage (it is to be connected to support circuits) on the voltage adjuster output line that the bias voltage that can prevent the circuit bolt-lock can be provided.When system will leave the deep shutdown mode order and be sent to other peripheral circuit, VDPD can get back to ground connection (0 volt) and all can be closed by circuit 71,72 and 76, and charge pump 70 and 81, and voltage adjuster 73,74,75 and 82 can conductings.The falling edge that detects VDPD can make memory chip return normal operation.
When system will enter the deep shutdown mode order and leave the deep shutdown mode order when being sent to memory chip 69 continually, because the switching electric charge in order to the memory chip that keeps the internal circuit voltage quasi position can be less than the switching electric charge of the memory chip that does not keep the internal circuit voltage quasi position, so in this case, the first embodiment of the present invention can be saved system with more power.This be because memory chip this as large capacitor, and if during deep shutdown mode, fail to keep the accurate position of builtin voltage, then all electric charges of memory body will be discharged to ground.When memory chip leaves deep shutdown mode and gets back to normal operation, outer power voltage VDD will need once more large capacitor to be charged then.Moreover deep shutdown mode of the present invention can prevent the leakage current that can not expect in the defective mnemon (or repair unit) (as character line and the short circuit of bit line, or bit line and the short circuit of plate voltage line).
In the second embodiment of the present invention, after entering deep shutdown mode, all voltage adjusters and group's pump circuit can be closed immediately, and the output line of the correspondence of voltage adjuster and charge pump can be by ground connection lock 83 and 84 and be discharged to ground.Fig. 4 A is the calcspar that shows second embodiment. Ground connection lock 83 and 84 can activations, the VBB ground connection that it can make the voltage VPP, the VCC that are connected to peripheral circuit and VCCSA, the VEQ that is connected to the mnemon anode and VPL and be connected to the memory body substrate.When memory chip receives when leaving the deep shutdown mode order, deep shutdown mode can stop, and wherein ground connection lock 83 and 84 is open circuits, and charge pump 70 and 81, and voltage adjuster 73,74,75 and 82 can return normal operation.
For second embodiment, if when memory chip is in the activation pattern, memory chip receives and enters the deep shutdown mode order, and then memory chip will directly enter deep shutdown mode.If when memory chip is in the preliminary filling pattern, memory chip receives and enters the deep shutdown mode order, and then memory chip also will directly enter deep shutdown mode.If when being in deep shutdown mode, memory chip receives and leaves the deep shutdown mode order, and then memory chip will directly enter the preliminary filling pattern.
Fig. 4 B is the sketch plan of employed ground connection lock 83 among the displayed map 4A.After entering deep shutdown mode and make VDPD voltage rise to VDD, can make the output ground connection of the circuit of additional ground connection lock from ground connection.Fig. 4 C is the employed ground connection lock 84 of output of VBB charge pump 81 shown among the displayed map 4A.VSS (ground connection) can make the ground connection lock close fully to the accurate bit shift phase inverter 85 of VBB (negative voltage).If VDPD voltage is to be connected directly to node N1, then when memory chip 69 is in normal mode and VDPD and equals low-voltage as ground connection, VBB will have the leakage current that flows to ground.Because VBB is a negative voltage.So when node N1 was ground connection, ground connection lock 86 can not cut out fully.Therefore by inserting the accurate bit shift phase inverter 85 of VSS to VBB, when VDPD was low-voltage, node N1 was positioned at VBB, and ground connection lock 86 can cut out fully.
Fig. 4 D is the waveform that shows corresponding to the second embodiment of the present invention.Fig. 4 B is similar to Fig. 3 B, except after entering deep shutdown mode 20, VPP, VCC, VCCSA, VBB, VEQ and VPL all can be by ground connection lock 83 and 84 and reduce to 0 volt immediately, rather than as the situation of first embodiment as shown among Fig. 3 B, make VEQ, VPL and VBB can be tending towards ground connection, and VPP, VCC and VCCSA can supply the voltage VDD and obtain from outside wafer.When VDPD when 0 volt rises to VDD, wafer can enter deep shutdown mode, and ground connection lock 83 and 84 can make VPP, VCC, VCCSA, VEQ, VPL and VBB be coupled to ground.When deep shutdown mode finishes 21, VDPD can get back to 0 volt, ground connection lock 83 and 84 can open circuit and charge pump 70 and 81, voltage adjuster 73,74,75 and 82 activation and memory chip can be got back to normal operation again.The selection that should be noted that ground connection lock 83 shown among logical lock circuit 71,72,76 shown among Fig. 3 A and Fig. 4 A and 84 is in conjunction with can be used for deep shutdown mode.
In the third embodiment of the present invention, open 20 o'clock beginnings at deep shutdown mode, charge pump 70 and 81, voltage adjuster 73,74,75 and 82 can cut out. Ground connection lock 83 and 84 can conducting or is not existed, but and all internal electric source VPP, VCC, VCCSA, VEQ, VPL and VBB or a subclass suspension joint.Finish at 21 o'clock at deep shutdown mode, all internal electric sources can be got back to normal operation.
For the 3rd embodiment, if when memory chip is in the activation pattern, memory chip receives and enters the deep shutdown mode order, and then memory chip will directly enter deep shutdown mode.If when memory chip is in the preliminary filling pattern, memory chip receives and enters the deep shutdown mode order, and then memory chip also will directly enter deep shutdown mode.If when being in deep shutdown mode, memory chip receives and leaves the deep shutdown mode order, and then memory chip will directly enter the preliminary filling pattern.
Though having cooperated its preferred embodiment, the present invention shows especially and illustrates that what be familiar with that this operator will recognize is under without departing from the spirit or scope of the invention, can carry out the various changes of mode and details.
Claims (30)
1. deep shutdown circuit is characterized in that: in order to save the power of a low-power memory chip, comprising:
A) a plurality of logical lock circuit, its each be that lotus root is connected to the electric charge pump circuit that is positioned at this low-power memory chip inside and the output of voltage adjuster; And
B) when those charge pumps, those voltage adjusters and voltage generator were in a deep shutdown mode and close, those logical lock circuit can make an external voltage lotus root of this low-power memory chip be connected to the memory body support circuits.
2. deep shutdown circuit as claimed in claim 1, it is characterized in that: when wherein this deep shutdown mode after carrying out a mnemon preliminary filling opens the beginning, those charge pumps and those voltage adjusters can be closed, and those logical lock circuit meeting conductings are to offer power supply those support circuits.
3. deep shutdown circuit as claimed in claim 1 is characterized in that: wherein when this deep shutdown mode finished, those logical lock circuit can be closed, and those charge pumps, those voltage adjusters and those voltage generators can conductings.
4. deep shutdown circuit as claimed in claim 1, it is characterized in that: wherein those logical lock circuit are replaced by ground connection lock that can activation in this deep shutdown mode, so that be positioned at those charge pumps of inside of this low-power memory chip and the output ground connection of those voltage adjusters.
5. deep shutdown circuit as claimed in claim 4, it is characterized in that: wherein when this low-power memory chip entered this deep shutdown mode, the combination of a selectivity of those ground connection locks and those logical lock circuit was the output that is used for replacing those electric charge pump circuits and those voltage adjusters.
6. deep shutdown circuit as claimed in claim 4, it is characterized in that: wherein being in this deep shutdown mode after closing, do not re-use those logical lock circuit and those ground connection locks, and make the output suspension joint of those electric charge pump circuits and those voltage adjusters.
7. deep shutdown circuit as claimed in claim 6, it is characterized in that: wherein when this low-power memory chip entered this deep shutdown mode, the combination of a selectivity of the suspension joint of the output of those ground connection locks, those logical lock circuit and those electric charge pump circuits and those voltage adjusters was the output that is used for replacing those electric charge pump circuits and those voltage adjusters.
8. a method that reduces the memory chip power during the deep shutdown mode is characterized in that: comprise the following steps:
A) before implementing a deep shutdown mode, mnemon is carried out precharge handle; And
B) enter this deep shutdown mode and reduce the power of a memory chip, comprising:
I) make to those mnemon carry out precharge handle in employed voltage suspension joint; And
Ii) replace and those mnemons are carried out precharge and handle incoherent memory internal body wafer voltage with the resulting voltage of an external voltage from this memory chip.
9. method as claimed in claim 8 is characterized in that: wherein those mnemons being carried out the precharge processing is to make those mnemons enter a pre-charge state.
10. method as claimed in claim 9 is characterized in that: wherein make the step of those mnemon voltage being carried out employed voltage suspension joint in the precharge processing, more comprise:
A) make bit line voltage suspension joint;
B) make memory body storage capacitors plate voltage suspension joint and
C) make mnemon basic voltage suspension joint.
11. method as claimed in claim 8 is characterized in that: wherein make and those mnemon voltage is carried out in the pre-service untapped voltage suspension joint comprise voltage adjuster and charge pump are closed.
12. method as claimed in claim 8 is characterized in that: wherein replace and the step of those mnemons being carried out the incoherent memory internal body of pre-service wafer voltage, more comprise:
A) voltage adjuster and charge pump are closed; And
B) use and the logical lock circuit that is connected from the resulting voltage of an outside wafer voltage, replace those builtin voltages of the output that comes from the voltage adjuster of closing and charge pump.
13. method as claimed in claim 12 is characterized in that: wherein replacing with those mnemons are carried out the incoherent memory internal body of pre-service wafer voltage with the resulting voltage in outside is in order to prevent at the wafer bolt-lock after this deep shutdown mode leaves.
14. method as claimed in claim 12 is characterized in that: wherein replacing memory internal body wafer voltage is by using the ground connection lock, so that the output ground connection of voltage adjuster of closing and charge pump.
15. method as claimed in claim 14 is characterized in that: those voltage adjusters and those charge pumps of wherein closing are output as suspension joint, and can not replace with in those logical lock circuit and those ground connection locks any.
16. method as claimed in claim 15 is characterized in that: those voltage adjusters of wherein closing and the output of those charge pumps are that the selectivity with the suspension joint of logical lock circuit, ground connection lock and those voltage adjusters and those charge pumps makes up and replaces.
17. a system that saves the memory chip power during the deep shutdown mode is characterized in that: comprising:
A) usefulness is so that the device that voltage adjuster and charge pump are closed on the wafer on the memory chip; And
B) one in order to replace the device of the output voltage of those voltage adjusters and those charge pumps during a deep shutdown mode.
18. system as claimed in claim 17 is characterized in that: wherein with so that this device that voltage adjuster and charge pump are closed on the wafer can make mnemon voltage suspension joint.
19. system as claimed in claim 17 is characterized in that: wherein with so that this device that voltage adjuster and charge pump are closed on the wafer can eliminate in order to keep by those voltage adjusters and the required standby power of voltage that those charge pumps produce.
20. system as claimed in claim 17 is characterized in that: wherein this device that replaces the output voltage of those voltage adjusters during this deep shutdown mode and those charge pumps in order to resulting voltage from a memory external body wafer voltage is to use logical lock circuit.
21. system as claimed in claim 20, it is characterized in that: wherein remove and this memory chip when getting back to normal operation when this deep shutdown mode, can prevent the circuit bolt-lock in order to this device of the output voltage that replaces those voltage adjusters and those charge pumps.
22. system as claimed in claim 20, it is characterized in that: wherein in order to during this deep shutdown mode, this device that replaces the output voltage of those voltage adjusters and those charge pumps is to use a device of the output ground connection that makes those voltage adjusters and those charge pumps.
23. the system as claimed in claim 22, it is characterized in that: wherein in order to during this deep shutdown mode, this device that replaces the output voltage of those voltage adjusters and those charge pumps can make the output suspension joint of those voltage adjusters and those charge pumps.
24. system as claimed in claim 23, it is characterized in that: wherein in order to during this deep shutdown mode, this device that replaces the output voltage of those voltage adjusters and those charge pumps is to use the selectivity combination of the suspension joint of logical lock circuit, ground connection lock and those voltage adjusters and those charge pumps.
25. a deep shutdown mode that is used for the low-power memory chip is characterized in that: comprising:
A) a low-power memory chip;
B) builtin voltage circuit is in order to provide internal circuit power to this memory chip;
C) a logical lock circuit is with so that an outside resultant voltage is connected to those builtin voltage circuit;
D) a deep shutdown signal reduces power in order to control one of this memory chip; And
E) this deep shutdown signal is in order to during a deep shutdown, controls those builtin voltage circuit and closes and control those logical lock circuit turn-ons, to reduce the power of this memory chip.
26. deep shutdown mode as claimed in claim 25 is characterized in that: be to be a plurality of voltage adjusters and a plurality of electric charge pump circuit wherein at those builtin voltage circuit.
27. deep shutdown mode as claimed in claim 25 is characterized in that: wherein during this deep shutdown mode, those logical lock circuit are to make the resultant voltage lotus root in this outside be connected to the output of those builtin voltage circuit.
28. deep shutdown mode as claimed in claim 25 is characterized in that: wherein during this deep shutdown mode, those logical lock circuit are so that the ground connection lock of the output ground connection of those builtin voltage circuit replaces.
29. deep shutdown mode as claimed in claim 28 is characterized in that: wherein during this deep shutdown mode, those builtin voltage circuit can be closed, and allow to make the output suspension joint of those builtin voltage circuit.
30. deep shutdown mode as claimed in claim 29, it is characterized in that: wherein during this deep shutdown mode, the selectivity combination of the suspension joint of those logical lock circuit, those ground connection locks and those builtin voltage circuit output is to be used for reducing memory chip power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410095632 CN1779852A (en) | 2004-11-26 | 2004-11-26 | Memory chip internal power administrative framework in deep shutdown mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410095632 CN1779852A (en) | 2004-11-26 | 2004-11-26 | Memory chip internal power administrative framework in deep shutdown mode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1779852A true CN1779852A (en) | 2006-05-31 |
Family
ID=36770120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410095632 Pending CN1779852A (en) | 2004-11-26 | 2004-11-26 | Memory chip internal power administrative framework in deep shutdown mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1779852A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856131A (en) * | 2012-12-06 | 2014-06-11 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
-
2004
- 2004-11-26 CN CN 200410095632 patent/CN1779852A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856131A (en) * | 2012-12-06 | 2014-06-11 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
| CN103856131B (en) * | 2012-12-06 | 2016-06-22 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4047375B2 (en) | Sequential programming of flash EEPROM memory | |
| US8339183B2 (en) | Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories | |
| US7292494B2 (en) | Internal power management scheme for a memory chip in deep power down mode | |
| US7969234B2 (en) | Clock control circuit and voltage pumping device using the same | |
| CN100490011C (en) | Circuit of local word line driver of DRAM | |
| US6842383B2 (en) | Method and circuit for operating a memory cell using a single charge pump | |
| KR100562654B1 (en) | Bleq driving circuit and semiconductor memory device using it | |
| CN103959387A (en) | Enhanced data retention mode for dynamic memories | |
| US8009483B2 (en) | Nonvolatile memory cell and data latch incorporating nonvolatile memory cell | |
| JPH07231647A (en) | Semiconductor device | |
| US20010001263A1 (en) | VPX bank architecture | |
| CN1801605A (en) | Comparator using differential amplifier with reduced current consumption | |
| CN106384605B (en) | low-power-consumption nonvolatile electronic programmable memory | |
| US6208539B1 (en) | Two-phase clock charge pump with power regulation | |
| KR102330656B1 (en) | Nvm with charge pump and method therefor | |
| WO2007077801A1 (en) | Memory system for reducing current consumption and method thereof | |
| JP2012226805A (en) | Internal power supply voltage generation circuit and internal power supply voltage generating method of semiconductor memory | |
| US6847250B2 (en) | Pumping circuit for outputting program voltage and program verify voltage of different levels | |
| US6414882B1 (en) | Low voltage charge pump apparatus and method | |
| JP5727121B2 (en) | Internal voltage generation circuit and semiconductor device including the same | |
| CN1779852A (en) | Memory chip internal power administrative framework in deep shutdown mode | |
| CN1722301B (en) | Semiconductor storage device | |
| JPH01282796A (en) | Non-volatile semiconductor storage | |
| US10770153B2 (en) | Charge pump drive circuit with two switch signals | |
| EP0928003B1 (en) | Row decoder circuit for an electronic memory device, particularly for low voltage applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20060531 |