CN1777310A - Clock correcting method and device - Google Patents

Abstract

The invention discloses a clock set method, comprising step computing clock set time, in the step, firstly computing timing error value, then computing clock set time according to timing error value. It also discloses a clock set device, comprising a computing unit for computing said clock set time. The computing unit comprises: a timing error computing unit for computing timing error value; and a clock set time computing unit for computing clock set time according to timing error value obtained from computing. The invention can reduce clock set cycle under premise of satisfying timing error, and increasing terminal deep sleeping time, and prolonging terminal stand-by time.

Description

Clock correcting method and equipment

Technical field

The present invention relates in a kind of being applied in the radio communication system terminal, particularly TD-SCDMA mobile communication system terminal clock correcting method and equipment.

Background technology

In portable terminal, power consumption is an important performance parameter of terminal.How to reduce the importance that to consider when power consumption is Terminal Design with the stand-by time that increases portable terminal and air time.Terminal reduces power consumption in the standby process method mainly is by in the paging receiving information process, between adjacent paging indication, does province's electric treatment.Comprising: radio-frequency module, Analog Baseband module, digital baseband part.The analog baseband section branch comprises that falling voltage handles; Digital baseband part comprises that falling voltage handles and down conversion process.

For the battery saving mode in the paging, need guarantee the correctness of terminal when receiving the paging indication.For the TD-SCDMA system terminal, mean and to guarantee the correct of System Frame Number and frame timing.For portable terminal, after entering the sound sleep pattern, generally the master clock of system is turned off.This moment, the timing of system was kept by a low-frequency clock.The frequency of this low-frequency clock is uncertain, must be through calibration carry out the timing maintenance with this clock before.

When low-frequency clock is calibrated, reach certain precision in order to guarantee low-frequency clock, need the regular hour to utilize high frequency clock that low-frequency clock is calibrated.And this moment, system can't enter deep sleep mode.Directly influenced the length of system's length of one's sleep in the length of alignment time.And this calibration process need periodically carry out.Present implementation is that each paging cycle need carry out clock alignment one time.In order not influence the length of one's sleep of system, the low-frequency clock alignment time should be short as much as possible.But the too short precision that can not guarantee low-frequency clock again of alignment time, thereby cause bigger timing error.How the appropriate alignment time is set, makes under the prerequisite that guarantees the low-frequency clock precision, avoid taking system length of one's sleep as far as possible because of clock alignment.

Summary of the invention

The objective of the invention is provides in a kind of TD-SCDMA of being applied to mobile communication system terminal in order to solve the above-mentioned problems in the prior art and defective, is used for self-adapting type clock correcting method and device under the battery saving mode.

The objective of the invention is to be achieved through the following technical solutions:

A kind of clock correcting method comprises the step of calculating the clock alignment time, calculates in the clock alignment time step at this, calculates the timing error value earlier, calculates the clock alignment time according to the timing error value then.

Can calculate timing error value Δ by the following method:

Δ＝α(T _FT+T _W)-δ，

Wherein, T _FTBe the timing tracing positional of current path track algorithm, T _wBe the fault-tolerant error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, and α is predefined coefficient, 0＜α≤1.

Preferably, α is more than or equal to 0.5 and smaller or equal to 1.

Can calculate the clock alignment time T by the following method _m:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}},$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

And then when low-frequency clock was calibrated, carrying out time span was T _mCalibration.

Technical scheme of the present invention also comprises a kind of clock alignment equipment, comprises a calculation element, is used to calculate the described clock alignment time, and this calculation element comprises: a timing error computing unit is used to calculate the timing error value; A clock alignment time calculating unit calculates the clock alignment time according to the timing error value that calculates.

Wherein, at this timing error computing unit, the formula below utilizing calculates timing error value Δ:

Δ＝α(T _FT+T _W)-δ，

In the formula, T _FTBe the timing tracing positional of current path track algorithm, T _wBe the fault-tolerant error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, and α is predefined coefficient, 0＜α≤1.

The preferable range of α is more than or equal to 0.5 and smaller or equal to 1.

Wherein, this alignment time computing unit profit is calculated the described clock alignment time in the following method:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}}$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

This clock alignment equipment also comprises a calibrating installation, and it is T that low-frequency clock is carried out time span _mCalibration.

Positive progressive effect of the present invention is: satisfying under the timing error requirement prerequisite, can reduce the clock alignment cycle, thereby increase the deep sleep time of terminal, and then prolong the stand-by time of terminal.

Description of drawings

Fig. 1 is the structured flowchart of the embodiment of the invention 5,6,7,8.

Embodiment

Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.

Embodiment 1

A kind of clock correcting method comprises the step of calculating the clock alignment time, calculates in the clock alignment time step at this, calculates the timing error value earlier, calculates the clock alignment time according to the timing error value then.

At first, obtain paging indication receiving cycle, calculate the step of clock alignment time then according to the network broadcast message that receives.

Wherein, can calculate timing error value Δ by the following method:

Δ＝α(T _FT+T _W)-δ，

Wherein, T _FTBe the tracing positional of path trace algorithm, T _wBe the timing error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, described T _FT, T _W, T _DRXAnd f _HBe in the communication system predefined, δ is the poor of high frequency clock and low-frequency clock, and α is according to the predefined coefficient of the needs of communication system, in the present embodiment, and α=1.

That is: Δ=(T _FT+ T _W-δ),

Wherein, calculate the clock alignment time T by the following method _m:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}},$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

Then, when low-frequency clock was calibrated, carrying out time span was T _mCalibration.

Embodiment 2

Present embodiment is with the different of embodiment 1: α=0.5, all the other processes are all identical with embodiment 1, repeat no more.

Embodiment 3

Present embodiment is with the different of embodiment 1 or 2: α=0.8, all the other processes are all identical with embodiment 1, repeat no more.

Embodiment 4

Different being of present embodiment and embodiment 1,2 or 3: α=0.2, all the other processes are all identical with embodiment 1, repeat no more.

Embodiment 5

As shown in Figure 1, a kind of clock alignment equipment comprises a calculation element 1, is used to calculate the described clock alignment time, and this calculation element 1 comprises: a timing error computing unit 11 is used to calculate the timing error value; A clock alignment time calculating unit 12 calculates the clock alignment time according to the timing error value that calculates.

Wherein, at this timing error computing unit 11, the formula below utilizing calculates timing error value Δ:

Δ＝α(T _FT+T _W)-δ，

Wherein, T _FTBe the tracing positional of path trace algorithm, T _wBe the timing error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, described T _FT, T _w, T _DRXAnd f _HBe in the communication system predefined, δ is the poor of high frequency clock and low-frequency clock, and α is according to the predefined coefficient of the needs of communication system, in the present embodiment, and α=1.

Wherein, these alignment time computing unit 12 profits are calculated the described clock alignment time in the following method:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}},$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

This clock alignment equipment also comprises a calibrating installation 2, and it is T that low-frequency clock is carried out time span _mCalibration.

Embodiment 6

The difference of present embodiment and embodiment 5 is: α=0.5, remainder are all identical with embodiment 3, repeat no more.

Embodiment 7

The difference of present embodiment and embodiment 5 or 6 is: α=0.8, remainder are all identical with embodiment 3, repeat no more.

Embodiment 8

The difference of present embodiment and embodiment 5,6 or 7 is: α=0.2, remainder are all identical with embodiment 3, repeat no more.

Claims (10)

1, a kind of clock correcting method comprises the step of calculating the clock alignment time, it is characterized in that, calculates in the clock alignment time step at this, calculates the timing error value earlier, calculates the clock alignment time according to the timing error value then.

2, the clock correcting method under the battery saving mode according to claim 1 is characterized in that, can calculate timing error value Δ by the following method:

Δ＝α(T _FT+T _W)-δ，

Wherein, T _FTBe the timing tracing positional of current path track algorithm, T _wBe the fault-tolerant error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, and α is predefined coefficient, 0＜α≤1.

3, the clock correcting method under the battery saving mode according to claim 2 is characterized in that, α is more than or equal to 0.5 and smaller or equal to 1.

4, according to the clock correcting method under claim 2 or the 3 described battery saving modes, it is characterized in that, calculate the clock alignment time T by the following method _m:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}},$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

5, the clock correcting method under the battery saving mode according to claim 4 is characterized in that, when low-frequency clock was calibrated, carrying out time span was T _mCalibration.

6, a kind of clock alignment equipment comprises a calculation element, is used to calculate the described clock alignment time, it is characterized in that this calculation element comprises: a timing error computing unit is used to calculate the timing error value; A clock alignment time calculating unit calculates the clock alignment time according to the timing error value that calculates.

7, clock alignment equipment according to claim 6 is characterized in that, at this timing error computing unit, the formula below utilizing calculates timing error value Δ:

Δ＝α(T _FT+T _W)-δ，

Wherein, T _FTBe the timing tracing positional of current path track algorithm, T _wBe the fault-tolerant error that can calibrate before the paging receiving indication by the path trace algorithm, δ is the timing error surplus, and α is predefined coefficient, 0＜α≤1.

8, clock alignment equipment according to claim 7 is characterized in that, α is more than or equal to 0.5 and smaller or equal to 1.

According to claim 7 or 8 described clock alignment equipment, it is characterized in that 9, this alignment time computing unit profit is calculated the described clock alignment time in the following method:

$T_m=\frac{T_{\mathrm{DRX}}}{f_H\mathrm{\Δ}}$

Wherein, T _DRXBe discontinuous receiving cycle, f _HIt is the frequency of high frequency clock.

10, clock alignment equipment according to claim 9 is characterized in that, it also comprises a calibrating installation, and it is T that low-frequency clock is carried out time span _mCalibration.