CN1777230A - Satellite digital television receiver set top box based on embedded technology - Google Patents
Satellite digital television receiver set top box based on embedded technology Download PDFInfo
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- CN1777230A CN1777230A CNA2005101111483A CN200510111148A CN1777230A CN 1777230 A CN1777230 A CN 1777230A CN A2005101111483 A CNA2005101111483 A CN A2005101111483A CN 200510111148 A CN200510111148 A CN 200510111148A CN 1777230 A CN1777230 A CN 1777230A
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Abstract
A satellite digital TV set-top box based on inlaying-type technique includes a fore-panel module and a power supply module that respectively connects to a main processing circuit. The main processing circuit includes a modulation-demodulation module, a digital signal processing DSP module and a CPU module that are connected in turn. The main processing circuit also includes a video D/A module and a display that connects to the digital signal processing DSP module in turn, an audio decoding module, an audio D/A module and a voice box that connects to the DSP module in turn, and a FPGA (field programmable gate array) module. Advantages: increased satellite channel number under same bandwidth of satellite converter and raised channel utilizing rate.
Description
Technical field
The present invention relates to a kind of satellite digital television receiver set top box, belong to the satellite digital TV system, further belong to the user terminal receiving equipment in the satellite digital TV system based on embedded technology.
Background technology
Whole satellite digital TV system is received by transmitting terminal, repeater satellite and signal and subscriber terminal equipment is formed:
As shown in Figure 1, described transmitting terminal is divided into two parts, and a part forms (being source encoding) 1 ' and multiplexing part 2 ' for signal, and another part is signal transmission (being chnnel coding) 3 ' and digital modulation part 4 '; Coding can adopt high-speed computer or special equipment with multiplexing equipment, and chnnel coding and digital modulation part generally adopt special equipment.
The channel quantity that described repeater satellite can transmit signal is N, and then computing formula is: N=n*f
z/ f
d, wherein: n is the quantity of satellite repeater; f
zBandwidth for single satellite repeater; f
dFor one way channel with prevent to disturb required bandwidth sum.
Described signal receiver comprises parabolic antenna, feed.
As shown in Figure 2, after described subscriber terminal equipment receives the satellite RF signal by signal receiver,, channel demodulation 6 ', source coding 7 ' 5 ' tuning and the form output of 8 ' back that displays the play with analog video signal and simulated audio signal through its tuner that comprises.
The bandwidth of the satellite RF signal that present subscriber terminal equipment receives is: 950MHZ～2150MHZ, the channel modulation mode of subscriber terminal equipment is QPSK (Quadrature Phase Shift Keying modulation), the tuner, the channel demodulation module that adopt are generally integration module, the standard of source coding is generally MPEG2, adopt special chip, operating system and application program thereof are solidified togather with special chip.
The shortcoming of above-mentioned subscriber terminal equipment is:
1, channel utilization is low: the compression ratio of the compress mode of MPEG2 is low, and the data rate after cover commercial SD (720 * 576,50/second, perhaps 720 * 480,60/second) the TV programme compression is 3～4Mbps; Adopt the channel modulation mode of QPSK in addition, and 8PSK (modulation of 8 phase keyings), 16QAM technology such as (quadrature amplitude modulation) be applied not also, a transponder bandwidth is up to 54Mbit, the channel transmitted limited amount.
2, do not have independent intellectual property right, need the huge patent fee of payment: at present domestic satellite digital TV terminal in use generally adopts external ready-made technology, and it is the same to be similar to DVD, need pay huge patent fee to the patent holder.
The operating system of set-top box inside and application software are to be provided by the main process chip manufacturer that buys basically, do not have independent intellectual property right, and the MPEG-2 patent fee of every station terminal equipment is just up to 2.5 U.S. dollars.
3, function singleness: generally just have satellite-signal and receive and the function of playing, the function that does not have to upgrade occurs.
4, poor stability: MPEG2 is ripe in the world video/audio encoding and decoding technology, and the threshold of grasping this technology is low; A lot of illegal set-top box are arranged on the market, and private dress spreads unchecked; If satellite repeater is attacked by the lawless person, satellite user is easy to receive illegal programs, is difficult to management.
Summary of the invention
A kind of satellite digital television receiver set top box based on embedded technology provided by the invention adopts embedded system structure triturating machine top box, has strengthened function, has improved channel utilization.
In order to achieve the above object, the invention provides a kind of satellite digital television receiver set top box, comprise main treatment circuit based on embedded technology, and the front panel module and the power module that are connected with main treatment circuit respectively;
Described main treatment circuit comprises tuning and demodulation module, Digital Signal Processing DSP module and the CPU module that connects successively;
Describedly tuningly comprise tuner module and the channel demodulation module that is connected successively with demodulation module;
The status register of described tuner module inside writes configuration, the correct back of configuration operate as normal by Digital Signal Processing DSP module by I2C (Inter-Integrated Circuit implants integrated circuit) bus; The input input satellite RF signal of demodulation module outputs to the intermediate-freuqncy signal that obtains in the channel demodulation module;
The input of described channel demodulation module connects the output of described tuner module, adopt QPSK (Quadrature Phase Shift Keying modulation) channel demodulation, the intermediate-freuqncy signal of input is carried out channel demodulation after output signal be: the TS of 8bit and line output (transmission) code stream, TS code stream are exported clock, TS code stream synchronizing signal;
Described Digital Signal Processing DSP module is connected described tuning and demodulation module by GPIO (general I/O) Simulation with I 2C bus with the first high-speed parallel mouth, described Digital Signal Processing DSP module comprises demultiplexing module, looks the audio sync module, video decode module and Audio Processing output module, and described Digital Signal Processing DSP module also connects a SDRAM (synchronous DRAM) and a FLASH (flash memory);
Described Digital Signal Processing DSP module utilizes FLASH that system is powered on/the zero clearing initialization; Write each register configuration toward tuning with demodulation module by GPIO Simulation with I 2C bus; Receive TS code stream tuning and demodulation module output by the first high-speed parallel mouth, by interrupting and DMA (direct memory access (DMA)) controller and being cached among the SDRAM in the Digital Signal Processing DSP module;
Described demultiplexing module is carried out demultiplexing to the TS code stream that is cached among the SDRAM, obtains video ES stream (basic stream), audio ES stream, DTS (beginning decode time), PTS (broadcast start time), PCR (reference clock);
Describedly look the utilization of audio sync module begins decode time DTS, broadcast start time PTS, reference clock PCR carries out Synchronization Control to looking audio frequency;
Described video decode module is carried out the AVS video decode to video ES stream, and decoded digital video signal is carried out the ITU-T656 format conversion, exports by the second high-speed parallel mouth;
Described Audio Processing output module is exported audio ES stream by high speed serial port (SPI mouth);
Described CPU module is by UART (universal asynchronous receiver transmitter) mouthful and I
2The S bus connects described Digital Signal Processing DSP module; Connect described front panel module by the GPIO holding wire; Connect PC (personal computer) machine by network interface; Described CPU module also connects the 2nd SDRAM and the 2nd FLASH;
Described CPU module utilizes FLASH that system is powered on/the zero clearing initialization; By the UART mouth control command is sent to Digital Signal Processing DSP module; Receive the TS passback code stream of removing empty bag of high speed serial port (SPORT interface) output of Digital Signal Processing DSP module by the I2S bus; With operating system nucleus, application program, intermediate data storage in the 2nd SDRAM;
Embedded Reworks/Rede (operating system of 32 research institutes of science and technology group of China Electronics exploitation) operating system nucleus on the described CPU module, and on the basis of embedded operating system kernel, transplant TCP/IP (TCP) agreement, finish the configuration of SDRAM and FLASH, operating system nucleus is transplanted, ultra-red order receives, the panel button signal receives, the compiling of instruction also is sent to Digital Signal Processing DSP module by the UART interface, the reception of Digital Signal Processing DSP module passback TS code stream, network interface drives, the driving of serial line interface etc.
Further, described main treatment circuit also comprises video d/a module and the display that connects Digital Signal Processing DSP module successively, the audio decoder module, audio frequency D/A module and the audio amplifier that connect Digital Signal Processing DSP module successively, and FPGA (field programmable gate array) module;
Described video d/a module is carried out register configuration by Digital Signal Processing DSP module by GPIO Simulation with I 2C bus; The video d/a module is carried out digital-to-analogue conversion to the decoding rear video signal of the ITU-T656 standard of Digital Signal Processing DSP module output, and the analog video signal after the conversion is outputed to display;
Described audio decoder module flows by the audio ES that SPI (serial peripheral interface) bus receives the output of Digital Signal Processing DSP module, carries out audio decoder;
Obtain the left and right acoustic channels audio signal after PCM (pulse code modulation) data transaction of described audio frequency D/A module to audio decoder module output, with this left and right acoustic channels audio signal output to audio amplifier;
Described FPGA module receives high trigger signal, to this signal carry out anti-phase after, the low level reset signal is provided for CPU module, Digital Signal Processing DSP module, audio frequency D/A module; Receive the clock of the active crystal oscillator input of 27MHZ, be divided into 2 the tunnel and export to Digital Signal Processing DSP module and video d/a module; Reception is from 6 tunnel high trigger signal of front panel module, to this signal carry out anti-phase after, produce 6 tunnel low level triggering signals, and export to the CPU module.
Described front panel module connects main treatment circuit by holding wire, has the function of infrared remote control instruction, panel button reception, channel information demonstration;
Described power module is connected main treatment circuit by first power line with the second source line, is main treatment circuit power supply.
A kind of satellite digital television receiver set top box based on embedded technology provided by the invention adopts embedded system structure triturating machine top box, has strengthened function; Under the bandwidth of same satellite transponder, the satellite channel number of transmission is increased, improved channel utilization.
Description of drawings
Fig. 1 is the structural representation of transmitting terminal in the satellite digital television system in the background technology;
Fig. 2 is the structural representation of subscriber terminal equipment in the satellite digital television system in the background technology;
Fig. 3 is the structural representation of a kind of satellite digital television receiver set top box based on embedded technology provided by the invention;
Fig. 4 is the structural representation of the main treatment circuit of a kind of satellite digital television receiver set top box based on embedded technology provided by the invention.
Embodiment
Followingly specify a kind of preferred forms of the present invention according to Fig. 3, Fig. 4:
As shown in Figure 3, the invention provides a kind of satellite digital television receiver set top box, comprise main treatment circuit 1 based on embedded technology, and the front panel module 2 and the power module 3 that are connected with main treatment circuit 1 respectively;
As shown in Figure 4, described main treatment circuit 1 comprises tuning and demodulation module 101, Digital Signal Processing DSP module 102 and the CPU module 103 that connects successively;
Describedly tuningly comprise tuner module and the channel demodulation module that is connected successively with demodulation module 101;
The status register of described tuner module inside writes configuration by Digital Signal Processing DSP module 102 by the I2C bus, the correct back of configuration operate as normal; The input input satellite RF signal of demodulation module outputs to T, the P passage intermediate-freuqncy signal that obtains in the channel demodulation module;
The input of described channel demodulation module connects the output of described tuner module, adopt the QPSK channel demodulation, T, the P passage intermediate-freuqncy signal of input are carried out channel demodulation after output signal be: the TS code stream of 8bit and line output, TS code stream output clock, TS code stream synchronizing signal;
Described Digital Signal Processing DSP module 102 is connected described tuning and demodulation module 101 by GPIO Simulation with I 2C bus with high-speed parallel mouth 1, described Digital Signal Processing DSP module 102 comprises demultiplexing module, looks the audio sync module, video decode module and Audio Processing output module, and described Digital Signal Processing DSP module 102 also connects a SDRAM1021 and a FLASH1022;
Described Digital Signal Processing DSP module 102 utilizes FLASH1022 that system is powered on/the zero clearing initialization; Write each register configuration toward tuning with demodulation module 101 by GPIO Simulation with I 2C bus; Receive TS code streams tuning and demodulation module 101 outputs by high-speed parallel mouth 1, by interruption and dma controller and be cached among the SDRAM1021 in the Digital Signal Processing DSP module 102;
Described demultiplexing module is carried out demultiplexing to the TS code stream that is cached among the SDRAM1021, obtains video ES stream, audio ES stream, DTS, PTS, PCR;
Describedly look the utilization of audio sync module begins decode time DTS, broadcast start time PTS, reference clock PCR carries out Synchronization Control to looking audio frequency;
Described video decode module is carried out the AVS video decode to video ES stream, and decoded digital video signal is carried out the ITU-T656 format conversion, by 2 outputs of high-speed parallel mouth;
Described Audio Processing output module is exported audio ES stream by high speed serial port;
Described CPU module 103 is connected described Digital Signal Processing DSP module 102 by the UART mouth with the I2S bus; Connect described front panel module 2 by the GPIO holding wire; Connect PC by network interface; Described CPU module 103 also connects a SDRAM1031 and a FLASH1032;
Described CPU module 103 utilizes FLASH1032 that system is powered on/the zero clearing initialization; By the UART mouth control command is sent to Digital Signal Processing DSP module 102; Receive the TS passback code stream of removing empty bag of the high speed serial port output of Digital Signal Processing DSP module 102 by the I2S bus; With operating system nucleus, application program, intermediate data storage in SDRAM1031;
Embedded the Reworks/Rede operating system nucleus on the described CPU module 103, and on the basis of embedded operating system kernel, transplant ICP/IP protocol, the configuration, operating system nucleus of finishing SDRAM1031 and FLASH1032 transplanted, ultra-red order receives, the panel button signal receives, the compiling of instruction and by reception, network interface that the UART interface is sent to Digital Signal Processing DSP module 102, Digital Signal Processing DSP module 102 passback TS code streams drive, the driving of serial line interface etc.
Further, described main treatment circuit 1 also comprises video d/a module 104 and the display 105 that connects Digital Signal Processing DSP module 102 successively, the audio decoder module 106, audio frequency D/A module 107 and the audio amplifier 108 that connect Digital Signal Processing DSP module 102 successively, and FPGA109 (field programmable gate array) module;
Described video d/a module 104 is carried out register configuration by Digital Signal Processing DSP module 102 by GPIO Simulation with I 2C bus; The decoding rear video signal of the ITU-T656 standard of 104 couples of Digital Signal Processing DSP of video d/a module module, 102 outputs carries out digital-to-analogue conversion, and the analog video signal after the conversion is outputed to display 105;
Described audio decoder module 106 is carried out audio decoder by the audio ES stream of spi bus receiving digital signals processing DSP module 102 outputs;
Obtain the left and right acoustic channels audio signal after the PCM data transaction of 107 pairs of audio decoder modules of described audio frequency D/A module 106 output, with this left and right acoustic channels audio signal output to audio amplifier 108;
Described FPGA module 109 receives high trigger signal, to this signal carry out anti-phase after, the low level reset signal is provided for CPU module 103, Digital Signal Processing DSP module 102, audio frequency D/A module 107; Receive the clock of the active crystal oscillator input of 27MHZ, be divided into 2 the tunnel and export to Digital Signal Processing DSP module 102 and video d/a module 104; Reception is from 6 tunnel high trigger signal of front panel module 2, to this signal carry out anti-phase after, produce 6 tunnel low level triggering signals, and export to CPU module 103.
Described front panel module 2 connects main treatment circuit 1 by holding wire, has the function of infrared remote control instruction, panel button reception, channel information demonstration;
Described power module 3 is connected main treatment circuit 1 by power line 1 with power line 2, be main treatment circuit 1 power supply.
A kind of satellite digital television receiver set top box based on embedded technology provided by the invention adopts embedded system structure triturating machine top box, has strengthened function; Under the bandwidth of same satellite transponder, the satellite channel number of transmission is increased, improved channel utilization.
Claims (10)
1. the satellite digital television receiver set top box based on embedded technology is characterized in that, comprises main treatment circuit (1), and front panel module (2) that is connected with main treatment circuit (1) respectively and power module (3);
Described main treatment circuit (1) comprises tuning and demodulation module (101), digital signal processing module (102) and the CPU module (103) that connects successively;
Described digital signal processing module (102) is implanted integrated circuit (IC) bus by general I/O simulation and is connected described tuning and demodulation module (101) with the first high-speed parallel mouth, described digital signal processing module (102) comprises demultiplexing module, looks the audio sync module, video decode module and Audio Processing output module, and described digital signal processing module (102) also connects first synchronous DRAM (1021) and first flash memory (1022);
Described digital signal processing module (102) utilizes first flash memory (1022) that system is powered on/the zero clearing initialization; Implant integrated circuit (IC) bus by general I/O simulation and write each register configuration with demodulation module (101) toward tuning; Receive transmission code stream tuning and demodulation module (101) output by the first high-speed parallel mouth, by interrupting and direct memory access (DMA) controller and being cached in first synchronous DRAM (1021) in the digital signal processing module (102);
Described CPU module (103) is connected described digital signal processing module (102) by universal asynchronous receiver transmitter mouth with the implantation integrated circuit (IC) bus; Connect described front panel module (2) by general input/output signal line; Connect personal computer by network interface; Described CPU module (103) also connects second synchronous DRAM (1031) and second flash memory (1032).
2. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, describedly tuningly comprises tuner module and the channel demodulation module that is connected successively with demodulation module (101);
The status register of described tuner module inside writes configuration by digital signal processing module (102) by implanting integrated circuit (IC) bus, the correct back of configuration operate as normal; The input input satellite RF signal of demodulation module outputs to the intermediate-freuqncy signal that obtains in the channel demodulation module;
The input of described channel demodulation module connects the output of described tuner module, adopt the Quadrature Phase Shift Keying channel demodulation, the intermediate-freuqncy signal of input is carried out channel demodulation after output signal be: the transmission code stream of 8 bit parallels output, transmission code stream output clock, transmission code stream synchronizing signal.
3. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1, it is characterized in that, described demultiplexing module is carried out demultiplexing to the transmission code stream that is cached in the synchronous DRAM (1021), obtains video-frequency basic flow, audio frequency flows, begins decode time, broadcast start time, reference clock substantially.
4. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, describedly looks the utilization of audio sync module and begins decode time, broadcast start time, reference clock and carry out Synchronization Control to looking audio frequency;
Described video decode module is carried out the AVS video decode to video-frequency basic flow, and decoded digital video signal is carried out the ITU-T656 format conversion, exports by the second high-speed parallel mouth;
Described Audio Processing output module flows audio frequency substantially by high speed serial port to be exported.
5. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, described CPU module (103) utilizes flash memory (1032) that system is powered on/the zero clearing initialization; By universal asynchronous receiver transmitter mouth control command is sent to digital signal processing module (102); The transmission of removing empty bag of exporting by the high speed serial port of implanting integrated circuit (IC) bus receiving digital signals processing module (102) returns code stream; With operating system nucleus, application program, intermediate data storage in SDRAM (1031);
Embedded Reworks/Rede operating system nucleus on the described CPU module (103), and on the basis of embedded operating system kernel, transplanted ICP/IP protocol by the exploitation of 32 research institutes of science and technology group of China Electronics.
6. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, described main treatment circuit (1) also comprises video d/a module (104) and the display (105) that connects digital signal processing module (102) successively; Described video d/a module (104) is implanted integrated circuit (IC) bus by digital signal processing module (102) by general I/O simulation and is carried out register configuration; Video d/a module (104) is carried out digital-to-analogue conversion to the decoding rear video signal of the ITU-T656 standard of digital signal processing module (102) output, and the analog video signal after the conversion is outputed to display (105).
7. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1, it is characterized in that described main treatment circuit (1) also comprises audio decoder module (106), audio frequency D/A module (107) and the audio amplifier (108) that connects digital signal processing module (102) successively;
Described audio decoder module (106) provides the audio frequency of bus interface receiving digital signals processing module (102) output to flow substantially by service, carries out audio decoder;
Obtain the left and right acoustic channels audio signal after the pulse code modulation data conversion of described audio frequency D/A module (107) to audio decoder module (106) output, with this left and right acoustic channels audio signal output to audio amplifier (108).
8. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, described main treatment circuit (1) also comprises programmable gate array module (109);
Described field programmable gate array module (109) receives high trigger signal, to this signal carry out anti-phase after, the low level reset signal is provided for CPU module (103), digital signal processing module (102), audio frequency D/A module (107); Receive the clock of the active crystal oscillator input of 27MHZ, be divided into 2 the tunnel and export to digital signal processing module (102) and video d/a module (104); Reception is from 6 tunnel high trigger signal of front panel module (2), to this signal carry out anti-phase after, produce 6 tunnel low level triggering signals, and export to CPU module (103).
9. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, described front panel module (2) connects main treatment circuit (1) by holding wire.
10. the satellite digital television receiver set top box based on embedded technology as claimed in claim 1 is characterized in that, described power module (3) is connected main treatment circuit (1) by first power line with the second source line, is main treatment circuit (1) power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005101111483A CN1777230A (en) | 2005-12-05 | 2005-12-05 | Satellite digital television receiver set top box based on embedded technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005101111483A CN1777230A (en) | 2005-12-05 | 2005-12-05 | Satellite digital television receiver set top box based on embedded technology |
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| Publication Number | Publication Date |
|---|---|
| CN1777230A true CN1777230A (en) | 2006-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005101111483A Pending CN1777230A (en) | 2005-12-05 | 2005-12-05 | Satellite digital television receiver set top box based on embedded technology |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100533380C (en) * | 2007-11-30 | 2009-08-26 | 上海广电（集团）有限公司中央研究院 | Upgrade system and upgrade method based on DSP |
| CN103581742A (en) * | 2013-10-28 | 2014-02-12 | 南京熊猫电子股份有限公司 | Method for converting encrypted audio stream into PCM codes on high-definition set top box |
| CN103778389A (en) * | 2012-10-18 | 2014-05-07 | 美国博通公司 | Integration of untrusted framework component with secure operating system environment |
-
2005
- 2005-12-05 CN CNA2005101111483A patent/CN1777230A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100533380C (en) * | 2007-11-30 | 2009-08-26 | 上海广电（集团）有限公司中央研究院 | Upgrade system and upgrade method based on DSP |
| CN103778389A (en) * | 2012-10-18 | 2014-05-07 | 美国博通公司 | Integration of untrusted framework component with secure operating system environment |
| CN103581742A (en) * | 2013-10-28 | 2014-02-12 | 南京熊猫电子股份有限公司 | Method for converting encrypted audio stream into PCM codes on high-definition set top box |
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