CN1776782A

CN1776782A - Plasma display apparatus and driving method thereof

Info

Publication number: CN1776782A
Application number: CNA2005100881791A
Authority: CN
Inventors: 李基凡; 郑允权; 金默熙
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 2004-11-19
Filing date: 2005-07-29
Publication date: 2006-05-24
Anticipated expiration: 2025-07-29
Also published as: CN100428301C; KR100656703B1; KR20060056162A

Abstract

The present invention relates to a plasma display apparatus and a driving method thereof in which an erroneous discharge, a misdischarge and an abnormal discharge are prevented, a darkroom contrast is increased, an operation margin is widened, and an influence of a lower substrate wall charge is reduced in a sustain discharge. The plasma display apparatus and its driving method is characterized in that when the plasma display panel has a second temperature higher than a first temperature, a period between the last sustain pulse generated during a sustain period of (n-1) th sub-field (''n'' is a positive integer) and an initialization signal generated during a reset period of n th sub-field is more lengthened than when it has the first temperature. The plasma display apparatus and its driving method is characterized in that a pre sustain pulse (PRESUSP) rising from a sustain bias voltage (Vzb) is applied to the second electrode in the sustain period.

Description

Plasma display panel device and driving method thereof

The application requires the patented claim No.10-2004-0095451 that submits in Korea S on November 19th, 2004 and the right of priority of the patented claim No.10-2004-0095455 that submits in Korea S on November 19th, 2004, and it is comprised fully and be incorporated herein by reference at this in full.

Technical field

The present invention relates to plasma display panel device.More specifically say, the present invention relates to plasma display panel device and driving method thereof, wherein prevent erroneous discharge or improper discharge, increased darkroom contrast, widened margin of operation, and reduced the influence of keeping subtegulum wall electric charge in the discharge.

Background technology

Plasma display panel device is by by showing when the ultraviolet ray excited fluorescent material that produces such as the noble gas discharge of He+Xe, Ne+Xe or He+Ne+Xe the time.In plasma display panel device, not only promoted the size of Bao Heda, and because recent technical progress has improved image quality.

In Fig. 1, for gray scale images, drive plasma display panel device by a frame being divided into several height field, wherein each son field has different light emitting times.Divide each son to have the reset cycle of initialization entire image, be used to select sweep trace and, and be used for keeping the cycle based on discharge time concrete manifestation gray level at the addressing period of selected scanning line selection discharge cell.For example, when with 256 gray level display images, will be divided into eight sons (SF1 is to SF8) corresponding to 1/60 second frame period (16.67ms).As mentioned above, each in eight sons (SF1 is to SF8) is divided into reset cycle, addressing period and keeps the cycle.In each son field, the reset cycle is identical with addressing period, yet for each son field, the number of keeping pulse of keeping cycle and distribution is with 2 ⁿThe ratio of (wherein n=0,1,2,3,4,5,6,7) increases.

Fig. 2 shows the schematic plan view of the arrangement of electrodes of existing three electrode AC creeping discharge type Plasmia indicating panels (hereinafter, being called PDP).

In Fig. 2, AC creeping discharge type PDP is included in the scan electrode (Y1-Yn) that forms on the substrate and keeps electrode (Z); On subtegulum, form and with scan electrode (Y1 is to Yn) with keep the rectangular addressing electrode of electrode (Z) (X1-Xm).

Scan electrode (Y1-Yn), keep electrode (Z) and addressing electrode (X1-Xm) the point of crossing with matrix arrangement discharge cell 1, to represent redness, green and blue any one.

Have scan electrode (Y1-Yn) and keeping the last substrate upper strata piezoelectric dielectric layer and the MgO protective seam of electrode (Z).

On subtegulum, form barrier rib, obscure to prevent light and electricity between neighboring discharge cells 1 with addressing electrode (X1-Xm).On subtegulum and barrier rib, form fluorescent material and by ultraviolet excitation, thus visible emitting.

To be infused in the discharge space that is provided with between the last substrate of PDP and the subtegulum such as the inert gas of He+Xe, Ne+Xe or He+Ne+Xe.

Fig. 3 shows the drive waveforms of the PDP that is applied to Fig. 2.The drive waveforms of Fig. 3 is described to the wall CHARGE DISTRIBUTION of 4E with reference to figure 4A.

In Fig. 3, each son (SFn-1, SFn) comprise reset cycle (RP) of the discharge cell 1 that is used for the initialization entire image, be used to select the addressing period (AP) of discharge cell, be used to keep the keeping the cycle (SP) and be used for wiping erase cycle (EP) of discharge of selected discharge cell 1 at the wall electric charge of discharge cell 1.

In the erase cycle (EP) of n-1 son (SFn-1), will wipe tilt waveform (ERR) and be applied to and keep electrode (Z).During erase cycle (EP), be added to scan electrode (Y) and addressing electrode (X) with 0 volt.Wiping tilt waveform (ERR) is the positive tilt waveform that rises to positive tilt waveform (Vs) gradually from 0 volt.By wiping tilt waveform (ERR), produce therein and keep the opening in the unit (on-cell) of discharge, at scan electrode (Y) with keep between the electrode (Z) and produce erasure discharge.As a result, in erase cycle (EP) afterwards, each discharge cell 1 has the wall CHARGE DISTRIBUTION of Fig. 4 A.

Set up the cycle (SU) in reset cycle (RP) of n (SFn) beginning is added to all scan electrodes (Y) with positive tilt waveform (PR), and 0V is added to keeps electrode (Z) and addressing electrode (X).By the positive tilt waveform (PR) in the cycle of setting up (SU), the voltage of scan electrode (Y) rises to gradually and is higher than the positive resetting voltage of keeping voltage (Vs) (Vr) from the positive voltage (Vs) of keeping.By positive tilt waveform (PR), between scan electrode (Y) and addressing electrode (X), produce the dark discharge produce light hardly, and in the discharge cell of entire image at scan electrode (Y) with keep the dark discharge that generation simultaneously produces light hardly between the electrode (Z).As the result of dark discharge, the cycle of setting up (SU) afterwards, shown in Fig. 4 B, positive wall electric charge is stayed addressing electrode (X) and is kept on the electrode (Z), and negative wall electric charge is stayed on the scan electrode (Y).When the cycle of setting up (SU) produces dark discharge, will and keep between the electrode (Z) and the gap voltage (Vg) between scan electrode (Y) and addressing electrode (X) is initialized as the approaching trigger voltage (Vf) that causes discharge at scan electrode (Y).

The setting up the cycle of reset cycle (RP) (SU) removing the cycle afterwards (SD), negative tilt waveform (NR) is added to scan electrode.Simultaneously, the positive voltage (Vs) of keeping is added to and keeps electrode (Z), and 0V is added to addressing electrode.By negative tilt waveform (NR), the voltage of scan electrode (Y) drops to negative erasing voltage (Ve) from the positive voltage (Vs) of keeping.Tilt waveform (NR) by negative produces dark discharge between scan electrode (Y) and addressing electrode (X), and its in the whole discharge cell of entire image at scan electrode (Y) with keep generation simultaneously between the electrode (Z).As the result of the dark discharge in the cycle of removing (SD), the wall CHARGE DISTRIBUTION of each discharge cell 1 is changed to optimum addressing condition, shown in Fig. 4 C.At this moment, the too much wall electric charge that does not need to be used for address discharge is wiped from scan electrode (Y) and addressing electrode (X), and the wall electric charge of scheduled volume is stayed in each discharge cell 1.Keep on the electrode (Z) along with negative wall electric charge moves and is accumulated in from scan electrode (Y), keep the polarity of the positive wall electric charge of electrode (Z) and reverse to negative polarity.When removing the cycle in (SD) of reset cycle (RP) produces dark discharge, scan electrode (Y) and keep electrode (Z) and gap voltage between scan electrode (Y) and addressing electrode (X) near trigger voltage (Vf).

In addressing period (AP), with negative scanning impulse (SCNP) sequentially be added to scan electrode (Y), and simultaneously and negative scanning impulse (SCNP) synchronously positive data pulse (DP) is added to addressing electrode (X).(voltage SCNP) is to drop to negative scanning voltage (scanning voltage Vy) (Vsc) from 0V or near its negative scan bias voltage (Vyb) to scanning impulse.The voltage of data pulse (DP) is positive data voltage (Va).During addressing period (AP), will be lower than the positive positive Z bias voltage (Vzb) of keeping voltage (Vs) and be provided to and keep electrode (Z).Because therein in reset cycle (RP) afterwards in the state of adjusting play voltage near trigger voltage (Vf), gap voltage between scan electrode (Y) and addressing electrode (X) surpasses trigger voltage (Vf), (Y produces address discharge between X) at the electrode of opening the unit of having used scanning voltage (Vsc) and data voltage (Va).The main address discharge that produces between scan electrode (Y) and addressing electrode (X) produces the particle that charges in discharge cell, to cause at scan electrode (Y) and to keep secondary discharge between the electrode (Z), shown in Fig. 4 D.Fig. 4 E shows the wall CHARGE DISTRIBUTION in the unit opened that produces address discharge therein.

The wall CHARGE DISTRIBUTION that does not wherein produce the closing unit (off-cell) of address discharge is kept the state of Fig. 4 C basically.

In the cycle of keeping (SP), the positive pulse (SUSP) of keeping of keeping voltage (Vs) alternately is added to scan electrode (Y) and keeps electrode (Z).By doing like this, keep pulse (SUSP) because the wall CHARGE DISTRIBUTION of Fig. 4 E and at scan electrode (Y) with keep between the electrode (Z) generation and keep discharge at each by the unit of opening that address discharge is selected.Opposite, closing unit does not produce discharge during the cycle of keeping.This is because the wall CHARGE DISTRIBUTION of closing unit is kept the state of Fig. 4 C, and therefore, when with positive when keeping voltage (Vs) and being added to scan electrode (Y), can not surpass trigger voltage (Vf) at scan electrode (Y) and the gap voltage kept between the electrode (Z).

But, the shortcoming that the plasma display panel device of prior art has is: during the reset cycle (RP) of the erase cycle (EP) of n-1 (SFn-1) and n field (SFn), initialization discharge cell 1 and execution multiple discharge are used to control the wall electric charge, have reduced the darkroom contrast value thus and have therefore reduced contrast-ratio.In table 1, electric discharge type and the formerly erase cycle (EP) of son (SFn-1) and the discharge time of execution in the reset cycle (RP) in the plasma display panel device of prior art have been arranged.

Table 1

As shown in table 1, when opening the unit n-1 (SFn-1) conducting, in erase cycle (EP) with during the reset cycle (RP), at scan electrode (Y) with keep between the electrode (Z) and to carry out the discharge of three subsurfaces, and between scan electrode (Y) and addressing electrode (X), produce discharge on the contrary for twice (opposite discharge).When son (SFn) stopping unit formerly, in erase cycle (EP) with during the reset cycle (RP), at scan electrode (Y) with keep between the electrode (Z) and to produce twice surface-discharge, and between scan electrode (Y) and addressing electrode (X), produce twice and discharge on the contrary.

Discharge time in erase cycle and reset cycle execution makes in erase cycle and photoemissive amount increase in the reset cycle, has reduced the darkroom contrast value thus.Consider contrast-response characteristic, if possible the light emission measure should minimize.Specifically, because a large amount of light emissions of opposite discharge generation are compared in surface-discharge, surface-discharge is compared opposite discharge for darkroom contrast and is had very different influence.

In the plasma display panel device of prior art, because do not wipe the wall electric charge well in the erase cycle (EP) of n-1 son (SFn-1), negative wall electric charge is accumulation too much on scan electrode (Y).Therefore, do not produce dark discharge in (SU) n setting up the cycle of (SFn).If in abnormal execution dark discharge of the cycle of setting up (SU), then discharge cell is not initialised.Therefore, should increase resetting voltage (Vr), in the cycle of setting up, to produce discharge.If (SU) do not carry out dark discharge in the cycle of setting up, then after the reset cycle discharge cell not in optimum addressing condition.Therefore, cause improper discharge or erroneous discharge.Go up under the situation of too much accumulation at scan electrode (Y) at the positive afterwards wall electric charge of the erase cycle (EP) of n-1 (SFn-1) therein, produce strong discharge, thus when setting up the cycle in (SU) at n (SFn), in the time of will keeping voltage (Vs) and be added to scan electrode (Y) as the initial voltage of positive tilt waveform (PR) positive, the whole discharge cell of initialization unevenly.Above-mentioned shortcoming will be described in detail with reference to figure 5 time.

Fig. 5 shows and is applied to scan electrode (Y) and keeps external voltage (Vyz) between the electrode (Z) and the gap voltage (Vg) in the discharge cell in the cycle of setting up (SU).Here, use the solid line of Fig. 5 to show the voltage (Vyz) that the outside applies, and it is added to each scan electrode (Y) and keeps electrode (Z).Because 0V is added to keeps electrode (Z), the voltage that the outside applies (Vyz) is substantially equal to positive tilt waveform (PR).In Fig. 5, the gap voltage (Vg) that 1., 2. and 3. dotted line indicates in discharge gas the wall electric charge by discharge cell to form.This gap voltage (Vg) is different shown in 1., 2. with 3. as dotted line, and this is because the wall quantity of electric charge in the discharge cell is different according to whether producing discharge in the son formerly.External voltage (Vyz) is added to scan electrode (Y) and keeps between the electrode (Z).In the discharge gas of discharge cell, form gap voltage (Vg).

The relation of external voltage (Vyz) and gap voltage (Vg) is shown in following equation 1:

Vyz=Vg+Vw equation 1

In Fig. 5, " 1. " expression is wherein fully wiped in discharge cell and the gap voltage (Vg) when minimizing the wall electric charge.The increase if gap voltage (Vg) and the outside voltage (Vyz) that applies are directly proportional, and arrive trigger voltage (Vf), then produce dark discharge.By dark discharge, in discharge cell, gap voltage is initialised to trigger voltage (Vf).

In Fig. 5, " 2. " expression wherein during the erase cycle (EP) of n-1 (SFn-1) the strong discharge of generation with the gap voltage (Vg) of the polarity chron that is reversed in the wall electric charge in the wall CHARGE DISTRIBUTION in the discharge cell.In erase cycle (EP) soon afterwards, because negative wall electric charge forward ground counter-rotating on polarity of accumulating is gone up in strong discharge at scan electrode (Y).This is by having low inhomogeneity discharge cell or causing according to the tilt waveform (ERR) of wiping that the temperature variation in large-sized Plasmia indicating panel changes by its slope.At this moment, as shown in Figure 5, primary clearance voltage (Vg) transition increases, and therefore, in the cycle of setting up (SU), the positive voltage (Vs) of keeping is added to scan electrode (Y), and simultaneously, gap voltage (Vg) surpasses trigger voltage (Vf), produces strong discharge thus.By strong discharge, discharge cell is not initialised to have the wall CHARGE DISTRIBUTION of optimum addressing condition, in other words, has the wall CHARGE DISTRIBUTION of Fig. 4 C in cycle of setting up (SU) and erase cycle (EP), and therefore, can in the closing unit that should be cut off, produce address discharge.In other words, when before the reset cycle when erase cycle produces strong erasure discharge, it can produce erroneous discharge.

In Fig. 5, " 3. " expression does not produce erasure discharge or very weak the gap voltage (Vg) when producing to keep the wall CHARGE DISTRIBUTION that does not change in the discharge cell wherein during the erase cycle (EP) of n-1 son field (SFn-1).Keep the result of discharge and form the wall CHARGE DISTRIBUTION as execution before erasure discharge.

In detailed description, as shown in Figure 3, in the time will keeping pulse (SUSP) and be added to scan electrode (Y), produce the last discharge of keeping.Keep the result of discharge as last, stay positive wall electric charge on the electrode (Z) staying negative wall electric charge on the scan electrode (Y) and keeping.Should wipe this wall electric charge for the normal initialization of next height field, if but do not carry out erasure discharge or very a little less than, then their polarity will remain unchanged.Because the slope that discharge cell has low homogeneity or wipes tilt waveform (ERR) do not carry out because of the change of the temperature variation of PDP erasure discharge or very a little less than.Because primary clearance voltage (Vg) is low-down negative voltage, as shown in Figure 5, reference number 3., even positive tilt waveform (RP) rises to resetting voltage (Vr) in the cycle of setting up, the gap voltage of discharge cell (Vg) does not arrive trigger voltage (Vf).Therefore, do not produce dark discharge in cycle of setting up (SU) and erase cycle (EP).As a result, when before the reset cycle when when erase cycle does not produce erasure discharge or very weak, cause erroneous discharge or improper discharge because of improper initialization.

The reference number of Fig. 5 3. in, the relation of gap voltage (Vg) and trigger voltage (Vf) is by following formula 2 expressions, and the reference number of Fig. 5 3. in, the relation of gap voltage (Vg) and trigger voltage (Vf) is represented by following formula 3:

Vgini+Vs＞Vf formula 2

Vgini+Vr＜Vf formula 3

Vgini wherein: the primary clearance voltage before the cycle of setting up (SU) beginning, as shown in Figure 5.

Consider above-mentioned shortcoming, shown in 4, it satisfies

formula

2 and 3 to the gap voltage condition (or wall charge condition) of permission normal initialization as the following formula in cycle of setting up (SU) and reset cycle (RP):

Vf-Vr＜Vgini＜Vf-Vs formula 4

The result, if the cycle of setting up (SU) before primary clearance voltage (Vgini) do not satisfy formula 4, then the plasma display panel device of prior art can cause erroneous discharge (erroneous discharge), misplace electricity (misdiscgarge) or improper discharge, and narrow margin of operation.In other words, in the plasma display panel device of prior art, should normally carry out erase operation to guarantee job stability and surplus, still may undesired execution erase operation according to the serviceability temperature among discharge cell homogeneity or the PDP.

The shortcoming of the plasma display panel device of prior art be the wall CHARGE DISTRIBUTION because too much space discharge and they in hot environment effective momentum and become unstable, cause erroneous discharge thus, misplace electricity or improper discharge, and consequent narrow margin of operation.This will describe in detail to 6C with reference to figure 6A.

In hot environment, compare room temperature environment or low temperature environment produce space charge 61 in discharge amount and momentum.Therefore, produce space charge 61 in the discharge keeping of n-1 son (SFn-1), even and its n (SFn) set up the cycle (SU) effective exercise in discharge space afterwards, as shown in Figure 6A.

Have therein in the state that the space charge of big momentum exists in discharge space, as shown in Figure 6A, during addressing period, data voltage (Va) is added to addressing electrode (X), and scanning voltage (Vy) is added to scan electrode (Y).If like this, result as the foundation in the cycle of setting up (SU) discharge, positive space charge 61 and to go up the negative wall electric charge of accumulation at scan electrode (Y) compound again, and negative space charge 61 and to go up the positive wall electric charge of accumulation at addressing electrode (X) compound again.

As a result, wiped from scan electrode (Y) by setting up the negative wall electric charge that forms that discharges, and wiped from addressing electrode (X), shown in Fig. 6 C by setting up the positive wall electric charge that forms that discharges.Therefore, even (Vy) be added to addressing electrode (X) and scan electrode (Y), gap voltage (Vg) does not reach trigger voltage (Vf), therefore, does not produce address discharge with data voltage (Va) and scanning voltage.Therefore, exist in the hot environment, open the shortcoming that the unit writes through constant error if the drive waveforms of Fig. 3 is added to PDP.

In the plasma display panel device of prior art, if by process errors cause the subtegulum structure inhomogeneous (for example, inhomogeneous or the fluorescent material of the shape of barrier rib in uneven thickness), on amount, have a great difference at the wall electric charge of accumulating on the subtegulum between the neighboring discharge cells.Use any one adjacent discharge cell wherein as open unit and another as closing unit with only in the data pattern that the unit produces discharge of opening of a side, or use in the data-modulated of the shake mask with same effect, on amount, have a great difference at the wall electric charge of accumulating on the subtegulum between the neighboring discharge cells.If different on amount at the wall electric charge of accumulating on the subtegulum of adjacent discharge cell, and the too much accumulation on the subtegulum of unwanted closing unit of wall electric charge, closing unit erroneous discharge during the cycle of keeping then, and be shown as a point.This erroneous point discharge is caused by the big influence at the wall electric charge of keeping subtegulum under the discharge scenario, and has at the edge of subtegulum usually because the plasma display panel device of the big unevenness that process errors causes causes.

Fig. 7 shows the zoomed-in view of drive waveforms, and this waveform is added to addressing period (AP) and keeps the cycle each of electrode (X, Y and Z) between (SP).Fig. 8 shows by first and keeps the view that discharge mechanism is kept in first of pulse (FSTSUSP) generation.

With reference to figure 7 and 8, if 0V is added to addressing electrode (X) and keeps electrode (Z), then the voltage of scan electrode (Y) is kept pulse (FSTSUSP) by first and is changed to from 0V and keep voltage (Vs), produces first at corresponding discharge cell and keeps discharge.But, if the accumulation too much on the subtegulum of discharge cell of negative wall electric charge, then at scan electrode (Y) with keep and produce discharge between the electrode (Z), and simultaneously, the strong discharge of generation between scan electrode (Y) and addressing electrode (X).As mentioned above, keep discharge, and therefore, produce green or carmine point with low gray level at the angle of PDP by the wall charge affects of on subtegulum, accumulating.

Summary of the invention

Therefore, the present invention proposes a kind of plasma display panel device and driving method thereof, and it has avoided the restriction of existing prior art and one or more problems that shortcoming causes basically.

Advantage of the present invention provides the wherein plasma display panel device of stable discharging and driving method thereof under hot environment.

Another advantage of the present invention is to provide plasma display panel device and the driving method thereof that wherein reduces the influence of subtegulum wall electric charge in keeping discharge.

An advantage more of the present invention is wherein to prevent erroneous discharge, misplaces electricity and improper discharge, increases darkroom contrast and plasma display panel device and the driving method thereof of widening margin of operation.

Description of drawings

Accompanying drawing comprises in order further to understand the present invention, and be included into a part that constitutes this instructions in this instructions, these accompanying drawings show one or more embodiment of the present invention, and are used for this instructions principle of the present invention being described.In the accompanying drawings:

Fig. 1 shows the sub-field mode that is used in 8 bit default code of plasma display panel device concrete manifestation 256 gray levels;

Fig. 2 shows the schematic plan view of arrangement of electrodes of the Plasmia indicating panel of three electrode AC creeping discharge types;

Fig. 3 shows the view of the drive waveforms of general Plasmia indicating panel;

Fig. 4 A is the stepping view that is illustrated in the discharge cell wall CHARGE DISTRIBUTION that the drive waveforms by Fig. 3 changes to 4E;

Fig. 5 shows when driving Plasmia indicating panel by the drive waveforms of Fig. 3, is added to scan electrode and keeps the variation of the outside between the electrode and at the view of the gap voltage of setting up the periodic discharging unit;

Fig. 6 A is to be illustrated in the hot environment to 6C, the view of space charge when driving Plasmia indicating panel by the drive waveforms of Fig. 3 and their motion;

Fig. 7 shows the enlarged drawing of the drive waveforms of Fig. 3, at addressing period with during keeping edge cycle between the cycle it is added to each electrode;

Fig. 8 shows the view of being kept the discharge mechanism of pulse generation in keeping discharge by first of Fig. 7;

Fig. 9 shows the oscillogram according to the driving method that is used for plasma display panel device of first embodiment of the invention;

Figure 10 shows the drive waveforms figure according to the first son field of the driving method that is used for plasma display panel device of second embodiment of the invention;

Figure 11 shows the drive waveforms figure according to the first son field of the driving method that is used for plasma display panel device of third embodiment of the invention;

Figure 12 A shows in discharge cell the stepping view of the wall CHARGE DISTRIBUTION that the drive waveforms by Figure 11 changes to 12E;

Figure 13 shows according to the drive waveforms figure in the sub-field duration outside first son of the driving method that is used for plasma display panel device of third embodiment of the invention;

Figure 14 showed after the cycle of keeping, and was formed the view of wall CHARGE DISTRIBUTION in discharge cell by the drive waveforms of Figure 13;

Figure 15 showed before the cycle of setting up, the wall CHARGE DISTRIBUTION in the discharge cell that is formed by the drive waveforms of Figure 11 and 13 and the view of gap voltage;

Figure 16 shows when driving plasma display panel device by the drive waveforms of Figure 11 and 13, is added to scan electrode and keeps the variation of the external voltage between the electrode and at the view of the gap voltage of the discharge cell in the cycle of setting up;

Figure 17 shows in erase cycle with during the reset cycle, the view that the wall charge polarity that is caused by the existing drive waveforms of Fig. 3 changes;

Figure 18 shows in the reset cycle and is keeping on the electrode view that wall charge polarity that the drive waveforms by Figure 11 and 13 causes changes;

Figure 19 shows the drive waveforms figure of the first sub-field duration in according to the driving method of the plasma display panel device of fourth embodiment of the invention;

Figure 20 shows the drive waveforms figure of the sub-field duration outside the first sub-field duration in according to the driving method of the plasma display panel device of fourth embodiment of the invention;

Figure 21 shows the oscillogram according to the driving method of the plasma display panel device of fifth embodiment of the invention;

Figure 22 shows the block diagram according to the plasma display panel device of the embodiment of the invention;

Figure 23 shows the drive waveforms figure of the first sub-field duration in according to the driving method of the plasma display panel device of sixth embodiment of the invention;

Figure 24 shows the enlarged drawing of the drive waveforms of Figure 23, and it is added to each electrode at addressing period with during keeping edge cycle between the cycle with this drive waveforms;

Figure 25 A is the stepping view of the wall CHARGE DISTRIBUTION that changed by the drive waveforms of Figure 23 in discharge cell to 25F;

Figure 26 shows the drive waveforms figure of the sub-field duration outside the first sub-field duration in according to the driving method of the plasma display panel device of sixth embodiment of the invention;

Figure 27 shows after the cycle of keeping soon in discharge cell the view of the wall CHARGE DISTRIBUTION that the drive waveforms by Figure 26 forms;

Figure 28 showed before the cycle of setting up, the wall CHARGE DISTRIBUTION in discharge cell that is formed by the drive waveforms of Figure 23 and 26 and the view of gap voltage;

Figure 29 shows the oscillogram according to the driving method of the plasma display panel device of seventh embodiment of the invention;

Figure 30 shows the oscillogram according to the driving method of the plasma display panel device of eighth embodiment of the invention;

Figure 31 shows the oscillogram according to the driving method of the plasma display panel device of ninth embodiment of the invention;

Figure 32 shows the drive waveforms figure according to the first sub-field duration in the driving method of the plasma display panel device of tenth embodiment of the invention;

Figure 33 shows the drive waveforms figure according to the sub-field duration outside the first sub-field duration in the driving method of the plasma display panel device of tenth embodiment of the invention;

Figure 34 shows the drive waveforms figure according to the first sub-field duration in the driving method of the plasma display panel device of eleventh embodiment of the invention;

Figure 35 shows the drive waveforms figure according to the sub-field duration outside the first sub-field duration in the driving method of the plasma display panel device of eleventh embodiment of the invention;

Figure 36 shows the drive waveforms figure according to the first sub-field duration in the driving method of the plasma display panel device of twelveth embodiment of the invention;

Figure 37 shows the drive waveforms figure according to the sub-field duration outside the first sub-field duration in the driving method of the plasma display panel device of twelveth embodiment of the invention;

Figure 38 shows the oscillogram according to the driving method of the plasma display panel device of thriteenth embodiment of the invention;

Figure 39 shows the oscillogram according to the driving method of the plasma display panel device of fourteenth embodiment of the invention;

Figure 40 shows the drive waveforms figure according to the son field that is added to a frame period in the plasma display panel device of fifteenth embodiment of the invention; And

Figure 41 shows the block diagram of plasma display panel device according to another embodiment of the present invention.

Embodiment

Below will be in detail with reference to embodiments of the invention, the example shown in the drawings.

Be used to be stabilized in discharge under the hot environment with describing according to plasma display panel device of the present invention and driving method thereof.Afterwards, with another advantage of describing in detail according to plasma display panel device of the present invention and driving method thereof, in keeping discharge, reduce the influence of subtegulum wall electric charge.

Fig. 9 shows the oscillogram according to the driving method of the plasma display panel device of first embodiment of the invention.The drive waveforms of Fig. 9 is added to the three electrode AC creeping discharge type Plasmia indicating panels (PDP) that are similar to Fig. 2.In Fig. 9, each son (SFn-1, SFn) comprising: the reset cycle (RP) that is used for the discharge cell of initialization entire image, be used to select the addressing period (AP) of discharge cell, be used to keep the keeping the cycle (SP) and be used for wiping erase cycle (EP) of discharge of selected discharge cell at the wall electric charge of discharge cell 1.

The drive waveforms of reset cycle (RP), addressing period (AP) and the cycle of keeping (SP) and Fig. 3 identical, and therefore omit its detailed description.

In driving method, suppose that Plasmia indicating panel has first temperature and second temperature according to the plasma display panel device of first embodiment of the invention.When Plasmia indicating panel has second temperature that is higher than first temperature, longer when in the end a cycle of keeping between pulse and the initializing signal is compared it and has first temperature.During the cycle of keeping of n-1 (SFn-1), produce the last pulse (" n " is positive integer) of keeping.During the reset cycle of n (SFn), produce initializing signal.Here, second temperature that need be higher than first temperature is the high temperature more than 40 degrees centigrade.

In other words, when Plasmia indicating panel is in the hot environment more than 40 degrees centigrade, space charge damped cycle (Tdecay) is set to cause the decay of keeping the space charge between the rising point of positive tilt waveform (PR) of reset cycle (RP) beginning of the rising point of pulse (LSTSUSP) and n (SFn) in last of n-1 (SFn-1).

It is longer in than room temperature environment in the hot environment more than 40 degrees centigrade that space charge damped cycle (Tdecay) is set.The space charge damped cycle is in the scope of about 200 μ s to 500 μ s.During space charge damped cycle (Tdecay), decay because of the compound again of the other side and with the compound again of wall electric charge at the space charge of keeping to produce in the discharge of n-1 son (SFn-1).After the space charge decay, during the reset cycle (RP) of n (SFn), carry out continuously and set up discharge and remove discharge.As a result, reset cycle (RP) of n (SFn) afterwards, shown in Fig. 4 C, come each discharge cell of initialization with the preferred wall CHARGE DISTRIBUTION of the address discharge that does not almost have space charge state.

During the erase cycle (EP) of space charge damped cycle (Tdecay), will wipe tilt waveform (ERR) and be added to and keep electrode (Z) to cause erasure discharge.Wiping tilt waveform (ERR) is positive tilt waveform, and it rises to the positive voltage (Vs) of keeping gradually from 0V.Carry out and to keep the opening in the unit of discharge by wiping tilt waveform (ERR) therein, at scan electrode (Y) with keep between the electrode (Z) and carry out erasure discharge.

Figure 10 shows the oscillogram according to the driving method of the plasma display panel device of second embodiment of the invention.

The drive waveforms of Figure 10 can be applied to wherein only using previous sub last to keep the ensuing PDP that removes discharge that discharge comes the initialization discharge cell and do not use foundation discharge and its next height field, in other words, be applied to have the PDP of the wide driving surplus of high uniformity and discharge cell.

With reference to Figure 10, n-1 son (SFn-1) comprise reset cycle (RP), addressing period (AP) and keep the cycle (SP), n field (SFn) comprise only have the cycle of removing and do not set up the cycle reset cycle (RP), addressing period (AP), keep the cycle (SP) and erase cycle (EP).

Addressing period (AP) is identical with the drive waveforms of the embodiment of Fig. 3 and Fig. 9 with the cycle of keeping (SP), therefore omits its detailed description.

At the driving method that is used for plasma display panel device according to second embodiment of the invention, space charge damped cycle (Tdecay2) is set, to cause the decay that forms the space charge between the drop point of (PR) at the negative tilt waveform that last of n-1 (SFn-1) kept reset cycle (RP) beginning of the rising point of pulse (LSTSUSP) and n (SFn) in hot environment.

Space charge damped cycle (Tdecay2) is identical with last pulse width of keeping pulse, and it is set, and to compare room temperature environment in the hot environment more than 40 degrees centigrade longer.Space charge damped cycle (Tdecay2) in hot environment in the scope of about 200 μ s to 500 μ s.During space charge damped cycle (Tdecay2), last that keep voltage (Vs) kept pulse (LSTSUSP) and is added to scan electrode (Y) and keeps voltage (Vs).From last is kept time point that pulse (LSTSUSP) is added to scan electrode (Y) through the schedule time (Td) afterwards, will keep voltage (Vs) and be added to and keep electrode (Z).By this voltage, during space charge damped cycle (Tdecay2), go up the negative space charge of accumulation and go up the positive space charge of accumulation at addressing electrode (X) at scan electrode (Y).Therefore, at space charge damped cycle (Tdecay2) afterwards, be similar to the foundation discharge result's of prior art wall CHARGE DISTRIBUTION, in other words, come each discharge cell of initialization to be similar to the wall CHARGE DISTRIBUTION that space charge major part wherein is dispersed in Fig. 4 B of each discharge cell.

At space charge damped cycle (Tdecay2) afterwards, during the reset cycle (RP (SD)) of n (SFn), negative tilt waveform (NR) is added to scan electrode (Y).During the reset cycle (RP (SD)), the positive voltage (Vs) of keeping is added to and keeps electrode (Z), and 0V is added to addressing electrode (X).By negative tilt waveform (NR), the voltage of scan electrode (Y) drops to negative erasing voltage (Ve) gradually from the positive voltage (Vs) of keeping.Tilt waveform (NR) by negative produces dark discharge between scan electrode (Y) and addressing electrode (X) in the discharge cell of entire image, and the while, at scan electrode (Y) with keep between the electrode (Z) and produce dark discharge.As the result of the dark discharge in the cycle of removing (SD), the wall CHARGE DISTRIBUTION of each discharge cell 1 is changed to have the optimum addressing condition shown in Fig. 4 C.

Figure 11 shows the oscillogram according to the driving method of the plasma display panel device of third embodiment of the invention.The drive waveforms of Figure 11 is described referring to figures 12A through the wall CHARGE DISTRIBUTION of 12E.

Among Figure 11, by with at least one height field, for example, first son is divided into pre-reset cycle (PRERP), reset cycle (RP), addressing period (AP) and keeps the cycle (SP) and drives plasma display panel device.During the pre-reset cycle (PRERP), go up the positive wall electric charge of formation at scan electrode (Y), and keeping the upward negative wall electric charge of formation of electrode (Z).During the reset cycle (RP), use the wall CHARGE DISTRIBUTION that during the pre-reset cycle (PRERP), forms to come the discharge cell of initialization entire image.During the cycle of keeping (SP), keep the discharge of selected discharge cell.Erase cycle can be included between the reset cycle of the cycle of keeping (SP) and its next son field.

In the pre-reset cycle (PRERP), the positive voltage (Vs) of keeping is added to all and keeps electrode (Z).Afterwards, when through schedule time when (Td2), (the negative tilt waveform (NRY1) of Y V1) is added to all scan electrodes (Y) will to drop to negative voltage from 0V or ground voltage.Here, the schedule time (Td2) is according to panel characteristics and can be different.When keeping this voltage of keeping electrode (Z), the voltage of scan electrode (Y) descends and afterwards voltage (V1) is kept the schedule time.During the pre-reset cycle (PRERP), 0V is added to addressing electrode (X).

During the initial schedule time (Td2) of pre-reset cycle (PRERP), the negative space charge of discharge cell is gone up accumulation at scan electrode (Y), and by changing into the wall electric charge being added to the difference of keeping voltage (Vs) and being added between the 0V of scan electrode (Y) of keeping electrode (Z).The positive space charge of discharge cell is gone up accumulation keeping electrode (Z), and is changed and is the wall electric charge.After wiping space charge, to keep voltage (Vs) is added to and keeps electrode (Z), and the tilt waveform (NRY1) that a Y is negative is added to scan electrode (Y), they in whole discharge cell, scan electrode (Y) and keep between the electrode (Z) and keeping electrode (Z) and addressing electrode (X) between produce dark discharge.As the result of discharge, the pre-reset cycle (PRERP) afterwards, shown in Figure 12 A, in whole discharge cell, positive wall electric charge is gone up accumulation at scan electrode (Y), and negative wall electric charge is gone up accumulation keeping electrode (Z).Wall CHARGE DISTRIBUTION by Figure 12 A, in whole discharge cell, at scan electrode (Y) with keep the enough big positive gap voltage of formation between the electrode (Z), and in each discharge cell, form electric field to the direction of keeping electrode (Z) from scan electrode (Y).

At set up the cycle (SU) of reset cycle (RP), the positive tilt waveform (PRY2) of tilt waveform that a Y is positive (PRY1) and the 2nd Y is added to all scan electrodes (Y) continuously, and 0V is added to keeps electrode (Z) and addressing electrode (X).The positive tilt waveform (PRY1) of the one Y rises to the positive voltage (Vs) of keeping from 0V.The positive tilt waveform (PRY2) of the 2nd Y rises to and is higher than the positive positive Y resetting voltage (Vry) of keeping voltage (Vs) from the positive voltage (Vs) of keeping.The positive tilt waveform shape (PRY2) of the 2nd Y has the slope less than the positive tilt waveform of a Y (PRY1).Simultaneously, according to panel characteristics, the positive tilt waveform of positive tilt waveform of a Y (PRY1) and the 2nd Y can also be set to have same slope.Though with in discharge cell in scan electrode (Y) and the voltage of keeping between the electrode (Z) electric field that the forms positive tilt waveform form (PRY1) of a Y of suing for peace, in whole discharge cell, at scan electrode (Y) with keep electrode (Z) and between scan electrode (Y) and addressing electrode (X), produce dark discharge.As the result of discharge, wall electric charge negative when setting up the cycle (SU) in whole discharge cell after is gone up accumulation at scan electrode (Y), and shown in Figure 12 B, the polarity of scan electrode (Y) is reversed to negative polarity.The more accumulations on addressing electrode (X) of positive wall electric charge.Fu wall electric charge moves towards scan electrode (Y) from keeping electrode (Z) simultaneously, and their amount reduces a little, but scan electrode (Y) is kept negative polarity.

Simultaneously, the pre-reset cycle (PRERP) afterwards, before the cycle of removing (SU) produced dark discharge, gap voltage positive in whole discharge cell was enough big by the wall CHARGE DISTRIBUTION.Therefore, resetting voltage (Vr) is lower than the resetting voltage as shown in Figure 3 (Vr) of prior art.In addition, in the pre-reset cycle (PRERP) with during setting up the cycle (SU), positive wall electric charge is gone up fully accumulation at addressing electrode (X).Therefore, it can reduce the absolute value of the applied external voltage that need be used for address discharge, just, can reduce data voltage (Va) and scanning voltage (absolute value Vy).

At remove the cycle (SD) of reset cycle (RP) afterwards in the cycle of setting up (SU), the tilt waveform (NRY2) that the 2nd Y is negative is added to scan electrode (Y), and simultaneously that the 2nd Z is negative tilt waveform (NRZ2) is added to and keeps electrode (Z).The negative tilt waveform (NRY2) of the 2nd Y drops to positive voltage (V2) from the positive voltage (Vs) of keeping.The negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage from the positive voltage (Vs) of keeping.It is (V2) (V1) identical or different with the voltage of pre-reset cycle (PRERP) that voltage can be set.During the cycle of removing (SD), scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.By this dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).As a result, whole discharge cell has uniform wall electric charge and distributes, shown in Figure 12 C.In the wall CHARGE DISTRIBUTION of Figure 12 C, negative wall electric charge is fully accumulation on scan electrode, and positive wall electric charge is gone up fully accumulation at addressing electrode (X).Therefore, the gap voltage between scan electrode (Y) and addressing electrode (X) rises near trigger voltage (Vf).Therefore, the cycle of removing (SD) afterwards, the wall CHARGE DISTRIBUTION of whole discharge cell is adjusted to has optimum addressed state.

At addressing period (AP), negative scanning impulse (SCNP) be added to scan electrode (Y) sequentially, and simultaneously, and scanning impulse (is added to addressing electrode (X) with positive data pulse (DP) SCNP) synchronously.The voltage of scanning impulse (SCNP) is scanning voltage (Vsc), and it drops to negative scanning voltage (Vy) from 0V or near its negative scan bias voltage (Vyb).During addressing period (AP), will be lower than the positive positive Z bias voltage (Vzb) of keeping voltage (Vs) and be added to scan electrode Z.Have in the state of the gap voltage of adjusting to optimum addressing condition at whole afterwards discharge cell of reset cycle (RP) therein, have the opening in the unit of the scanning voltage (Vsc) that is applied to it and data voltage (Va), the gap voltage between scan electrode (Y) and addressing electrode (X) surpasses trigger voltage (Vf).If like this, only between electrode (Y and X), produce address discharge.The wall CHARGE DISTRIBUTION of opening the unit that wherein produces address discharge is shown in Figure 12 D.After producing address discharge, the wall CHARGE DISTRIBUTION of opening the unit is changed, and shown in Figure 12 E, by address discharge, positive wall electric charge is gone up accumulation at scan electrode (Y), and negative wall electric charge is gone up accumulation at addressing electrode (X).

Simultaneously, therein 0V or ground voltage are added to addressing electrode (X) or wherein 0V or scan bias voltage (Vyb) are added in the closing unit of scan electrode (Y), gap voltage is less than trigger voltage.Therefore, do not produce therein in the closing unit of address discharge, the wall CHARGE DISTRIBUTION is kept basically shown in Figure 12 C.

At the cycle of keeping (SP), the positive pulse (FISRTSUSP, SUSP and LSTSUSP) of keeping of keeping voltage (Vs) alternately is added to scan electrode (Y) and keeps electrode (Z).During the cycle of keeping (SP), 0V or ground voltage are added to addressing electrode (X).The pulse (FSTSUSP) of keeping that at first is added to each scan electrode (Y) and keeps electrode (Z) is set to have than normally keeping the bigger pulse width of pulse (SUSP), thus stable maintenance discharge initialization.In addition, keep pulse (LSTSUSP) and be added to and keep electrode (Z) last.In the initial conditions of the cycle of setting up (SU), be provided with and last keep pulse (LSTSUSP) having than normally keeping the bigger pulse width of pulse (SUSP), to go up the fully negative wall electric charge of accumulation keeping electrode (Z).During the cycle of keeping, open the unit because the cause of the wall CHARGE DISTRIBUTION of Figure 12 E is kept pulse (SUSP) at scan electrode (Y) with keep between the electrode (Z) generation and keep discharge at each by what address discharge was selected.Opposite,, keep the cycle the identical of the initial wall CHARGE DISTRIBUTION of (SP) and Figure 12 C at closing unit.Therefore, be added to closing unit, keep gap voltage, do not produce discharge thus less than trigger voltage (Vf) even will keep pulse (FISRTSUSP, SUSP and LSTSUSP).

In order to reduce the amount of the space charge that produces in keeping discharge, each is set, and to keep pulse (FISRTSUSP, SUSP and LSTSUSP) longer to have rising cycle and the decline cycle of about 340ns ± 20ns.

The drive waveforms of Figure 11 is not limited only to the first son field, but can be applicable to comprise several initial sub of first sub, and can be applicable to be included in the whole sub-field in the frame period.

Figure 13 shows in the driving method according to the plasma display panel device of third embodiment of the invention, keeping the cycle in (SP) of n-1 (SFn-1) and n (SFn), be similar to the drive waveforms that can be added to Plasmia indicating panel (PDP) of Fig. 2.Here, " n " represents the positive integer more than or equal to 2.The drive waveforms of Figure 13 is described below with reference to the wall CHARGE DISTRIBUTION of Figure 14 and 15.

In Figure 13, in n (SFn), by using afterwards at n-1 (SFn-1), for example, in first son whole unit that the wall CHARGE DISTRIBUTION that forms is come initialization PDP.

Each of n-1 (SFn-1) and n (SFn) comprises and being used for because wherein the wall electric charge of bearing fully is accumulated in the wall CHARGE DISTRIBUTION kept on the electrode (Z) and reset cycle (RP) of initialization whole unit, the keeping the cycle of discharge (SP) that be used for the addressing period (AP) of selected cell and be used to keep selected unit.

Keeping in the cycle of n-1 (SFn-1), keep pulse (LSTSUSP3) and be added to and keep electrode (Z) last.Simultaneously, 0V or ground voltage are added to scan electrode (Y) and addressing electrode (X).Setting has the enough time space charge is changed into the wall electric charge corresponding to the space charge damped cycle (Tdecay3) of the last pulse width of keeping pulse (LSTSUSP3), cause the discharge of keeping of opening in the unit thus, and wipe this space charge from discharge cell before in the reset cycle (RP) of n (SFn).For this reason, space charge damped cycle (Tdeeay3) is set for having about 200 μ s, keeps pulse (LSTSUSP3) and maintain and keep voltage (Vs) last at it to 500 μ.

By keeping pulse (LSTSUSP3) at scan electrode (Y) with keep the discharge that produces between the electrode (Z) by last, positive wall electric charge is gone up fully accumulation at scan electrode (Y), and negative wall electric charge is being kept upward fully accumulation of electrode (Z), and does not almost have space charge, as shown in figure 14.

At set up the cycle (SU) of n (SFn), the wall CHARGE DISTRIBUTION of Figure 14 is used to produce dark discharge on whole unit, and initialization whole unit thus is to the wall CHARGE DISTRIBUTION shown in Figure 12 B.Setting up the cycle (SU) operation ensuingly removes initialization, addressing and keeps operation identical with the drive waveforms of Figure 11 basically with it.

In plasma display panel device and driving method thereof, in hot environment, space charge changed into the wall electric charge with initialization wall CHARGE DISTRIBUTION stably according to third embodiment of the invention.The cycle of setting up of next height field is son keep after the discharge at last formerly, and be not used in the erase cycle of the wall electric charge between reset cycle of cycle of keeping of wiping formerly son and next son field.Because keeping discharge is strong light emitting discharge, it can and keep electrode (Z) and go up the fully a lot of wall electric charge of accumulation at scan electrode (Y), and can stable maintenance at the positive wall electric charge on the scan electrode (Y) with keeping the polarity of the negative wall electric charge on the electrode (Z).

Figure 15 shows the cell gap voltage status of being discharged or discharging and being formed by last the keeping of pre-reset cycle (PRERP).

In Figure 15, by the last waveform of keeping pulse (LSTSUSP) (NRY1, PRZ and NRZ1) of pre-reset cycle (PRERP), at scan electrode (Y) with keep between the electrode (Z) and to produce discharge.Therefore, the cycle of setting up (SU) before, in the unit, by pointing to primary clearance voltage (Vgini-yz) between the Y-Z that the electric field keep electrode (Z) forms from scan electrode (Y), and by forming primary clearance voltage (Vgini-yx) Y-X by scan electrode (Y) to the electric field of addressing electrode (X) direction.

Primary clearance voltage (Vgini-yz) is formed in the unit in the cycle of setting up (SU) before by the wall CHARGE DISTRIBUTION of Figure 15 between Y-Z.Therefore, if, then during the cycle of setting up (SU), in discharge cell, produce dark discharge by being applied to external voltage in the voltage difference between the primary clearance voltage (Vgini-yz) between trigger voltage (Vf) and Y-Z.This can be represented by following formula 5:

Vyz=Vf-(Vgini-yz) equation 5

Vyz wherein: during the cycle of setting up (SU), be added to scan electrode (Y) and keep the external voltage (hereinafter, being called external voltage between Y-Z) of electrode (Z)." Vyz " is illustrated in the drive waveforms of Figure 11 and 13, be added to scan electrode positive tilt waveform (PRY1, PRY2) voltage and be added to the 0V of scan electrode Z.

As equation 5 and shown in Figure 16, if external voltage between Y-Z (Vyz) then produces dark discharge because wide driving surplus is stablized fully being increased to during the cycle of setting up (SU) greater than in the voltage difference between the primary clearance voltage (Vgini-yz) between trigger voltage (Vf) and Y-Z in discharge cell.

In the plasma display panel device according to third embodiment of the invention, the luminous quantity that produces during the reset cycle in each son field is very little compared to existing technology.This is the discharge time of carrying out in the unit because of during reset cycle of each son field, and specifically, the surface-discharge number of times is less than the discharge time of prior art.

In table 2, the discharge time of having arranged electric discharge type and having carried out in first sub pre-reset cycle (PRERP) of in the drive waveforms of Figure 11, describing and reset cycle (RP).In table 3, the discharge time of having arranged electric discharge type and having carried out in the reset cycle (RP) of each residue son that does not have the pre-reset cycle (PRERP) of in the drive waveforms of Figure 13, describing.

Table 2:

Table 3:

As shown in table 2, in the drive waveforms of first son of Figure 11, during pre-reset cycle (PRERP) and reset cycle (RP), carry out three opposite discharges and maximum is arrived in twice surface-discharge.In its ensuing son field, as shown in table 3, during the reset cycle (RP), carry out once opposite discharge and twice surface-discharge to maximum, and only carry out once discharge on the contrary in the closing unit that formerly end the son field.In plasma display panel device according to third embodiment of the invention, when being divided into 12 son fields a frame period, plasma display panel device compared to existing technology is because the difference of discharge time and electric discharge type reduces to 1/3rd or littler with black image brightness.Therefore, plasma display panel device of the present invention can show the black image with darkroom contrast value lower than prior art, and therefore can more clearly illustrate image.

Discharge time in the less situation, means that the wall electric charge changes or reversing is littler in discharge cell in the reset cycle (RP) therein.For example, as shown in figure 17, in the plasma display panel device of prior art, from after n-1 (SFn-1) last kept discharge after the dark discharge of removing the cycle (SD) of n field (SFn), the wall charge polarity of keeping electrode (Z) changes in proper order, from positive polarity, wipe and negative polarity (Fig. 4 A), positive polarity (Fig. 4 B) and negative polarity (Fig. 4 C).Compare these, as shown in figure 18, in plasma display panel device of the present invention, after the dark discharge of removing the cycle (SD) of n (SFn), the wall electric charge of keeping electrode (Z) is maintained has negative polarity after last the keeping of n-1 (SFn-1) discharged.In other words, shown in Figure 12 A, 12B and 14, in plasma display panel device of the present invention, when the wall electric charge of keeping addressing electrode (X) in initialization process consistently has negative polarity, addressing period (AP) beginning.

Figure 19 shows in the drive waveforms according to the first sub-field duration in the driving method of the plasma display panel device of fourth embodiment of the invention, and Figure 20 shows in the drive waveforms according to the sub-field duration outside the first sub-field duration in the driving method of the plasma display panel device of fourth embodiment of the invention.Here, " n " represents the positive integer more than or equal to 2.

With reference to Figure 19 and 20, in the driving method of plasma display panel device of the present invention, in each son field, during the cycle of removing (SD), will be applied to scan electrode (Y), to be adjusted at the wall CHARGE DISTRIBUTION of the cycle of foundation (SU) initialized whole discharge cell from the voltage of 0V or ground voltage (GND) decline.

First sub comprises pre-reset cycle (PRERP), reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 19.Other son (SFn) comprises reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 20.

For space charge is changed into thereby the wall electric charge is wiped space charge and in the pre-reset cycle (PRERP) of first son in the wall CHARGE DISTRIBUTION that forms in each discharge cell shown in Figure 12 A, from keeping electrode (Z) to all and pass through the schedule time (Td2) afterwards using the positive voltage (Vs) of keeping, (tilt waveform (NRY1) that Y V1) bears is applied to all scan electrodes (Y) will to drop to negative voltage from 0V or ground voltage (GND).

Being added to keep electrode (Z) last before in the reset cycle (RP) except n of first son keeps pulse (LSTSUSP3) and keeps the positive voltage (Vs) of keeping during the space charge damped cycle (Tdecay3) of 500 μ s at about 200 μ s.During space charge damped cycle (Tdecay3), space charge is changed to the wall electric charge and is wiped free of.During the removing the cycle of reset cycle (RP) of each son (SFn-1 and SFn) (SD), the tilt waveform (NRY2) that the 2nd Y is negative is added to scan electrode and simultaneously, the tilt waveform (NRZ2) that the 2nd Z is negative is added to keeps electrode (Z).The negative tilt waveform (NRY2) of the 2nd Y drops to negative voltage (V2), and unlike the foregoing description from 0V or ground voltage (GND).The negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage from the positive voltage (Vs) of keeping.During the cycle of removing (SD), scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.By dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).Simultaneously, can omit the negative tilt waveform (NRZ2) of the 2nd Z.

If the negative tilt waveform (NRY2) of the 2nd Y descends from 0V or ground voltage, compare the foregoing description and shortened the cycle of removing (SD).In addition, even the negative tilt waveform (NRY2) of the 2nd Y descends from 0V or ground voltage, littler at scan electrode (Y) and the voltage difference kept between the electrode (Z).Therefore, plasma display panel device of the present invention can more effectively be suppressed at scan electrode (Y) and keep discharge between the electrode (Z), more stably carries out initialization simultaneously.Therefore, at present embodiment,, can guarantee the initialization operation during (SD) removed the cycle in driving time and execution more stably more because reduced the cycle of removing (SD).

In order to reduce the space charge amount that in keeping discharge, produces, each is kept pulse (FIRSTSUSP, SUSP, LSTSUSP) extend to have rising cycle and the decline cycle of about 340ns ± 20ns relatively.

Figure 21 shows the drive waveforms according to the driving method of the plasma display panel device of fifth embodiment of the invention.This drive waveforms is applied to hot environment.

With reference to Figure 21, in the driving method of plasma display panel device of the present invention, at the final cycle of n-1 (SFn-1), will keep positive keep voltage last during the space charge damped cycle (Tdecay3) of 500 μ s at about 200 μ s and keep pulse (LSTSUSP) and be added to and keep electrode (Z).Afterwards, 0V or ground voltage (GND) are added to keep electrode (Z).

In the driving method of plasma display panel device of the present invention, the positive voltage (Vs) of keeping is applied to all and keeps electrode (Z).Afterwards, from through the schedule time (T2), (tilt waveform (NRY1) that Y V1) bears is applied to all scan electrodes (Y) will to drop to negative voltage from 0V or ground voltage (GND).Therefore, be maintained to when keeping voltage (Vs) when keeping electrode (Z), the tilt waveform (NRY1) that a Y is negative is applied to scan electrode (Y).Afterwards, in the driving method of plasma display panel device of the present invention, 0V or ground voltage (GND) are applied to scan electrode (Y).Afterwards, will be added to and keep electrode from keeping the negative tilt waveform (NRZ1) of a Z that voltage (Vs) drops to 0V or ground voltage (GND) gradually.

In order to reduce the space charge amount that in keeping discharge, produces, comparatively prolong each and keep pulse (FIRSTSUSP, SUSP, LSTSUSP) to have rising cycle and the decline cycle of about 340ns ± 20ns.

The space charge that is produced by a series of drive waveforms in hot environment almost is wiped free of or changes into the wall electric charge before at n (SFn).Each discharge cell of initialization owing to the wall CHARGE DISTRIBUTION of Figure 12 A.

Figure 22 is the block diagram according to the plasma display panel device of the embodiment of the invention.

With reference to Figure 22, plasma display panel device of the present invention comprises Plasmia indicating panel (PDP) 200; Be used to respond to the temperature sensor 206 of the temperature of PDP 200; Be used to provide data to the data-driven unit 202 of the addressing electrode (X1-Xm) of PDP200; Be used to drive the scan drive cell 203 of the scan electrode (Y1-Yn) of PDP 200; Be used to drive PDP 200 keep electrode (Z) keep driver element 204; Be used for controlling the time schedule controller 201 of each driver element 202,203 and 204 according to the temperature of PDP 200; Driving voltage generator 205 with the driving voltage that is used to produce each driver element 202,203 and 204 needs.

Temperature sensor 206 is responded to the temperature of PDP with the generation induced voltage, and induced voltage is converted to digital signal to provide this digital signal to time schedule controller 201.

After data are carried out reverse gamma-corrected and error diffusion by reverse gamma-corrected circuit (not shown) and error diffusion circuit (not shown), by son mapping circuit with this data map to predetermined sub-field mode, and offer data-driven unit 202.Shown in Fig. 9,10,11,13,19,20 and 21, data-driven unit 202 is in pre-reset cycle (PRERP), reset cycle (RP) and keep the cycle (SP) and provide 0V or ground voltage to addressing electrode (X1-Xm).Under the control of time schedule controller 201, after sampling and the latch data, data-driven unit 202 offers addressing electrode (X1-Xm) with data during the addressing period (AP) of each son field in data-driven unit 202.

Shown in Fig. 7,8,9,11,17,18 and 19, scan drive cell 203 provides tilt waveform (NRY1, PRY1, PRY2, NRY2) to scan electrode (Y1 is to Yn), thereby under the control of time schedule controller 201, at pre-reset cycle (PRERP) and the whole discharge cell of reset cycle (RP) initialization.Afterwards, scan drive cell 203 provides scanning impulse (SCNP) to scan electrode (Y1-Yn) sequentially, thereby is chosen in the sweep trace that data are provided during the addressing period (AP).When PDP has high temperature, what scan drive cell 203 provided rising cycle with about 340ns ± 20ns and decline cycle keeps pulse (FSTSUSP and SUSP) to scan electrode (Y1-Yn), thus in the cycle of keeping (SP) selected open to produce in the unit keep discharge.

Shown in Fig. 8,10,16 to 22, keeping driver element 204 provides tilt waveform (NRZ1 and NRZ2) to keeping electrode (Z) under the control of time schedule controller 201, thereby at pre-reset cycle (PRERP) and the whole discharge cell of reset cycle (RP) initialization.Then, keeping driver element 204 provides Z bias voltage (Vzb) to keeping electrode (Z) in addressing period (AP).At the cycle of keeping (SP), keep driver element 204 and scan drive cell 203 alternations and keep pulse (FSTSUSP, SUSP, LSTSUSP) to keeping electrode (Z) to provide.When PDP has high temperature, increase what keep that driver element 204 produces and last keep pulse (LSTSUSP) to have the pulse width of 200 μ s-500 μ s.Each is kept pulse (FSTSUSP, SUSP, LSTSUSP) and has rising cycle and the decline cycle of about 340ns ± 20ns.

Time schedule controller 201 reception vertical/horizontal synchronizing signals and clock signal are to produce each driver element 202,203 and 204 timing control signals (CTRX, CTRY, CTRZ) that need.Time schedule controller 201 provide timing control signal (CTRX, CTRY, CTRZ) to the corresponding driving unit 202,203 and 204 to control each driver element 202,203 and 204.The timing control signal (CTRX) that is provided to data-driven unit 202 comprises sampling clock, latch control signal that is used for sampled data and the switch controlling signal that is used for the connection/shut-in time of control energy recovery circuit and driving switch element.The timing control signal (CTRY) that offers scan drive cell 203 comprises the switch controlling signal of the connection/shut-in time of the energy recovering circuit that is used for gated sweep driver element 203 and driving switch element.Offer the switch controlling signal that the timing control signal (CTRZ) of keeping driver element 204 comprises the connection/shut-in time that is used to control the energy recovering circuit of keeping driver element 204 and driving switch element.

When PDP 200 has high temperature, time schedule controller 201 receives output voltages with gated sweep driver element 203 with keep driver element 204 from temperature sensor 206, prolong the degree of the last pulse width of keeping pulse (LSTSUSP) thus to 200 μ s-500 μ s, and gated sweep driver element 203 and keep driver element 204 and have rising cycle and the decline cycle of about 340ns ± 20ns to allow each to keep pulse (FSTSUSP, SUSP, LSTSUSP).In addition, time schedule controller 201 gated sweep driver elements 203 and keep driver element 204 and keep voltage (Vs) to keeping electrode (Z) to provide positive before at the negative tilt waveform (NRY1) of a Y.

Driving voltage generating unit 205 produces the driving voltage that offers PDP 200, just, voltage (Vry, Vs ,-V1 ,-V2 ,-Vy, Va, Vyb, Vzb), as Fig. 8,10 and 16-22 shown in.This driving voltage can change according to the composition of discharge characteristic or discharge gas, and these are different and different according to the resolution of PDP 200 and model.

As mentioned above, describe plasma display panel device of the present invention and driving method thereof in detail for the purpose of stablizing the discharge in the hot environment.

Hereinafter, will describe plasma display panel device and driving method thereof in detail for another advantage of the influence of the wall electric charge of minimizing subtegulum in keeping discharge.

Figure 23 and 24 shows according to sixth embodiment of the invention, during the first sub-field duration of the driving method of plasma display panel device, is provided to the drive waveforms of the PDP of Fig. 2.The drive waveforms of Figure 23 and 24 is described to the wall CHARGE DISTRIBUTION of 25F below with reference to Figure 25 A.

With reference to Figure 23 and 24, in the driving method of plasma display panel device of the present invention, the first son field comprises pre-reset cycle (PRERP), reset cycle (RP), addressing period (AP) and keeps the cycle (SP).During the pre-reset cycle (PRERP), positive wall electric charge is gone up at scan electrode (Y) and is formed and negative wall electric charge is gone up and formed keeping electrode (Z).During the reset cycle (RP), use forms the wall CHARGE DISTRIBUTION and comes the discharge cell of initialization entire image during the pre-reset cycle (PRERP).During addressing period (AP), select discharge cell.During the cycle of keeping (SP), keep the discharge of selected discharge cell.

In the pre-reset cycle (PRERP), to keep Z anacline waveform (PRZ) that voltage (Vs) rises to positive Z resetting voltage (Vrz) and be added to all and keep electrode (Z) from positive, and (the negative tilt waveform (NRY1) of Y V1) be added to all scan electrodes (Y) will to drop to negative voltage from 0V or ground voltage (GND).When the voltage of keeping electrode (Z) formed (PRZ) rising by positive tilt waveform, the voltage of scan electrode (Y) was risen by the negative tilt waveform (NRY1) of a Y, and afterwards, keeps this voltage (V1) schedule time.During the pre-reset cycle (PRERP), 0V is added to addressing electrode (X).The negative tilt waveform (NRY1) of this a Z anacline waveform (PRZ) and a Y whole discharge cell be created in scan electrode (Y) and keep between the electrode (Z) and keeping electrode (Z) and addressing electrode (X) between dark discharge.As the result of discharge, the pre-reset cycle (PRERP) afterwards, shown in Figure 25 A, in whole discharge cell, positive wall electric charge is gone up accumulation at scan electrode (Y), and a large amount of negative wall electric charge is gone up accumulation keeping electrode (Z).In addition, positive wall electric charge is gone up accumulation at addressing electrode (X).Utilize the wall CHARGE DISTRIBUTION of Figure 25 A, in the internal discharge gas space of whole discharge cell, at scan electrode (Y) with keep the enough big positive gap voltage of formation between the electrode (Z), and in each discharge cell, form electric field towards keeping electrode (Z) from scan electrode (Y).

At set up the cycle (SU) of reset cycle (RP), the positive tilt waveform form (PRY2) of tilt waveform form (PRY1) that a Y is positive and the 2nd Y is applied to all scan electrodes (Y) continuously, and 0V is added to keeps electrode (Z) and addressing electrode (X).The positive tilt waveform (PRY1) of the one Y rises to the positive voltage (Vs) of keeping from 0V, and the positive tilt waveform (PRY2) of the 2nd Y rises to and is higher than the positive positive Y resetting voltage (Vry) of keeping voltage (Vs) from the positive voltage (Vs) of keeping.Positive Y resetting voltage (Vry) is less than positive Z resetting voltage (Vrz).Positive Y resetting voltage (Vry) is defined as at positive Z resetting voltage (Vrz) and the positive voltage of keeping between the voltage (Vs).The positive tilt waveform (PRY2) of the 2nd Y has the slope less than the positive tilt waveform of a Y (PRY1).The positive tilt waveform (PRY2) of tilt waveform (PRY1) that the one Y is positive and the 2nd Y can also be set to have same slope.With in discharge cell at scan electrode (Y) with when keeping between the electrode (Z) the positive tilt waveform (PRY1) of the voltage that forms electric field and a Y and suing for peace, in whole discharge cell at scan electrode (Y) with keep between the electrode (Z) and between scan electrode (Y) and addressing electrode (X) and produce dark discharge.Result as discharge, in whole discharge cell, the cycle of setting up (SU) afterwards, shown in Figure 25 B, negative wall electric charge is accumulated in scan electrode (Y) goes up with polarity to negative inversion scanning electrode (Y), and the accumulation more on addressing electrode (X) of positive wall electric charge.In addition, keeping negative wall electric charge that electrode (Z) goes up accumulation directly facing to scan electrode (Y), and on amount, reducing slightly, but their negative polarity is kept.

Simultaneously, the cycle of removing (SD) produces before the dark discharge by the wall CHARGE DISTRIBUTION afterwards in the pre-reset cycle (PRERP), and gap voltage positive in whole discharge cell is enough big.Therefore, Y resetting voltage (Vr) can be lower than the resetting voltage (Vr) of Fig. 3 of prior art.Use therein in the experimental result of wall CHARGE DISTRIBUTION all discharge cells of initialization before setting up discharge shown in Figure 25 A, confirm in all discharge cells to keep voltage (Vs) and produce and set up discharge being equal to or less than.Therefore, in the drive waveforms of Figure 23 and 24, may not need the positive tilt waveform of the 2nd Y (PRY2).Keep voltage (Vs) even the voltage that is added to scan electrode (Y) in the cycle of setting up (SU) is only risen to by the positive tilt waveform of a Y (PRY1), then in all discharge cells, can stably produce and set up discharge.

In the pre-reset cycle (PRERP) with during setting up the cycle (SU), positive wall electric charge is gone up fully accumulation at addressing electrode (X).Therefore, the absolute value of the applied external voltage that address discharge needs, just, the absolute value of data voltage and scanning voltage is lowered.

At remove the cycle (SD) of reset cycle (RP) afterwards in the cycle of setting up (SU), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y), and simultaneously, the tilt waveform (NRZ2) that the 2nd Z is negative is applied to keeps electrode (Z).The negative tilt waveform of the 2nd Y forms (NRY2) and drops to negative voltage (V2) from the positive voltage (Vs) of keeping.And the negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage from keeping voltage (Vs).Can be provided with voltage (V2) and voltage (V1) identical or different.During the cycle of removing (SD), scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.By dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).As a result, shown in Figure 25 C, whole discharge cell has uniform wall electric charge and distributes.In the wall CHARGE DISTRIBUTION of Figure 25 C, upward fully upward fully accumulate at addressing electrode (X) by accumulation and positive wall electric charge at scan electrode (Y) for negative wall electric charge.Therefore, the gap voltage between scan electrode (Y) and addressing electrode (X) rises near trigger voltage (Vf).Therefore, the cycle of removing (SD) afterwards, the wall CHARGE DISTRIBUTION of whole discharge cell is adjusted to optimum addressed state.

At addressing period (AP), negative scanning impulse (SCNP) is applied to scan electrode (Y) sequentially, and simultaneously, (SCNP) synchronous positive data pulse (DP) is applied to addressing electrode (X) with scanning impulse.(voltage SCNP) is scanning voltage (Vsc) to this scanning impulse, and it drops to negative scanning voltage (Vy) from 0V or near its negative scan bias voltage (Vyb).And the voltage of data pulse (DP) is positive data voltage (Va).During addressing period (AP), will be lower than the positive positive Z bias voltage (Vzb) of keeping voltage (Vs) and be applied to and keep electrode (Z).Therein the reset cycle (RP) afterwards, whole discharge cell is adjusted in the state of gap voltage of optimum addressing condition, have the opening in the unit of the scanning voltage (Vsc) that is applied to it and data voltage (Va), the gap voltage between scan electrode (Y) and addressing electrode (X) surpasses trigger voltage (Vf).If like this, only between electrode (Y and X), produce address discharge.The wall CHARGE DISTRIBUTION of opening the unit that wherein produces address discharge is shown in Figure 25 D.After producing address discharge, the wall CHARGE DISTRIBUTION of opening the unit is changed, and shown in Figure 25 E, go up accumulation because address discharge causes positive wall electric charge at scan electrode (Y), and negative wall electric charge is gone up accumulation at addressing electrode (X).

Only produce address discharge between scan electrode (Y) and addressing electrode (X), shown in Figure 25 D, and therefore, the time that address discharge needs shortens greatly.

Simultaneously, therein 0V or ground voltage are applied to addressing electrode (X) or wherein 0V or scan bias voltage (Vyb) are applied in the closing unit of scan electrode (Y), gap voltage is less than trigger voltage.Therefore, do not produce therein in the closing unit of address discharge, the wall CHARGE DISTRIBUTION is kept basically shown in Figure 25 C.

At the initial time point in the cycle of keeping (SP), ground voltage (GND) or 0V are added to scan electrode (Y).Simultaneously, the positive pulse (PRESUSP) of keeping in advance of keeping voltage (Vs) is applied to and keeps electrode (Z), and ground voltage (GND) or 0V are applied to addressing electrode (X).In other words, at the initial time point in the cycle of keeping (SP), the voltage of scan electrode (Y) rises to ground voltage (GND) or 0V from negative scan bias voltage (Vyb).Simultaneously, the voltage of keeping electrode (Z) rises to the positive voltage (Vs) of keeping from positive Z bias voltage (Vzb).Be applied to when keeping electrode (Z) when keeping pulse (PRESUSP) in advance, by the wall CHARGE DISTRIBUTION in the discharge cell, at scan electrode (Y) with keep gap voltage between the electrode (Z) less than trigger voltage.Therefore, offer when keeping electrode (Z), in opening the unit, do not produce discharge when keeping pulse (PRESUSP) in advance.

Keeping pulse (PRESUSP) in advance afterwards, keeping pulse (FSTSUSP) with first and be applied to scan electrode, and ground voltage (GND) and 0V are being applied to keep electrode (Z) simultaneously.In other words, during the voltage of scan electrode (Y) changed to the positive period 1 of keeping voltage (Vs) (t1) from ground voltage (GND) or 0V, the voltage of keeping electrode (Z) changed to ground voltage (GND) or 0V from the positive voltage (Vs) of keeping.Therefore, keep in the state of 0V with the voltage that will keep electrode (Z), keep the prior art that voltage (Vs) is applied to scan electrode (Y) and compare positive, the present invention can be elevated to the voltage of scan electrode (Y) the positive voltage (Vs) of keeping, and simultaneously, the voltage that to keep electrode (Z) drops to ground voltage (GND) or 0V, is increased in scan electrode (Y) thus more and keeps gap voltage between the electrode (Z).Therefore, when keeping pulse (FSTSUSP) by first and produce when keeping discharge opening the unit, because the wall CHARGE DISTRIBUTION of Figure 10 E, shown in Figure 25 F, mainly open the scan electrode (Y) in the unit and keep between the electrode (Z) generation and keep discharge, and the wall electric charge of subtegulum is almost without any influence selected.First keep pulse (FSTSUSP) and drop to the cycle (t2) of ground voltage (GND) or 0V during, utilize first to keep pulse (FSTSUSP), the voltage of keeping electrode (Z) rises to the positive voltage (Vs) of keeping from ground voltage (GND) or 0V.Keep pulse (FSTSUSP) afterwards first, the scanning impulse (SUSP, LSTSUSP) that alternately is provided to scan electrode (Y) and keeps electrode (Z) does not overlap each other.

During the reset cycle (RP), 0V or ground voltage are provided to addressing electrode (X).The pulse (FSTSUSP) of keeping that at first is applied to each scan electrode (Y) and keeps electrode (Z) is set to have than normally keeping the bigger pulse width of pulse (SUSP), thereby stably discharge is kept in initialization.Keep pulse (LSTSUSP) and be applied to and keep electrode (Z) last.In the original state of the cycle of setting up (SU), the last pulse (LSTSUSP) of keeping is set to have than normally keeping the wideer pulse width of pulse (SUSP), to keep the upward negative wall electric charge of punishment accumulation of electrode (Z).In opening the unit, keep pulse (FSTSUSP, SUSP, LSTSUSP) at scan electrode (Y) with keep between the electrode (Z) and to carry out discharge at each.Relative, in closing unit, keep the cycle the identical of the initial wall CHARGE DISTRIBUTION of (SP) and Figure 25 C.Therefore, keep pulse (FSTSUSP, SUSP, LSTSUSP) even apply, gap voltage is maintained the low-voltage that is lower than trigger voltage (Vf), does not produce discharge thus.

Figure 23 and 24 drive waveforms are not limited only to first son, but can be applicable to comprise first son and several initial son, and also can be applicable to be included in the whole son field in the frame period.

Figure 26 shows in the driving method according to the plasma display panel device of sixth embodiment of the invention, is provided to the drive waveforms of the PDP of Fig. 2 during the reset cycle (RP) of n-1 (SFn-1) and n field (SFn).Here, " n " represents the positive integer more than or equal to 2.The drive waveforms of Figure 26 will be described with reference to the wall CHARGE DISTRIBUTION of Figure 27.

With reference to Figure 26, by using the next whole discharge cell of the wall CHARGE DISTRIBUTION that after the cycle of keeping of n-1 (SFn-1), forms at n (SFn) initialization PDP.

Each of n-1 (SFn-1) and n (SFn) comprises and being used for because the reset cycle (RP) of wherein negative wall electric charge initialization whole unit keeping electrode (Z) to go up the wall CHARGE DISTRIBUTION of fully accumulating, the keeping the cycle of discharge (SP) that be used for the addressing period (AP) of selected cell and be used to keep selected unit.

Keeping in the cycle of n-1 (SFn-1), keep pulse (LSTSUSP3) and be applied to and keep electrode (Z) last.Simultaneously, 0V or ground voltage are applied to scan electrode (Y) and addressing electrode (X).Last keep pulse (LSTSUSP) in discharge cell at scan electrode (Y) with keep and produce the last discharge of keeping between the electrode (Z).As shown in figure 27, on scan electrode (Y), accumulate positive wall electric charge and go up the negative wall electric charge of accumulation keeping electrode (Z) fully.

At set up the cycle (SU) of n (SFn), the wall CHARGE DISTRIBUTION of Figure 27 is used to produce dark discharge in whole discharge cell, thus the wall CHARGE DISTRIBUTION of the whole discharge cell of initialization.Set up the cycle that (SU) operation and its are ensuing to be removed initialization, addressing and keep operation identical with the first son field of Figure 23 basically.

As mentioned above, in plasma display panel device of the present invention and driving method thereof, the cycle of setting up of next height field is last the keeping after the discharge of son formerly just, and be not used in the erase cycle of the wall electric charge between reset cycle of cycle of keeping of wiping formerly son and next son field.Keeping discharge is strong light emitting discharge.Therefore, keep discharge and can and keep electrode (Z) and go up the fully a lot of wall electric charges of accumulation at scan electrode (Y), and can stable maintenance at the positive wall electric charge on the scan electrode (Y) with keeping the polarity of the negative wall electric charge on the electrode (Z).

Figure 28 shows the last cell gap voltage status of keeping discharge or discharging and form by the pre-reset cycle (PRERP).

With reference to Figure 28, by last pulse (LSTSUP) or the waveform (NRY1, PRZ and NRZ1) of pre-reset cycle (PRERP) kept at scan electrode (Y) with keep to produce between the electrode (Z) and discharge.Therefore, the cycle of setting up (SU) before, in the unit, by forming primary clearance voltage (Vgini-yz) Y-Z from scan electrode (Y) to the electric field of keeping electrode (Z), and form primary clearance voltage (Vgini-yx) Y-X by electric field from scan electrode (Y) to addressing electrode (X).

As shown in figure 16, set up the cycle (SU) before at this, the wall CHARGE DISTRIBUTION by Figure 28 has formed primary clearance voltage (Vgini-yz) between Y-Z in discharge cell.Therefore, if, then during the cycle of setting up (SU), in discharge cell, produce dark discharge by applying external voltage in the voltage difference between the primary clearance voltage (Vgini-yz) between trigger voltage (Vf) and Y-Z.This is by top formula 5 expressions.Therefore, omitted and be repeated in this description.

As formula 6 and shown in Figure 16, if external voltage between Y-Z (Vyz) then stably produces dark discharge because of wide driving surplus fully being increased to during the cycle of setting up (SU) greater than in the voltage difference between the primary clearance voltage (Vgini-yz) between trigger voltage (Vf) and Y-Z in discharge cell.

In the plasma display panel device according to the embodiment of the invention, the luminous quantity that produces during the reset cycle in each son field is very little compared to existing technology.This is the discharge time of carrying out in the unit because of during reset cycle of each son field, and special, the surface-discharge number of times is less than prior art.

In above-mentioned table 2, arrangement be electric discharge type and in the embodiment of Figure 23, describe first the son the pre-reset cycle (PRERP) and the reset cycle (RP) in the execution discharge time.In table 3, arrangement be the discharge time of execution in reset cycle (RP) of electric discharge type and each residue son that is not having the pre-reset cycle (PRERP) of in the embodiment of Figure 26, describing.Therefore, omission is repeated in this description.

As shown in table 2, in the first son field of Figure 23, during pre-reset cycle (PRERP) and reset cycle (RP), carry out three opposite discharges and twice surface-discharge and arrive maximum.In its ensuing son field, as shown in table 3, carry out once discharge and twice surface-discharge on the contrary to maximum in the reset cycle (RP), and formerly only carry out once discharge on the contrary in the son closing unit that ends.In plasma display panel device of the present invention, when being divided into 12 son fields a frame period, plasma display panel device compared to existing technology is because the difference of discharge time and electric discharge type reduces to 1/3rd or littler with black image brightness.Therefore, plasma display panel device of the present invention can show the black image with darkroom contrast value lower than prior art, and therefore can more clearly illustrate image.

In the reset cycle (RP), in the less situation, mean that the wall electric charge changes or reversing is littler in discharge cell at discharge time.

For example, as shown in figure 17, in the plasma display panel device of prior art, from after n-1 (SFn-1) last kept discharge after the dark discharge of removing the cycle (SD) of n field (SFn), the wall charge polarity of keeping electrode (Z) is sequentially changed, from positive polarity, wipe (Fig. 4 A), positive polarity (Fig. 4 B) and negative polarity (Fig. 4 C).Compare these, as shown in figure 18, in plasma display panel device of the present invention, after the dark discharge of removing the cycle (SD) of n (SFn), the wall electric charge of keeping electrode (Z) is maintained has negative polarity after last the keeping of n-1 (SFn-1) discharged.In other words, in plasma display panel device of the present invention, when the wall electric charge of keeping addressing electrode (X) in initialization process consistently has negative polarity, shown in Figure 25 A, 25B and 25C, then begin addressing period (AP).

Figure 29 shows the oscillogram according to the driving method of the plasma display panel device of seventh embodiment of the invention.

With reference to Figure 29, in the driving method of plasma display panel device of the present invention, the tilt waveform (NRY2) that negative tilt waveform (NRZ2) ratio the 2nd Y of the 2nd Z bears is arrival point voltage (GND) quickly.

In this embodiment, pre-reset cycle (PRERP), reset cycle (RP) set up the cycle (SU), addressing period (AP) is identical with the cycle of keeping (SP) and the foregoing description, and so omits its detailed description.

Removing the cycle in (SD) of reset cycle (RP), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y), and simultaneously, the tilt waveform (NRZ2) that the 2nd Z is negative is applied to keeps electrode (Z).The negative tilt waveform (NRY2) of the 2nd Y drops to negative voltage (V2) from the positive voltage (Vs) of keeping.The negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage (GND) from positive Z bias voltage (Vzb).Negative tilt waveform (NRZ2) the arrival point voltage (GND) of the 2nd Z and through schedule time poor (Δ tbottom) afterwards, tilt waveform formation (NRZ2) arrival point voltage (GND) that the 2nd Z is negative.Keeping the negative tilt waveform (NRZ2) of the 2nd Z in the process of ground voltage (GND), if tilt waveform (NRY2) the arrival point voltage (GND) that the 2nd Y is negative is because scan electrode (Y) and the coupling of keeping electrode (Z) can prevent that the change in voltage of scan electrode (Y) is to keep negative voltage consistently (V2).Therefore, there is the stable advantage that guarantees to drive surplus.During the cycle of removing (SD), between scan electrode (Y) and addressing electrode (X), produce dark discharge.By dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).As a result, whole discharge cell has the uniform wall electric charge distribution under optimum addressing condition.

Figure 30 shows the oscillogram according to the driving method that is used for plasma display panel device of eighth embodiment of the invention.

With reference to Figure 30, in the driving method of plasma display panel device of the present invention, during the pre-reset cycle (PRERP), only tilt waveform is applied to and keeps electrode (Z).

In this embodiment, reset cycle (RP), addressing period (AP) and keep the cycle (SP) and the 7th embodiment basic identical, and therefore omit its detailed description.

At reset cycle (PRERP), will keep the positive tilt waveform (PRZ) of Z that voltage (Vs) rises to positive Z resetting voltage (Vrz) and be applied to all and keep electrode (Z) from positive.During the pre-reset cycle (PRERP), OV or ground voltage (GND) are applied to scan electrode (Y) and addressing electrode (X).This Z anacline waveform (PRZ) in whole discharge cell scan electrode (Y) and keep electrode (Z) and keeping electrode (Z) and addressing electrode (X) between produce dark discharge.As the result of this discharge, the pre-reset cycle (PRERP) afterwards, in whole discharge cell, positive wall electric charge is gone up accumulation at scan electrode (Y), and a large amount of negative wall electric charge is gone up accumulation keeping electrode (Z).Positive wall electric charge is gone up accumulation at addressing electrode (X).Discharge and effect thereof on the pre-reset cycle (PRERP) are similar to above-mentioned the 6th embodiment's.Therefore, compare the 7th embodiment, the advantage that this embodiment has is not only to provide the discharge effect of pre-reset cycle (PRERP), and scan electrode driving circuit be easier to control keep electrode (Z) because only tilt waveform is applied to.

Figure 31 shows the oscillogram according to the driving method of the plasma display panel device of ninth embodiment of the invention.

With reference to Figure 31, in the driving method of plasma display panel device, during the pre-reset cycle (PRERP), only tilt waveform is applied to scan electrode (Y).

In this embodiment, reset cycle (RP), addressing period (AP) and keep the cycle embodiment basic identical of (SP) and Figure 23, and therefore omit its detailed description.

In the pre-reset cycle (PRERP), (the negative tilt waveform (NRY1) of Y V1) is applied to all scan electrodes (Y) will to drop to negative voltage from 0V or ground voltage (GND).During the pre-reset cycle (PRERP), 0V or ground voltage (GND) be applied to keep electrode (Z) and addressing electrode (X).The negative tilt waveform (NRY1) of this Y in whole discharge cell scan electrode (Y) and keep between the electrode (Z) and keeping electrode (Z) and addressing electrode (X) between produce dark discharge.As the result of this discharge, the pre-reset cycle (PRERP) afterwards, in whole discharge cell, positive wall electric charge is gone up accumulation at scan electrode (Y), and negative wall electric charge is gone up accumulation keeping electrode (Z).Positive wall electric charge is gone up accumulation at addressing electrode (X).At the discharge of pre-reset cycle (PRERP) and embodiment that effect is similar to above-mentioned Figure 23 thereof.Therefore, compare the embodiment of Figure 23, the advantage that this embodiment has is not only to provide the discharge effect of pre-reset cycle (PRERP), and keeps electrode drive circuit and be easier to Be Controlled, because only tilt waveform is applied to scan electrode (Y).

In the mode identical with the embodiment of Figure 23, Figure 30 and 31 drive waveforms are not limited only to first son, and can be applicable to comprise the several initial son of first son, and can be applicable to the whole son that comprises in a frame period.

Figure 32 shows the drive waveforms according to the first sub-field duration in the driving method of the plasma display panel device of tenth embodiment of the invention.Figure 33 shows in the driving method according to the plasma display panel device of tenth embodiment of the invention, the drive waveforms during the keeping the cycle of n-1 (SFn-1) and n field (SFn) (SP).

With reference to Figure 32 and 33, in the driving method of plasma display panel device of the present invention, each son remove the cycle (SD) during, the voltage that descends from 0V or ground voltage (GND) is applied to scan electrode (Y) to be adjusted at the wall CHARGE DISTRIBUTION of the cycle of foundation (SU) initialized whole discharge cell.

First son comprises the pre-reset cycle (PRERP), the reset cycle (RP), and addressing period (AP) and keep the cycle (SP), shown in figure 32.Other son (SFn) comprises reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 33.

Pre-reset cycle (PRERP), work identical with the foregoing description basically of setting up the cycle (SU), addressing period (AP) and the cycle of keeping (SP).

At remove the cycle (SD) of reset cycle (RP) of each son (SFn-1 and SFn), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y), and simultaneously that the 2nd Z is negative tilt waveform forms (NRZ2) and is applied to and keeps electrode (Z).The negative tilt waveform of the 2nd Y forms (NRY2) and drops to negative voltage from 0V or ground voltage (GND) and (V2), be different from the foregoing description.The negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage from the positive voltage (Vs) of keeping.During the cycle of removing (SD), scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.By dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).

If the negative tilt waveform (NRY2) of the 2nd Y descends from 0V or ground voltage, compare the foregoing description and shortened the cycle of removing (SD).In addition, descend from 0V or ground voltage, reduce at scan electrode (Y) and the voltage difference kept between the electrode (Z) even the negative tilt waveform of the 2nd Y forms (NRY2).Therefore, plasma display panel device of the present invention can more effectively be suppressed at scan electrode (Y) and keep discharge between the electrode (Z), and more stably carries out initialization.Therefore, in this embodiment, can guarantee driving time, and more stably carry out the initialization operation of removing the cycle (SD) because remove the cycle minimizing of (SD).

Figure 34 shows the drive waveforms according to of first in the driving method of the plasma display panel device of eleventh embodiment of the invention field.Figure 35 shows in the driving method according to the plasma display panel device of eleventh embodiment of the invention, the drive waveforms during the keeping the cycle of n-1 (SFn-1) and n field (SFn) (SP).

With reference to Figure 34 and 35, in the driving method of plasma display panel device of the present invention, to be applied to scan electrode (Y) from the voltage of 0V or ground voltage (GND) decline, and in each son field, during the cycle of removing (SD), the voltage of keeping electrode (Z) is maintained at 0V or ground voltage (GND), to be adjusted at the wall CHARGE DISTRIBUTION of the cycle of foundation (SU) initialized whole discharge cell.

First sub comprises pre-reset cycle (PRERP), reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 34.Other son (SFn) comprises reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 23.

Pre-reset cycle (PRERP), operation identical with Figure 32 and 33 embodiment basically of setting up the cycle (SU), addressing period (AP) and the cycle of keeping (SP).

At remove the cycle (SD) of reset cycle (RP) of each son (SFn-1 and SFn), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y).During the cycle of removing (SD), 0V or ground voltage (GND) be applied to keep electrode (Z) and addressing electrode (X).The negative tilt waveform (NRY2) of the 2nd Y drops to negative voltage (V2) from 0V or ground voltage (GND).During the cycle of removing (SD), scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.By this dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).

If the negative tilt waveform (NRY2) of the 2nd Y descends from 0V or ground voltage, compare the foregoing description and remove the cycle (SD) and be shortened.In addition, even the negative tilt waveform (NRY2) of the 2nd Y descends from 0V or ground voltage, reduce at scan electrode (Y) and the voltage difference kept between the electrode (Z).Therefore, plasma display panel device of the present invention can more effectively be suppressed at scan electrode (Y) and keep discharge between the electrode (Z), more stably carries out initialization simultaneously.In addition, compare the embodiment of Figure 32 and 33, the advantage of this embodiment is to keep electrode drive circuit and is easier to control, because only tilt waveform is applied to scan electrode (Y) during the cycle of removing (SD).Therefore, in this embodiment, can guarantee driving time, and more stably carry out the initialization operation of removing the cycle (SD) because remove the cycle minimizing of (SD).

Figure 36 shows the drive waveforms according to of first in the driving method of the plasma display panel device of twelveth embodiment of the invention field.Figure 37 shows in the driving method according to the plasma display panel device of twelveth embodiment of the invention, the drive waveforms during the keeping the cycle of n-1 (SFn-1) and n field (SFn) (SP).

With reference to Figure 36 and 37, in the driving method of plasma display panel device of the present invention, each son remove the cycle (SD) during, positive bias voltage is applied to addressing electrode (X)

First sub comprises pre-reset cycle (PRERP), reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 36.Other son (SFn) comprises reset cycle (RP), addressing period (AP) and keeps the cycle (SP), as shown in figure 37.

Pre-reset cycle (PRERP), operation identical with the embodiment of Figure 23 basically of setting up the cycle (SU), addressing period (AP) and the cycle of keeping (SP).

At remove the cycle (SD) of reset cycle (RP) of each son (SFn-1 and SFn), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y), and simultaneously, the tilt waveform (NRZ2) that the 2nd Z is negative is applied to keeps electrode (Z).The negative tilt waveform (NRY2) of the 2nd Y drops to negative voltage (V2) from the positive voltage (Vs) of keeping.The negative tilt waveform (NRY2) of the 2nd Y can also descend from 0V or ground voltage, as the embodiment of Figure 32 to 35.The negative tilt waveform (NRZ2) of the 2nd Z drops to 0V or ground voltage from the positive voltage (Vs) of keeping.During the cycle of removing (SD), positive bias voltage is offered addressing electrode (X).For example, the voltage identical with data voltage (Va) is provided to addressing electrode (X), as positive bias voltage.Scan electrode (Y) and the voltage of keeping electrode (Z) descend simultaneously.Therefore, at scan electrode (Y) with keep between the electrode (Z) and do not produce discharge, yet between scan electrode (Y) and addressing electrode (X), produce dark discharge.The positive bias of addressing electrode (X) is increased in voltage difference between addressing electrode (X) and the scan electrode (Y) producing dark discharge quickly during erase cycle (EP), and prolongs the time of dark discharge.Therefore, even, in whole discharge cell, carry out dark discharge once, strengthen the homogeneity of whole discharge cell mesospore CHARGE DISTRIBUTION thus more when in each discharge cell, seriously causing the flash-over characteristic skew.

Figure 32,34 and 36 drive waveforms are not limited only to first son, and can be applicable to comprise the several initial son of first son, and also can be applicable to the whole son that comprises in a frame period.

Figure 38 shows the oscillogram according to the driving method of the plasma display panel device of thriteenth embodiment of the invention.

With reference to Figure 38, in the driving method of plasma display panel device of the present invention, the voltage that will keep electrode (Z) during the reset cycle (RP) maintains ground voltage.

In this embodiment, the setting up the cycle (SU), addressing period (AP) and keep the cycle the basic identical of (SP) and the foregoing description of pre-reset cycle (PRERP), reset cycle (RP), and so omit its detailed description.

During the removing the cycle of reset cycle (RP) (SD), the tilt waveform (NRY2) that the 2nd Y is negative is applied to scan electrode (Y) and ground voltage (GND) is applied to keeps electrode (Z).During the cycle of removing (SD), between scan electrode (Y) and addressing electrode (X), produce dark discharge.By this dark discharge, wipe too much negative wall electric charge from scan electrode (Y), and wipe too much positive wall electric charge from addressing electrode (X).As a result, whole discharge cell has the even wall CHARGE DISTRIBUTION under the optimum addressed state.

In this embodiment, the dark discharge that only during scan electrode (Y) and addressing electrode (X) cause the cycle of removing (SD), produces.As a result, only between scan electrode (Y) and addressing electrode (X), produce address discharge by the wall CHARGE DISTRIBUTION in the discharge cell that forms in discharge by the cycle of removing (SD).Therefore, reduced the time that addressing needs.

In the pre-reset cycle (PRERP), only can be provided to and keep electrode (Z) keeping voltage (Vs), as shown in figure 39, and can not form the positive tilt waveform of Z (PRZ).

Figure 39 shows the oscillogram according to the driving method of the plasma display panel device of fourteenth embodiment of the invention.Described Figure 39 in detail, caused to omit to be repeated in this description.

In Figure 23,26 and 29 to 39, during addressing period (SD), be applied to the positive Z bias voltage (Vzb) of keeping electrode (Z) and be lower than and keep voltage (Vs) and scanning voltage (Vsc), only to be created in scan electrode (Y) and to keep address discharge between the electrode (Z).

Figure 40 shows the part of the drive waveforms that is applied to the son field except the first son field in the plasma display panel device according to fifteenth embodiment of the invention.

With reference to Figure 40, use the drive waveforms of Figure 39 to drive plasma display panel device, and the drive waveforms of use Figure 32 is at other son driving plasma display panel device in the first son field.

This embodiment does not have erasure discharge between cycle of keeping (SP) and reset cycle (RP).In each son field, the positive wall charge generation that use is accumulated on addressing electrode is removed discharge and address discharge, and wherein positive wall electric charge is accumulated in the discharge of keeping of the preceding son of priority of use field generation.In the driving method of plasma display panel device of the present invention, during the cycle of removing (SD), to keep electrode (Z) and be maintained to have ground voltage (GND) or 0V, and formerly a son wall electric charge of going up accumulation at addressing electrode (X) is used to only produce to remove between scan electrode (Y) and addressing electrode (X) discharge and address discharge.

In plasma display panel device of the present invention, (SU) fully accumulates the wall electric charge at each discharge cell before in the cycle of setting up.Therefore, resetting voltage (Vry) can descend at the son (SF2 is to SFn) except that initial son (SF1).Son (SF2 is to SFn) outside initial son (SF1) can only use and keep voltage (Vs) and produces foundation discharge and do not rise to resetting voltage (Vry) in discharge cell.

Keep in the pulse (FSTSUSP) first, it is overlapping that the cycle and being used for that is used to change the voltage of scan electrode (Y) changes cycle of the voltage of keeping electrode (Z), to strengthen at scan electrode (Y) and keep the discharge between the electrode (Z) and any influence of almost causing the wall electric charge that forms on subtegulum.

With reference to Figure 41, plasma display panel device of the present invention comprises Plasmia indicating panel (PDP) 1800, be used to provide the data-driven unit 1820 of the addressing electrode of data to PDP1800 (X1-Xm), be used to drive the scan drive cell 1830 of the scan electrode (Y1-Yn) of PDP1800, be used to drive PDP1800 keep electrode (Z) keep driver element 1840, be used to control each driver element 1820,1830 and 1840 time schedule controller 1810 and be used to produce each driver element 1820, the driving voltage generating unit 1850 of 1830 and 1840 driving voltages that need.

After data are carried out reverse gamma-corrected and error diffusion by reverse gamma-corrected circuit (not shown) and error diffusion circuit (not shown), by son mapping circuit with this data map to predetermined sub-field mode, and offer data-driven unit 1820.Shown in Figure 23,26,29-35,38-40, data-driven unit 1820 is in pre-reset cycle (PRERP), reset cycle (RP) and keep the cycle (SP) and provide 0V or ground voltage to addressing electrode (X1-Xm).Shown in Figure 36 and 37, at remove the cycle (SD) of reset cycle (RP), data-driven unit 1820 also provides the positive bias voltage (for example, data voltage (Va)) of driving voltage generating unit 185 to addressing electrode (X1-Xm).After the control down-sampling and latch data of data-driven unit 1820 at time schedule controller 1810, it offers data addressing electrode (X1-Xm) during addressing period (AP).

Shown in Figure 23,26,29-40, scan drive cell 1830 provides tilt waveform (NRY1, PRY1, PRY2, NRY2) to scan electrode (Y1-Yn), thereby under the control of time schedule controller 1810, at pre-reset cycle (PRERP) and the whole discharge cell of reset cycle (RP) initialization.Afterwards, scan drive cell 1830 provides scanning impulse (SCNP) to scan electrode (Y1-Yn) in proper order, thereby is chosen in the sweep trace that data are provided during the addressing period (AP).Scan drive cell 1830 provides keeps pulse (FSTSUSP and SUSP) to scan electrode (Y1-Yn), thus in the cycle of keeping (SP) selected open to produce in the unit keep discharge.

Shown in Figure 23,26,29-40, keeping driver element 1840 provides tilt waveform (PRZ, NRZ1 and NRZ2) to keeping electrode (Z) under the control of time schedule controller 201, thereby at pre-reset cycle (PRERP) and the whole discharge cell of reset cycle (RP) initialization.Afterwards, keeping driver element 1840 provides Z bias voltage (Vzb) to keeping electrode (Z) in addressing period (AP).At the cycle of keeping (SP), keep driver element 1840 and scan drive cell 1830 alternations and keep pulse (FSTSUSP, SUSP, LSTSUSP) to keeping electrode (Z) to provide.

Time schedule controller 1810 reception vertical/horizontal synchronizing signals and clock signal are to produce each driver element 1820,1830 and 1840 timing control signals (CTRX, CTRY, CTRZ) that need.Time schedule controller 1810 provide timing control signal (CTRX, CTRY, CTRZ) to the corresponding driving unit 1820,1830 and 1840 to control each driver element 1820,1830 and 1840.The timing control signal (CTRX) that offers data-driven unit 1820 comprises sampling clock, latch control signal that is used for sampled data and the switch controlling signal that is used for the connection/shut-in time of control energy recovery circuit and driving switch element.The timing control signal (CTRY) that offers scan drive cell 1830 comprises the switch controlling signal of the connection/shut-in time of the energy recovering circuit that is used for gated sweep driver element 1830 and driving switch element.Offer the switch controlling signal that the timing control signal (CTRZ) of keeping driver element 1840 comprises the connection/shut-in time that is used to control the energy recovering circuit of keeping driver element 1840 and driving switch element.

Driving voltage generating unit 1850 produces the driving voltage that offers PDP1800, just, as Figure 23,26 and 29-40 shown in voltage (Vry, Vrz, Vs ,-V1 ,-V2 ,-Vy, Va, Vyb, Vzb).This driving voltage can change according to discharge characteristic or discharge gas composition, and these are different and different according to the resolution of PDP1800 and model.

As mentioned above, in plasma display panel device of the present invention and driving method thereof, when PDP has high temperature, keep pulse (LSTSUSP) and be lengthened to and have the pulse width of about 200 μ s last to 500 μ s, perhaps be lengthened to rising cycle and decline cycle with about 340ns ± 20ns, perhaps will just keep voltage (Vs) before at the negative tilt waveform (NRY1) of a Y is provided to and keeps electrode (Z), to reduce the space charge amount that in keeping discharge, produces, and the attenuating space electric charge, the discharge of stablizing PDP thus.

In plasma display panel device of the present invention and driving method thereof, before the initialization of discharge cell, in discharge cell, on scan electrode, fully accumulate positive wall electric charge to prevent erroneous discharge, misplace electricity and improper discharge.The discharge time of carrying out in initialization process reduces to strengthen darkroom contrast and to widen margin of operation.In addition, the negative tilt waveform that produces in the cycle of removing can drop to 0V or ground voltage, removes the cycle with minimizing, guarantees driving time thus.In the cycle of removing, positive bias voltage is added to the time of addressing electrode with the dark discharge that produces of lengthening between scan electrode and addressing electrode, adjust the wall CHARGE DISTRIBUTION in the whole discharge cell thus.

As mentioned above, in the plasma display panel device and driving method thereof of another embodiment of the present invention, in the cycle of keeping, can be applied to second electrode, be minimized in first influence of keeping the wall electric charge on the subtegulum in the discharge thus from keeping the pre-reset cycle (PRERP) that bias voltage (Vzb) rises.

In plasma display panel device of the present invention and driving method thereof, before the initialization discharge cell, in discharge cell, can on scan electrode, fully accumulate positive wall electric charge to prevent erroneous discharge, to misplace electricity and improper discharge.The discharge time of carrying out in initialization process is reduced to strengthen darkroom contrast and to widen margin of operation.In addition, the negative tilt waveform that produces in the cycle of removing can drop to 0V or ground voltage, removes the cycle with minimizing, guarantees driving time thus.In the cycle of removing, positive bias voltage is added to the time of addressing electrode with the dark discharge that produces of lengthening between scan electrode and addressing electrode, adjust the wall CHARGE DISTRIBUTION in the whole discharge cell thus.

It should be understood by one skilled in the art that and under the situation that does not break away from the spirit and scope of the present invention, can make multiple modifications and changes.Therefore, the invention is intended to cover modifications and changes within claims and the equivalent scope thereof.

Claims

1. plasma display panel device, it comprises:

Plasmia indicating panel; With

Driver element, it is used to drive Plasmia indicating panel makes and will be divided into N son the frame period with display image, and what wherein produce during the cycle of keeping of son field last keeps the function that pulse and the time cycle between the initialize signal that produces during the reset cycle of next height field are adjusted to temperature.

2. equipment as claimed in claim 1, wherein, this plasma display panel comprises scan electrode and keeps electrode.

3. equipment as claimed in claim 2, wherein, this time cycle is applied to scan electrode.

4. equipment as claimed in claim 2, wherein, this time cycle is applied to keep electrode.

5. equipment as claimed in claim 1, wherein, this drive unit drives Plasmia indicating panel makes the time cycle be expanded the function into temperature.

6. equipment as claimed in claim 1, wherein, this time cycle is corresponding to damped cycle.

7. equipment as claimed in claim 1, wherein, this time cycle is corresponding to the end of keeping the cycle in the son field.

8. equipment as claimed in claim 1, wherein, this time cycle is corresponding to erase cycle.

9. equipment as claimed in claim 1, wherein, this time cycle is corresponding to the beginning of the reset cycle of next height field.

10. equipment as claimed in claim 1, wherein, this drive unit drives Plasmia indicating panel makes produce during the cycle of keeping of son last keep pulse and the time cycle between the initialize signal that produces during the reset cycle of next height field is 200 μ s-500 μ s basically on the duration.

11. a plasma display panel device, it comprises:

Plasmia indicating panel, it has at least two electrodes; With

Driver, it is used to drive Plasmia indicating panel, and what wherein produce during the cycle of keeping last keep pulse and is expanded function into temperature.

12. plasma display panel device as claimed in claim 11, wherein, this plasma display panel comprises scan electrode, keeps electrode and data electrode.

13. plasma display panel device as claimed in claim 12, wherein, the pulse of keeping that this is last is applied to scan electrode.

14. plasma display panel device as claimed in claim 12, wherein, this is last keeps pulse and is applied to and keeps electrode.

15. plasma display panel device as claimed in claim 11, wherein, should during the cycle of keeping, produce last keep the pulse width that pulse has 200 μ s-500 μ s.

16. plasma display panel device as claimed in claim 11 wherein, should last kept pulse and the time cycle between the initialize signal that produces during the next reset cycle and be expanded function into temperature what produce during the cycle of keeping.

17. a plasma display panel device, it comprises:

Plasmia indicating panel;

Scan electrode;

Keep electrode; And

Driver element, it is used to drive Plasmia indicating panel, make the frame period be divided into N son with display image, wherein this first son field comprise wherein be applied to scan electrode keep pulse in time and be applied to keep electrode keep keeping the cycle of pulse overlap.

18. plasma display panel device as claimed in claim 17, wherein, described drive unit drives Plasmia indicating panel, make and to keep pulse and be applied to scan electrode a plurality of, and keep pulse and be applied to and keep electrode a plurality of, and wherein be added to keeping pulse and being applied to the pulse overlap of keeping of keeping electrode of scan electrode.

19. plasma display panel device as claimed in claim 18, wherein, described drive unit drives Plasmia indicating panel, feasible each that is applied to scan electrode kept the rising edge of pulse and is applied to the negative edge of keeping pulse of keeping electrode overlapping.

20. plasma display panel device as claimed in claim 18, wherein, described drive unit drives Plasmia indicating panel, feasible each that is added to scan electrode kept the negative edge of pulse and is applied to the rising edge of keeping pulse of keeping electrode overlapping.

21. plasma display panel device as claimed in claim 17, wherein, described drive unit drives Plasmia indicating panel, feasiblely will keep pulse in advance and at first be added to and keep electrode, and keep pulse with first then and be applied to scan electrode, and it is overlapping that the negative edge and first of wherein, keeping pulse is in advance kept the rising edge of pulse.

22. plasma display panel device as claimed in claim 17, wherein, this first son field further comprises the pre-reset cycle.

23. plasma display panel device as claimed in claim 22, wherein, this first son field further comprises reset cycle and addressing period, and the wherein pre-reset cycle is before the reset cycle.

24. plasma display panel device as claimed in claim 23, wherein, described drive unit drives Plasmia indicating panel made during the pre-reset cycle, negative voltage ramp ripple was added to scan electrode and positive voltage ramp ripple is added to keep electrode.

25. plasma display panel device as claimed in claim 17, wherein, each of a plurality of son comprise wherein be applied to scan electrode keep pulse in time and be applied to keep electrode keep keeping the cycle of pulse overlap.

26. plasma display panel device as claimed in claim 17, wherein, each of this N son field comprises the pre-reset cycle.

27. a method that drives Plasmia indicating panel, described method comprises:

Each of a plurality of picture frames is divided into N son, and wherein each of N son field comprises the cycle of keeping and reset cycle at least; And

What will produce during the cycle of keeping of son last keeps the function that pulse and the time cycle between the initialize signal that produces during the reset cycle of next height field are adjusted into temperature.

28. method as claimed in claim 27, wherein, this plasma display panel comprises scan electrode and keeps electrode.

29. method as claimed in claim 28, wherein, the step of this adjustment time cycle comprises:

Adjustment is applied to the signal of scan electrode.

30. method as claimed in claim 28, wherein, the step of this adjustment time cycle comprises:

Adjustment is applied to the signal of keeping electrode.

31. method as claimed in claim 27, wherein, the step of this adjustment time cycle comprises:

To expand to the function of temperature the time cycle.

32. method as claimed in claim 27, wherein, this time cycle is corresponding to die-away time.

33. equipment as claimed in claim 27, wherein, this time cycle is corresponding to the end of keeping the cycle in the son field.

34. equipment as claimed in claim 27, wherein, this time cycle is corresponding to erase cycle.

35. equipment as claimed in claim 27, wherein, this time cycle is corresponding to the beginning of the reset cycle of next height field.

36. equipment as claimed in claim 27, wherein, the step of this adjustment time cycle comprises:

Adjusting the time cycle makes produce during the cycle of keeping of son last keep pulse and the time cycle between the initialize signal that produces during the reset cycle of next height field is 200 μ s-500 μ s basically.

37. a method that drives Plasmia indicating panel, described method comprises:

Each of a plurality of picture frames is divided into N son, and wherein each of N son field comprises the cycle of keeping at least; With

The last width of keeping pulse that produces during the cycle of keeping is expanded to the function of temperature.

38. method as claimed in claim 37, wherein, this plasma display panel comprises scan electrode and keeps electrode.

39. method as claimed in claim 38, it further comprises:

The last pulse of keeping is applied to scan electrode.

40. method as claimed in claim 38, it further comprises:

Keep pulse and be applied to and keep electrode last.

41. method as claimed in claim 37, wherein, the step of the width of keeping pulse that this expansion is last comprises:

Expand the last width of keeping pulse and make that the duration of keeping pulse is 200 μ s-500 μ s basically.

42. method as claimed in claim 37, it further comprises:

To keep the function that pulse and the time cycle between the initialize signal that produces during next reset cycle expand to temperature last.

43. a driving comprises scan electrode and the method for keeping the Plasmia indicating panel of electrode, described method comprises:

Each of a plurality of picture frames is divided into N son, and wherein each of N son field comprises the cycle of keeping at least; And

Drive Plasmia indicating panel and make during cycle of keeping of at least one height field in given picture frame, be applied to scan electrode keep pulse in time be applied to the pulse overlap of keeping of keeping electrode.

44. method as claimed in claim 43, wherein, the step of this driving Plasmia indicating panel comprises:

Drive Plasmia indicating panel and make and keep pulse and be applied to scan electrode and keep pulse and be applied to and keep electrode a plurality of with a plurality of, and wherein be applied to scan electrode keep pulse and be applied to keep electrode to keep pulse overlapping in time.

45. method as claimed in claim 44, wherein, the step of this driving Plasmia indicating panel comprises:

Drive Plasmia indicating panel make be applied to scan electrode described a plurality of keep pulse at least one rising edge and be applied to the negative edge of keeping pulse of keeping electrode and overlap.

46. method as claimed in claim 44, wherein, the step of this driving Plasmia indicating panel comprises:

Drive Plasmia indicating panel make be applied to scan electrode described a plurality of keep pulse at least one negative edge and be applied to the rising edge of keeping pulse of keeping electrode and overlap.

47. method as claimed in claim 43, wherein, the step of this driving Plasmia indicating panel comprises:

Drive Plasmia indicating panel and make that will keep pulse in advance at first is added to and keeps electrode, and keep pulse with first then and be applied to scan electrode, its wherein, it is overlapping that the negative edge and first of keeping pulse is in advance kept the rising edge of pulse.

48. method as claimed in claim 43, wherein, first son field of this N son field comprises the pre-reset cycle.

49. method as claimed in claim 48, wherein, this first son field further comprises reset cycle and addressing period, and its wherein pre-reset cycle is before the reset cycle.

50. method as claimed in claim 49, wherein, the step of this driving Plasmia indicating panel comprises:

Drive Plasmia indicating panel and make during the pre-reset cycle, negative voltage ramp waveform is applied to scan electrode, and positive voltage ramp waveform is applied to keeps electrode.

51. method as claimed in claim 43, wherein, keeping in the cycle of a plurality of N, be applied to scan electrode keep pulse in time be applied to the pulse overlap of keeping of keeping electrode.

52. method as claimed in claim 43, wherein, each of this a plurality of N field is included in the pre-reset cycle before the reset cycle.