CN1750006A - A kind of quick simulator and method based on static RAM - Google Patents
A kind of quick simulator and method based on static RAM Download PDFInfo
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- CN1750006A CN1750006A CN 200410074678 CN200410074678A CN1750006A CN 1750006 A CN1750006 A CN 1750006A CN 200410074678 CN200410074678 CN 200410074678 CN 200410074678 A CN200410074678 A CN 200410074678A CN 1750006 A CN1750006 A CN 1750006A
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Abstract
The present invention relates to the semiconductor memory technologies field, particularly a kind of quick simulator and rapid simulation method based on static RAM (SRAM).Circuit layout construction is made of the storage unit that is positioned at the place, summit and the equivalent-circuit model of other locational storage unit.The emulation mode step is as follows: step 1, find and keep to be arranged in the storage unit domain that SRAM domain summit is located; Step 2 is to the corresponding equivalent-circuit model of other locational storage unit layout extraction; Step 3 is carried out post-simulation to the whole extraction net of the circuit of this equivalence table, and place, the summit storage unit that only needs emulation to keep in the simulation process gets final product.The characteristics of this quick simulator and method are that the scope of application is very wide, not only are applicable to the SRAM design, can also be used for the reservoir designs of a lot of other types.
Description
Technical field
The present invention relates to the semiconductor memory technologies field, particularly a kind of quick simulator and rapid simulation method based on static RAM.
Background technology
Nowadays in portable equipment and field of microprocessors, static RAM (SRAM) is widely used.High-speed, the low-power consumption of SRAM and high capacity design all become the difficult problem in the chip design all the time.
Because what the design of SRAM was adopted basically is the design cycle of full customization, this has just determined its whole design implementation procedure to be unable to do without the emulation of a large amount of transistor levels.Hspice has been approved for a long time and has been obtained widespread use in industry member as the simulation software of high-precision transistor level.But also there is defective in Hsipce, is exactly that simulation velocity is slower, and this makes it be applicable to that the more small-scale circuit of centering carries out emulation.And for a SRAM who has only the 1Kb capacity, the transistorized quantity that it comprised can reach several ten thousand usually, and it is just relatively more difficult that this makes that application Hspice carries out emulation to it.EDA company of present a few family has released one after another based on the Spice simulation software of large-scale circuit transistor level, comprising Hsim (Nassda company), Ultrasim (Cadence company), Nanosim (Synopsys company) etc., these softwares are than all fast last tens times of the simulation velocities of hspice.Their appearance has solved the problem that this large-scale circuit of SRAM is carried out high-speed simulation to a certain extent.But, the domain post-simulation speed of at present new software is also also unsatisfactory, reason has two, be because the capacity increase of SRAM is very fast on the one hand, on the other hand process constantly reduce make parasitic parameter increase, this will increase the device count that needs simulation calculation, and the reason of this two aspect makes those high-speed Spice simulation softwares will expect that accurate post-layout simulation results exhibit just has to carry out heavier formula and calculate, and finally causes simulation velocity still slow.
Summary of the invention
A kind of new quick simulator and the rapid simulation method that can be used for the SRAM design have been the objective of the invention is to propose.
A kind of quick simulator of static RAM, circuit layout construction is made of the storage unit that is positioned at the place, summit and the equivalent-circuit model of other locational storage unit, that is to say, except that having kept indivedual original storage unit, the circuit layout of remaining storage unit is all substituted by their equivalent-circuit model.
Circuit layout construction is that the equivalent electrical circuit by storage unit that is positioned at four summits and storage unit constitutes.
The structure of this quick simulator of SRAM is the storage unit at place, summit, the equivalent-circuit model of repeated storage unit a large amount of in the SRAM circuit with them to be replaced in having kept the SRAM domain.In the post-simulation process, can reduce a large amount of emulation device count like this, make simulation time shorten dramatically, thereby improved the efficient of reservoir designs to a great extent.
Why this rapid simulation method is feasible, is because this SRAM quick simulator of simplifying has been preserved all and needed the information of emulation, thereby has guaranteed the integrality of required emulated data.
The characteristics of this quick simulator and method are that the scope of application is very wide, not only are applicable to the SRAM design, can also be used for the reservoir designs of a lot of other types.
Description of drawings
Fig. 1 is a kind of SRAM laying out pattern structural drawing commonly used.
Fig. 2 is the structural drawing of quick simulator.
Fig. 3 is a SRAM rapid simulation method process flow diagram of the present invention.
Fig. 4 is the laying out pattern figure of a typical SRAM.
Fig. 5 contains 4096 storage unit, one six pipe unit figure figure.
Fig. 6 is the structural drawing of quick simulator of the present invention.
Fig. 7 is six pipe unit domains.
Fig. 8 is the equivalent-circuit model figure of storage unit.
Fig. 9 is critical path analysis figure.
Embodiment
This invention proposes at the slow-footed problem of SRAM domain post-simulation, and its simple structure and realization are easily.Its structure is different from the circuit layout of SRAM commonly used, and it has own particular structure, as shown in Fig. 1,2.
Fig. 1 is a kind of SRAM laying out pattern structure commonly used, and Fig. 2 is the structure of quick simulator.By contrast as can be seen, have only a kind of structure of storage unit A in the SRAM storage unit among Fig. 1, and storage unit comprises unit A and two kinds of structures of unit B in the quick simulator structure of Fig. 2.
Wherein, unit A among Fig. 2 and the unit A domain structure among Fig. 1 are identical, but it only is retained on four summits of memory cell array, and other locational storage unit A is all substituted by unit B.Because unit A not only contains the transistor of some, the resistance capacitance that also contains a large amount of parasitisms, and unit B is the equivalent electrical circuit of unit A, it is a kind of equivalent model of simplifying, the device count that it contains is wanted much less compared with unit A, will make that like this device count of post-simulation significantly reduces, thereby can improve the speed of domain post-simulation to a great extent.
Specifically as shown in Figure 3.Usually whole domain being extracted the net table in this emulation mode fast and in the past the SRAM design process, to carry out the flow process of post-simulation then different, and its operating process is divided into three steps.
Step 1 is to find and keep the storage unit domain that is arranged in SRAM domain summit according to existing domain;
Step 2 is the corresponding equivalent-circuit models of single storage unit layout extraction to remainder, normally a kind of resistance capacitance model of this model;
Step 3 is this circuit layout that contains equivalent model to be extracted the net table carry out post-simulation, gets final product and only need carry out emulation to the storage unit at place, summit in the simulation process.
In order to illustrate that above-mentioned emulator and rapid simulation method are accurately and effectively, will prove by an example below.
Fig. 4 is the laying out pattern of a typical SRAM, and capacity is the SRAM domain structure of 4Kb.It mainly is made up of two parts, and a part is a data path, comprises writing driving circuit, core cell and sense amplifier; Another part is an address path, mainly comprises decoding scheme.If this SRAM amount of capacity is 4Kb, 6 read/write address are arranged, the SRAM of single port is an example, its layout structure is as shown in Figure 4.As can be seen from the figure, the area maximum of core cell, reason are that its repetitive is many, are made of 4096 storage unit.What the structure of storage unit adopted mostly in the SRAM circuit is the designs of six pipe units.
One six pipe unit as shown in Figure 5.Contain 4096 storage unit for one, capacity is the SRAM of 4Kb, just contain 24576 transistors in the storage unit, if add decoding scheme, write the transistor in driving circuit and the sensitive amplifier circuit, whole SRAM circuit approximately is made up of more than 30,000 transistors.So many number of transistors if add the resistance capacitance number of a large amount of parasitisms that extract after domain generates, will be a very big net meter file, and this will cause post-simulation speed very slow.
Fig. 6 is the structural drawing of quick simulator of the present invention, and capacity is the emulation emulator of the SRAM of 4Kb.As can be seen from the figure its storage unit partly has two types---unit A and unit B.Unit A has only four, is distributed on four angles of storage array, and they remain the domain of six transistor memory units shown in Figure 5, and domain structure as shown in Figure 7.And unit B and unit A differ widely, and unit B is an equivalent electrical circuit that six pipe unit domains among Fig. 7 are extracted, and is not a domain, and its circuit structure as shown in Figure 8.That is to say that the domain of originally a large amount of storage unit has been substituted by their equivalent electrical circuit.If emulation can be got four unit on the angle earlier, delete the domain of unit B present position, extract the parasitic parameter and net table of residue domain, the net table with substituting unit B combines then, just can carry out emulation.
Below as can be seen, this equivalent-circuit model of unit B does not need the behavior of preserving data or reading of data, and model just plays the effect that load truly substitutes.To carry out emulation exactly to this SRAM circuit model of simplifying, will guarantee that this equivalent-circuit model can comprise the full detail of needed corresponding six transistor memory unit domains.Because shown in Fig. 8 is the equivalent electrical circuit of six pipe unit domains among Fig. 7, is example with it below, and its concrete calculating principle is described.
Storage unit equivalent-circuit model shown in Figure 8 can be divided into two parts, and a part is the equivalent electrical circuit (hereinafter to be referred as word line circuit) at word line, and another part is the equivalent electrical circuit (hereinafter to be referred as bit line circuit) at bit line.
Comprise resistance R 1, R2 and capacitor C 1 in the word line circuit.The six pipe unit domains of representing by Fig. 7 as can be seen, word line WL can be a very long metal connecting line usually because it will cross 64 storage unit, its dead resistance is very big.R1 represents the equivalent resistance of WL line when another storage unit enters next unit, and R2 then is the equivalent resistance that connects metal between transistor 1 and transistor 2 grids among Fig. 5.Calculative equivalent resistance is as long as according to the width of metal in the square resistance of metal under the specific process conditions and the domain, just can calculate.Capacitor C 2 in the word line circuit is equivalent, is transistor 1 and the grid of transistor 2 and the oxide layer electric capacity between the raceway groove, the just load of transistor 1 and 2 pairs of word lines among Fig. 5.Capacitance C
0Can calculate by formula 1 and 2.
Cox is the gate oxide electric capacity of unit area.ε 0=8.85*10 in the formula
-14A S/V cm is a permittivity of vacuum, and ε ox=3.9 is the silicon dioxide relative dielectric constant.
C
0＝C
ox*W*L [2]
W represents transistorized channel width, and L represents transistorized channel length.
According to shown in Figure 8, bit line circuit comprises resistance R 0 and capacitor C 0.Because bit line is the same with word line, runs through whole 64 unit, can not be left in the basket so the delay of metal connecting line is very big.R0 is the equivalent resistance of metal connecting line, equivalent is shown in Fig. 7 for it, enter into the transistor 1 of next unit or the metal connecting line BL or the BL of 2 source electrode from the another one storage unit, the calculating of R0 can be adopted the method for calculating R1, R2 in the above-mentioned word line circuit.
Capacitor C 0 is transistor 1 and 2 a source electrode equivalent capacity among Fig. 5 in the bit line circuit.Because the electric capacity in source/drain region mainly shows as the junction capacity between source/drain region and the substrate, so can calculate according to following formula.
C
diff＝C
jL
SW+C
JSW(2L
S+W) [3]
Wherein, L
SBe the length in source/drain region, W is the width in source/drain region.C
jBe the source/drain junction electric capacity of unit area, C
JSWIt is the source/leakage sidewall capacitance of unit length.
In a word, sort circuit is exactly the domain that has kept four summits in the SRAM storage unit domain, and the domain of other storage unit is replaced with their equivalent electrical circuit.As long as, add that simultaneously the net table of the equivalent electrical circuit of storage unit just can carry out the domain post-simulation so possess the domain of unit, summit and the domain of other peripheral circuit.
This SRAM structural model of simplifying can guarantee the integrality of required emulated data.This is determined by the position of SRAM storage unit and circuit structure.
Critical path analysis as shown in Figure 9, Ay, By, Cy, Dy represent respectively write operation four paths of process, Ax, Bx, Cx, Dx represent four paths of read operation respectively.Because clock is to introduce from the lower left of entire circuit, this has just determined no matter be write operation or read operation, and their critical path only may be in above-mentioned four paths.If calculate the time of a write operation, just adopt the longest path of write operation.As shown in the figure, the longest path of write operation only may be By, and this is because these row of clock signal arrival B, unit, D place are the slowest, so the time that their trigger the latest, apart from writing driving circuit farthest, the time that signal arrives is also just the longest again in the B unit simultaneously; In like manner, the longest path of read operation may be among Dx or the Bx, this is because of A, this row distance clock of unit, B place farthest, but they are nearest apart from sense amplifier, and the path of C, this delegation of unit, D place and A, this delegation of B is on the contrary, because of B, D cell distance decoding scheme farthest,, specifically adopt which bar will determine by emulation at last again so critical path only may be one among Bx, the Dx.
In addition, because SRAM is a sequential circuit, also must comprise the foundation and the retention time of each port in the performance parameter that is used for it is described, and this circuit of simplifying has comprised all data paths that need test, principle is the same.
By above explanation, this circuit model of simplifying has been preserved all needs the information of emulation.
In sum, this quick simulator has made full use of the many characteristics of repetitive in the SRAM circuit, and the equivalent electrical circuit of a large amount of repetitives with them replaced, and has reduced the device count that needs emulation to a great extent, thereby saved a large amount of simulation times, shortened the design cycle.Simultaneously, this SRAM structural circuit of simplifying can guarantee the integrality of required emulated data, and it has preserved all needs the information of emulation.And its scope of application is very wide, not only is applicable to the SRAM design, can also be used for the reservoir designs of a lot of other types.
Specific embodiment
The present invention has obtained application in the SRAM design process of Godson II CPU, what it adopted is the 0.18umCMOS of SMIC technology, and we have designed one 64, and frequency of operation is 500 megahertzes, the SRAM of capacity 4Kb.For accuracy and the reliability of verifying this method, the result that we measure this kind method compares with the result of final whole domain post-simulation, has listed the comparative result of several typical datas in the table 1.Simultaneously, also a large amount of emulated datas is contrasted, the result shows that the maximum deviation between the two does not surpass 5%, and each simulation velocity has improved nearly one times, thereby work efficiency is greatly improved.Entire chip has been passed through the checking of flow at present, and the result who has proved absolutely emulation testing is accurately and reliably.
The contrast of table 1 simulation result
Claims (4)
1, a kind of quick simulator of static RAM, it is characterized in that, circuit layout construction is made of the storage unit that is positioned at the place, summit and the equivalent-circuit model of other locational storage unit, except that having kept indivedual original storage unit, the circuit layout of remaining storage unit is all substituted by their equivalent-circuit model.
According to the quick simulator of the static RAM of claim 1, it is characterized in that 2, circuit layout construction is that the equivalent electrical circuit by storage unit that is positioned at four summits and storage unit constitutes.
3, according to the quick simulator of the static RAM of claim 2, it is characterized in that storage unit contains the transistor of some, also contain the resistance capacitance of a large amount of parasitisms, equivalent electrical circuit is a kind of equivalent model of simplifying.
4, a kind of rapid simulation method based on static RAM is characterized in that, it is divided into three operation stepss, and is specific as follows:
Step 1 finds and keeps the storage unit domain that is arranged in static RAM domain summit according to existing domain;
Step 2, to the corresponding equivalent-circuit model of storage unit layout extraction of remainder, normally a kind of resistance capacitance model of this model;
Step 3 is carried out post-simulation to this whole extraction net of the circuit table that contains equivalence, gets final product and only need carry out emulation to the storage unit at place, summit in the simulation process.
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| CNB2004100746780A CN100367285C (en) | 2004-09-13 | 2004-09-13 | Quick simulator based on static random storage and method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982847A (en) * | 2012-11-29 | 2013-03-20 | 上海集成电路研发中心有限公司 | Testing system and testing method for parasitic parameters of static random access memory |
| CN103093016A (en) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method for simulating high-capacity memory by imitating net list after simplifying memory |
| CN112597733A (en) * | 2020-12-30 | 2021-04-02 | 北京华大九天科技股份有限公司 | Storage unit identification method and device and computer readable storage medium |
| CN112699632A (en) * | 2020-12-23 | 2021-04-23 | 成都海光微电子技术有限公司 | Method and device for acquiring total power consumption of circuit in circuit design |
| CN118070717A (en) * | 2024-04-17 | 2024-05-24 | 全芯智造技术有限公司 | Storage unit coupling simulation method and device, storage medium and computing equipment |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10222545A (en) * | 1997-01-31 | 1998-08-21 | Sony Corp | Parameterized memory circuit degenerating method and logic cell library generating method |
| US6807520B1 (en) * | 2000-12-11 | 2004-10-19 | Synopsys, Inc. | System and method for simulation of an integrated circuit design using a hierarchical input netlist and divisions along hierarchical boundaries thereof |
| CA2340804A1 (en) * | 2001-03-14 | 2002-09-14 | Atmos Corporation | Sram emulator |
| JP2004013821A (en) * | 2002-06-11 | 2004-01-15 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit designing method and device |
| JP2004086318A (en) * | 2002-08-23 | 2004-03-18 | Sharp Corp | Device for generating equivalent circuit model for simulation, circuit simulation system, method for generating equivalent circuit model for simulation, control program, and readable recording medium |
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2004
- 2004-09-13 CN CNB2004100746780A patent/CN100367285C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103093016A (en) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method for simulating high-capacity memory by imitating net list after simplifying memory |
| CN103093016B (en) * | 2011-11-04 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | After simplifying storer, imitative net table realizes the method for mass storage emulation |
| CN102982847A (en) * | 2012-11-29 | 2013-03-20 | 上海集成电路研发中心有限公司 | Testing system and testing method for parasitic parameters of static random access memory |
| CN102982847B (en) * | 2012-11-29 | 2017-07-25 | 上海集成电路研发中心有限公司 | A kind of test system and method for the parasitic parameter of SRAM |
| CN112699632A (en) * | 2020-12-23 | 2021-04-23 | 成都海光微电子技术有限公司 | Method and device for acquiring total power consumption of circuit in circuit design |
| CN112597733A (en) * | 2020-12-30 | 2021-04-02 | 北京华大九天科技股份有限公司 | Storage unit identification method and device and computer readable storage medium |
| CN118070717A (en) * | 2024-04-17 | 2024-05-24 | 全芯智造技术有限公司 | Storage unit coupling simulation method and device, storage medium and computing equipment |
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