CN1743855A - Method and ic for detecting capacitance variation - Google Patents

Abstract

A method and an integrated circuit (IC) for detecting capacitance variation are disclosed. In order to resolve the prior art problem that sensitivity of detecting capacitance variation is decreased by a time delay component td of a charging/discharging unit, the present invention employs two time divided frequencies. More specifically, the method for detecting capacitance variation comprises the steps of: generating a detection frequency (fa) for capacitance variation and a detection frequency (fb) which lags the detection frequency (fa) by k times, wherein the detection frequencies (fa and fb) are based on a time divisional format; operating the detection frequencies (fa and fb) to produce a difference frequency (fd); operating variation rate of the difference frequency; and comparing the variation rate of the difference frequency with a predetermined detection level, and outputting a signal indicative of capacitance variation if the variation rate of the difference frequency is greater than the detection level. Therefore, the present invention can enhance sensitivity of detecting capacitance variation.

Description

Detect the method and the integrated circuit of capacitance variations

Technical field

The present invention relates to the method and the integrated circuit (IC) of a kind of detection capacitance variations (capacitance variation), particularly relate to a kind of method and IC that can use two time-division frequency detecting capacitance variations, thereby improve the sensitivity that detects capacitance variations.

Background technology

The integrated circuit that detects capacitance variations in the prior art is embodied as the change of the detection frequency that will change according to capacitance variations and compares with reference frequency, and when result's difference is higher than predetermined value as a comparison output detection frequency.Owing to produce to detect the time delay parts of charge/discharge control module of the frequency generator of frequency, can not be fully and capacitance variations produce the detection frequency pro rata.Therefore when detecting less relatively capacitance variations, can produce a large amount of errors.

Fig. 1 is a circuit of describing unifrequency generator in the prior art.With reference to figure 1, target capacitance is installed in the input block of the integrated circuit (IC) that is used for detecting capacitance variations, thereby the capacitance variations of target capacitance can be detected.Before detecting, the capacitance of hypothetical target electric capacity is expressed as Cs, the steady current that target capacitance is carried out charge/discharge is expressed as Is, the stray capacitance that the wiring of input block produces is expressed as Cp, and the time delay of charge/discharge control module is expressed as td, wherein time delay td comprises Schmidt trigger (Schmitt trigger) SCHMITT_A, phase inverter INV_1A, the switching delay component of PMOS transistor PM1～PM3 and nmos pass transistor NM1～NM3.Time (cycle) Ta represents to reach the spent time of incoming level Vth (Vth=Vb-Va) of Schmidt trigger SCHMIT_A when target capacitance begins charging up to its anodal level (positive lead level), and is expressed as following formula:

$1/\mathrm{fa}=\mathrm{Ta}=\mathrm{td}+\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp})}{\mathrm{Is}}---\left(1\right)$

The capacitance Cs of the target capacitance in being installed on input block changes under the situation of Cs+Cx, and time (cycle) Ta ' expression reaches the spent time of Vth when target capacitance begins to charge up to its anodal level, and is expressed as following formula:

$1/f{a}^{\′}=T{a}^{\′}=\mathrm{td}+\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp}+\mathrm{Cx})}{\mathrm{Is}}---\left(2\right)$

Therefore, the change in cycle is expressed as following formula:

$\frac{T{a}^{\′}-\mathrm{Ta}}{\mathrm{Ta}}=\frac{\mathrm{Cx}}{(\mathrm{Cs}+\mathrm{Cp})+(\mathrm{Is}/2\mathrm{Vth})\·\mathrm{th}}---\left(3\right)$

By above-mentioned equation, unless become enough little for the time delay td of the charge/discharge control module of capacitance variations Cx, thus otherwise reduce for the variation of the detection frequency f a of capacitance variations Cx very little its sensitive precision that becomes.Especially, increase to prevent external noise if detect frequency, the equipment of prior art can be subjected to the influence of the component of time delay td to a great extent.

Therefore, because the time delay component of charge/discharge control module, the shortcoming of the IC of prior art is, and is less relatively with the variation of the detection frequency of capacitance variation, thereby can not detect very little capacitance variation.

Summary of the invention

Therefore, the present invention is conceived to the problems referred to above and proposes, and a target of the present invention provides a kind of method that detects capacitance variations, and the influence of the time delay parts of charge/discharge control module is minimized, and improve the measuring accuracy of capacitance variations, and IC also is like this.

According to one aspect of the invention, above-mentioned and other targets can realize by a kind of method that detects capacitance variations is provided, described method comprises step: produce for the detection frequency (fa) of capacitance variations and lag behind and detect frequency (fa) k times detection frequency (fb), wherein said detection frequency (fa and fb) is based on time format; Calculate described detection frequency (fa and fb) to produce differential frequency (fd); Calculate the rate of change of described differential frequency; The rate of change of described differential frequency is compared with the predetermined detection level, and if the rate of change of described differential frequency be higher than described detection level then export the signal that shows capacitance variations.

Preferably, the rate of change that calculates described differential frequency can comprise step: produce reference frequency (fr (t)), be expressed as following formula,

If fr (t)=fr (t-1)+m-n is fd (t)-fd (t-1)＞m;

If fr (t)=fr (t-1)+g is 0≤fd (t)-fd (t-1)≤m; And

Fr (t)=fr (t-1)+h, if fd (t)-fd (t-1)＜0,

Wherein t and t-1 represent current period and previous cycle, m 〉=1,0＜n＜m, g 〉=1, h 〉=1, and g＞h respectively; And

Calculate rate of change (fr (t)-fd (t))/fr (t) of described differential frequency.

According to a further aspect of the present invention, a kind of integrated circuit (IC) that detects capacitance variations is provided, comprise: the bifrequency generating unit, be used to produce for the detection frequency (fa) of the capacitance variations of target capacitance and lag behind and detect frequency (fa) k detection frequency (fb) doubly, wherein said detection frequency (fa and fb) is based on time format; The differential frequency arithmetic element is used to calculate described detection frequency (fa and fb) to produce differential frequency (fd); Differential frequency rate of change computing unit is used to calculate the rate of change of described differential frequency; Detect the level input block, be used to import the predetermined detection level; Comparer is used for the rate of change of described differential frequency is compared with the detection level that is input to described detection level input block; And output unit, when being used for rate of change when the described differential frequency of described comparer and being higher than described detection level its high level is converted to low level and exports described low level signal.

Preferably, described differential frequency rate of change computing unit can comprise: the reference frequency generation unit, be used to produce reference frequency (fr (t)), and this reference frequency is expressed as following formula,

If fr (t)=fr (t-1)+m-n is fd (t)-fd (t-1)＞m;

If fr (t)=fr (t-1)+g is 0≤fd (t)-fd (t-1)≤m; And

Fr (t)=fr (t-1)+h, if fd (t)-fd (t-1)＜0,

Wherein t and t-1 represent current period and previous cycle, m 〉=1,0＜n＜m, g 〉=1, h 〉=1, and g＞h respectively; And

Computing unit, it is used to calculate rate of change (fr (t)-fd (t))/fr (t) of described differential frequency.

Preferably, described integrated circuit (IC) may further include: the reference frequency holding unit, be used to keep the reference frequency (fr (t)) of the time that depends on, and described reference frequency results from the reference frequency generation unit.

Preferably, described reference frequency holding unit can comprise resistance, thereby the retention time of reference frequency (fr (t)) depends on the resistance of described resistance and determines.

Preferably, described output unit can comprise integrator, is used for the comparative result from described comparer output is carried out integration.

Preferably, described detection level input block can comprise single external pin, and internal reference clock, current source and external capacitive (Cd) can be connected to this pin, thereby external capacitive (Cd) can be by described current source charging;

The voltage that wherein said detection level input block is measured described external capacitive (Cd) reaches the time of preset reference voltage (Vth) and selects to detect level according to the coding of determining based on the measured time, thereby imports a plurality of detection level by single pin.

Preferably, described integrated circuit (IC) may further include:

Bifrequency modulator (DFM) unit makes that described bifrequency generating unit increased the generating period (occurrence period) of described detection frequency (fa) in the given time when rate of change when described differential frequency was greater than or less than described detection level.

Preferably, described integrated circuit (IC) may further include: the enable signal I/O unit, it is configured to be in enabled state and be in waiting status when importing low-voltage from outside input high voltage the time, wherein said enable signal I/O unit self produces low level signal and not from outside input low level signal, and export described low level signal to the outside to communicate at DFM duration of work and adjacent elements.

Preferably, described bifrequency generating unit is disposed in a large number, generates the detection frequency (fa and fb) to a plurality of target capacitances, and the quantity enable signal I/O unit identical with the quantity of described bifrequency generating unit is mounted thereto.

Preferably, described target capacitance serial or parallel connection be connected to sensitivity adjusting electric capacity, be connected to described bifrequency generating unit simultaneously.

Description of drawings

Above-mentioned and other targets of the present invention, feature and other advantages can be by more being expressly understood in conjunction with the detailed description of following accompanying drawing, wherein:

Fig. 1 is a circuit of describing the unifrequency generator of prior art;

Fig. 2 is a schematic block diagram of describing the IC that detects capacitance variations according to first embodiment of the invention;

Fig. 3 is the circuit diagram and the oscillogram of describing its operation of the bifrequency generator 110 of IC among Fig. 2;

Fig. 4 is the detailed circuit diagram and the oscillogram of describing its operation of the bifrequency generator 110 of IC among Fig. 2;

Fig. 5 is the diagram that shows the influence of the time delay component td that describes the control module that charges/recharge among Fig. 2;

Fig. 6 shows reference frequency fr and detects the diagram that concerns between the frequency f d;

Fig. 7 is the structural drawing that explanation detects level;

Fig. 8 is the view that shows the waveform that detects the level input;

Fig. 9 is a view of describing the operation of DFM unit 200; And

Figure 10 is the schematic block diagram of description according to the IC of the detection capacitance variations of second embodiment of the invention.

Embodiment

Although show and described the present invention, it will be understood by those skilled in the art that and to make various changes and modification and do not deviate from essence of the present invention with reference to preferred embodiment.Therefore, scope of the present invention should not limited by embodiments of the invention.

[first embodiment]

Fig. 2 is the schematic block diagram of description according to the integrated circuit (IC) 100 of the detection capacitance variations of first embodiment of the invention, and wherein said IC is embodied as the chip with six pins.With reference to figure 2, describe method below in detail according to detection capacitance variations of the present invention.First pin of described chip is used for input voltage V+ as input end.Second pin is used for input voltage V-as input end.The 3rd pin is as output terminal.The 4th pin is used for the I/O enable signal as the I/O end.The 5th pin is used for input as input end and detects level.The 6th pin is as input end, and capacitance Cs puts on this pin.

[bifrequency generation]

When the capacitance Cs of target capacitance was applied to bifrequency generator 110 by the 6th pin, bifrequency generator 110 was that capacitance variations produces and detects frequency f a and fb with the time format.At this, the strength of current k of the electric current of the leading fb inflow of the strength of current target capacitance of the electric current of fa inflow target capacitance doubly.

Fig. 3 is the circuit diagram and the oscillogram of describing its operation of the bifrequency generator 110 of IC among Fig. 2.When F_CTRL is low level signal GND, PMOS transistor PM7 and nmos pass transistor NM7 are energized, thereby they excessive provide electric current I 3 and I4 to each current source.Therefore, turn-off respectively to the PMOS transistor PM4 of target capacitance charging with to the nmos pass transistor NM6 of its discharge.

In this state, discharge by PMOS transistor PM2 charging and by nmos pass transistor NM2 owing to have the target capacitance of capacitance Cs, charging and discharge current Is are applied to this electric capacity.When having capacitance Cs's, when reaching the upper voltage limit Vb of Schmidt trigger SCHMITT_A via the voltage of PMOS transistor PM2 by the electric capacity of input steady current Is charging, Schmidt trigger SCHMITT_A becomes height with its output from low, and phase inverter INV_1A is low with its output from hypermutation.Therefore, nmos pass transistor NM3 turn-offs and PMOS transistor PM3 conducting, thereby PMOS transistor PM2 turn-offs and nmos pass transistor NM2 conducting, thereby flows through steady current Is to capacitor discharge by NM2.On the other hand, if the voltage of target capacitance reaches voltage Va, the voltage of Schmidt trigger SCHMITT_A is low level, and PMOS transistor PM3 turn-offs and nmos pass transistor NM3 conducting, thereby target capacitance begins to recharge by PMOS transistor PM2.Herein, above-mentioned a series of process carries out having with generation the output waveform OUT_B of frequency f b repeatedly.

On the other hand, when F_CTRL was high level signal, the operation of PM6 and NM4 was identical with the operation of PM3 and NM3, thereby target capacitance charges by PM2 and PM4 and discharges by NM2 and NM6.At this, each charging and discharge current are respectively KIs, have leading frequency f b K frequency f a doubly.Frequency f a and fb are expressed as following formula,

$1/\mathrm{fa}=\mathrm{Ta}=\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp})}{k\·\mathrm{Is}}+\mathrm{td}---\left(4\right)$

$1/\mathrm{fb}=\mathrm{Tb}=\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp})}{\mathrm{Is}}+\mathrm{td}---\left(5\right)$

Herein, Cs represents the capacitance of target capacitance, Is is illustrated in the steady current when carrying out the charge/discharge operation in the bifrequency generator 110, Cp represents the stray capacitance of bifrequency generator 110, td represents the time delay of charge/discharge control module, and Vth (=Vb-Va) be the triggering level of Schmidt trigger SCHMITT_A.

When the capacitor C s that is connected to the 6th pin changes into capacitor C s+Cx, detect frequency f a ' and fb ' and be expressed as following formula,

$1/f{a}^{\′}=T{a}^{\′}=\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp}+\mathrm{Cx})}{k\·\mathrm{Is}}+\mathrm{td}---\left(6\right)$

$1/f{b}^{\′}=T{b}^{\′}=\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp}+\mathrm{Cx})}{\mathrm{Is}}+\mathrm{td}---\left(7\right)$

Therefore, frequency change is expressed as following formula,

$\frac{d{T}^{\′}-\mathrm{dT}}{\mathrm{dT}}=\frac{\mathrm{Cx}}{(\mathrm{Cs}+\mathrm{Cp})}---\left(8\right)$

That is to say, although the time delay td component of charge/discharge control module influences frequency change rate when electric capacity is adopted single oscillation frequency, to its two frequency components using time format to obtain differential frequency.After this, based on described differential frequency, can obtain the rate of change of differential frequency.By this result, because capacitance variations roughly is directly proportional with the rate of change of described differential frequency, if the proportion of stray capacitance reduces, capacitance variations is proportional with it more.

[influence of time delay td]

Fig. 4 is the detailed circuit diagram and the oscillogram of describing its operation of the bifrequency generator 110 of IC among Fig. 2.With reference to figure 4, describe the influence of time delay td below in detail.

When PDL when low, transistor M17 and M10 turn-off, and the path of therefore target capacitance being carried out charge/discharge is disconnected.Target capacitance is by transistor M15 and M2 charge/discharge.In the case, charge/discharge current reduces and therefore oscillation frequency reduction, shown in Fig. 4 waveform.

On the other hand, as PDL when being high, charge/discharge current accumulates together by M17, M10, M15 and M2 simultaneously, thereby total charge/discharge current increases.Therefore, the oscillation frequency of oscillator OSC increases.

T oscillation period of oscillator OSC is expressed as following formula,

$T=\frac{2\mathrm{Vth}(\mathrm{Cs}+\mathrm{Cp})}{k\·\mathrm{Is}}+\mathrm{td}---\left(9\right)$

Oscillation frequency is determined by the reference voltage Vth of capacitance Cs, stray capacitance Cp, the time delay td of charge/discharge control module, the charge/discharge current Is that flows through resistance R O and the Schmidt trigger SCHMITT of the target capacitance that is installed in the IC outside.

The time delay td of charge/discharge control module comprises the switching delay component that switching delay component that phase inverter I0, I1 in the phase inverter loop of oscillator OSC and I5 produce and MOS transistor M19, M17, M6, M10, M13, M1 and M2 produce.

When the voltage by capacitor C s+Cp charging was higher than the reference voltage Vth of Schmidt trigger SCHMITT, after Schmidt trigger SCHMITT reversed its output, discharge (charging) path should be turn-offed and switch in charging (discharge) path immediately.But because the existence of the time delay td of charge/discharge control module, charge/discharge path process td time delay after Schmidt trigger SCHMITT reverses its output just changes.Therefore, if oscillation frequency increases, the frequency change of electric capacity is owing to time delay td departs from proportionate relationship, as shown in Figure 5.

With reference to figure 2, for fear of the influence of the time delay td of above-mentioned charge/discharge control module, the present invention has adopted the bifrequency fa and the fb of time format.Described bifrequency fa and fb produce and are stored among frequency storage unit 110a and the 110b by bifrequency generating unit 110, thus they by differential frequency arithmetic element 120 calculated with produce differential frequency fd (=fa-fb).Described differential frequency is used to produce differential frequency rate of change R in differential frequency rate of change computing unit 130.

[reference frequency generation]

Describe the calculating of differential frequency rate of change below in detail.At first, produce reference frequency fr by reference frequency generating unit 130a.Because reference frequency fr compares and is used for capacitance variations with detecting frequency, suitable generation reference frequency fr is very important, thereby can remove external noise and can be from its output signal from it.

Reference frequency fr is expressed as following formula under specified criteria:

If fr (t)=fr (t-1)+m-n is fd (t)-fd (t-1)＞m;

If fr (t)=fr (t-1)+g is 0≤fd (t)-fd (t-1)≤m; And

If fr (t)=fr (t-1)+h is fd (t)-fd (t-1)＜0.

According to these formula, reference frequency fr and the relation that detects between the frequency f d are presented among Fig. 6.At this, m 〉=1,0＜n＜m, g 〉=1, h 〉=1, and g＞h.

With reference to figure 6, increase sharply (surpassing m) if detect frequency, reference frequency fr is to increase to the speed that gathers way similar that detects frequency so.Therefore, because reference frequency fr follows the detection frequency at short notice, reflection immediately detects the quick variation of frequency, can reach stable state rapidly and can detect capacitance variations immediately after powering up.

Although make that detecting frequency reduces because electric capacity increases under the condition of g＞h, reference frequency fr slowly reduces, thereby capacitance variations can be detected.

Herein, g preferably is set to relatively large value, thereby the capacitance of target capacitance can recover rapidly so that electric capacity is stable when its increase reduces then.Being provided with like this can detect the state that detects the frequency hysteresis reference frequency owing to the instantaneous increase of the capacitance of target capacitance immediately.

[differential frequency rate of change]

When producing reference frequency fr by reference frequency generating unit 130a, calculating differential frequency rate of change R in computing unit 130b (=(fr-fd)/fr).Differential frequency rate of change R can calculate by (fr-fd)/fr be multiply by suitable weight.

[output]

Comparer 140 will be input to the detection level DL that detects level input block 150 and compare with frequency change rate R, then the result be outputed to output unit 170.If differential frequency rate of change R is greater than detecting level DL, then output unit 170 is low with its output signal from hypermutation, then by the 3rd pin output low level signal.Preferably, output unit 170 comprises that the result who is used for comparer 140 carries out integration with integrator 170a that prevents the noise in the schedule time and the buffer memory 170b that is used to store integral result.

[detecting the level input]

External capacitive Cd is connected to the 5th pin, thereby can charge by the electric current that provides from the 5th pin under predetermined level.At this, under the strength of current from the electric current of the 5th pin output is constant condition, if a plurality of electric capacity are arranged, for example Cd1, Cd2 and Cd3, connection one by one, each external capacitive all is charged to preset reference voltage Vth, and its duration of charging is according to the capacitance separately of a plurality of electric capacity and inequality.Therefore, based on the measurement in duration of charging, can select to detect level according to the coding of determining in the chip.

Based on the reference clock that produces in the system clock generating unit, external capacitive Cd uses the electric current I 1 of the current source that equates with the electric current I 3 of another current source of adopting in the system clock generating unit to charge.Simultaneously, the charge value of counter measures external capacitive Cd reaches the time of the input limit value Vb of Schmidt trigger SCHIMITT_A.Herein, when the ENABLE of the input end that is input to counter (RST) input signal when low, counter is counted the quantity of the system clock SYSTEMCLOCK that is input to the counter clock end and is exported count results by output terminal with digital value.

ENABLE (RST) input signal produces by START signal and voltage Vout_Cd are carried out the OR computing.If the result of logic OR computing is low, then counter is activated.If the result is high, then counter is invalid.On the other hand, if the START signal is low, the external capacitive that then has capacitance Cd begins charging.Simultaneously, Vout_Cd is charged to height with its state from hanging down when V_CD reaches Vb.During this period, counter output count value.On the other hand, if the START signal is high, external capacitive Cd discharge and wait next cycle.The low state duration of Vout_Cd increases relatively when the capacitance Cd that is connected to outside external capacitive is relatively large.

When the START clock is illustrated in figure 8 as when low, select to detect the time of level by the counter measures of Fig. 7.When START clock when being high, counter is waited for next low period of state in reset mode.In the case, can periodically select, can increase respectively specific period/reduce and detect level owing to detect level.And, can use single external pin to import a plurality of detection level.Certainly, when having the external capacitive of capacitance Cd, preferably can adopt identical reference clock and current source so that new electric capacity is alternative.Herein, the variation of the current source that produces in the IC manufacture process can reduce, and is identical with the current source of the I3 of output current I2 and system clock unit because output shown in Figure 7 is set to the current source of the electric current I 1 of outside capacitor C d charging.

Sensitivity can change according to the capacitance Cd of external capacitive, and also can change by the capacitance Cs that regulates target capacitance.Be embodied as according to detection according to the present invention IC target capacitance in the detection chip capacitance Cs variation and produce output greater than corresponding to the rate of change of the capacitance Cd of external capacitive the time at the rate of change of capacitance Cs.

Herein, capacitance Cs is bigger, and the rate of change Δ Cs/Cs of capacitance Cs is less.Therefore, although the capacitance Cd of external capacitive does not change, the capacitance of the 6th pin changes fully and sensitivity also changes if the electric capacity that serial or parallel connection connects adjusting sensitivity between the 4th and the 6th pin to target capacitance, then is applied to.

[reference frequency maintenance]

When the capacitance Cs of target capacitance increased, differential frequency fd reduced.If the rate of change of differential frequency (reduction rate) is greater than detecting level, then output unit output low level signal.Fd reduces along with differential frequency, and it becomes and equates that with reference frequency is intimate differential frequency fd is similar to reference frequency in moment.In this moment, because the rate of change of differential frequency fd can not can detect capacitance variations less than detecting level.

Reference frequency holding unit 160 has time according to the reference frequency fr (t) that produces in the reference frequency generating unit 130 and keeps the function that changes.Reference frequency holding unit 160 is embodied as and comprises the installation resistance with predetermined resistance within it, thereby produces steady current by described resistance in the system clock generating unit, and produces steady current I2 and I3 as shown in Figure 7.Herein, resistance is variable.When resistance value was relatively large, internal clock speed was lower, and the reference frequency retention time increases.In the case, can detect capacitance variations slowly.On the other hand, when resistance value relatively hour because reference frequency can be followed the very fast relatively capacitance variations that changes rapidly, can under noise conditions, overcome the state of the capacitance variations of irregular change.

[bifrequency modulation (DFM)]

The present invention includes bifrequency modulation (DFM) unit 200, its generating period that is used for regulating frequency fa is to reduce power consumption.Because the power that is directly proportional with its frequency of operation of CMOS transistor dissipation, need to reduce generating period with relative frequency f a than high oscillation frequency, reduce power consumption thus.

To this, comparer 140 begins to discern detection signal, and the occurrence frequency of fa (occurrencefrequency) increases, thereby integrator 170a can carry out integration to it.After this produce output based on integral result.Yet because detection signal often mixes with noise, unless detection signal is discerned continuously, otherwise the detection signal of initial identification can be defined as noise component mistakenly.Therefore, the occurrence frequency of fa reduces once more.Herein, the time representation comparer 140 of identification detection signal is at rate of change R output result's when detecting level start time point, and it still be the time point of capacitance Cs normal increase when not having noise of target capacitance.

Under the situation that detection signal is identified, the occurrence frequency of fa increases, detection signal is integrated, integrated signal is determined, and produce final output, owing to be in stable state, the occurrence frequency of fa reduces to reduce power consumption (part is that capacitance Cs increases, and the capacitance Cs of Zeng Jiaing remains on predetermined value then).That is to say, the occurrence frequency of fa reduces in the detected state of the time point of time point that produces (Cs increases) with respect to the initial detecting signal and initial detecting release signal generation (Cs reduces) and non-detection status, and the occurrence frequency of fa increases in the given time.Therefore, can prevent the delay of circuit working in the total system, the occurrence frequency of fa is changed reducing power consumption, and the fb that has relatively than small frequency vibrated in the remaining cycle.In order further to reduce power consumption, the frequency of fb can be set to zero.Being created in the initial detecting signal generation unit 210 of initial detecting signal and initial detecting release signal is detected.

The cycle that consumes the frequency f a of more relatively power is concentrated generation when capacitance variations is changed, and reduces in the gap that capacitance variations does not have to change, and reduces the power that circuit working consumes thus.

[enable signal I/O unit]

Enable signal I/O unit 220 can be distinguished modes of circuit operation and standby mode, and considers current drain under the situation of battery and reduce working current or the like in standby mode using.That is to say that in standby mode, DFM unit 200 suspends the generation of fa and fb, to limit current drain as far as possible.

Enable signal I/O unit 220 is identified as enabled state when being high and is identified as waiting status when low at described voltage at the voltage that applies from the outside by the 4th pin.

When DFM unit 200 within it among portion's storer 110a and the 110b storing frequencies time from the 4th pin input low level signal to wherein the time, wherein may produce operating mistake.Therefore, low level signal can not be input in the DFM unit 200 in the storing frequencies in order to make in DFM unit 200 in internal storage 110a and 110b, thus described DFM unit 200 self produce low level signal and by the 4th pin with described low level signal output to the outside can with other chip communications.

Therefore, when using a plurality of chip simultaneously, if enable signal I/O unit 220 is connected to each other, chip A work is stored frequency f a in the storer into then to produce frequency f a.When storing frequencies fa in storer, the enable signal I/O unit 200 output low level signals of chip A are to other chips that are electrically connected with it.That is to say, when low level signal when chip A sends to other chips, other chips keep its operation to wait for next operation.After the operation of chip A stops, the enable signal I/O unit 220 output high level signals of chip A.Therefore, the DFM unit is based on sequence order work, and wherein at the time point that produces fa, other chips are closed.

Therefore, fa can not produce in a plurality of chips simultaneously.Especially, the interference of chip chamber can be lowered when abominable noise exists.When the signal with predetermined high gap was applied to the enable signal I/O unit by outside microcomputer etc. by the 4th pin, chip only worked in described high gap.Therefore, because chip is only worked in the required cycle, current drain can be optimized.

Although aforesaid embodiments of the invention have been described the situation that is provided with the single channel IC with bifrequency generating unit 110 in the chip, the present invention may be embodied as the situation that the hyperchannel IC with a plurality of bifrequency generating units 110 is set in the single chip that is included in.For hyperchannel IC, can detect the capacitance variations of a plurality of target capacitances, the quantity of described a plurality of target capacitances equates with the quantity of bifrequency generating unit 110.When a plurality of bifrequency generating unit 110 wherein has been installed, be used to control a plurality of DFM unit 200 of described a plurality of bifrequency generating units 110, a plurality of enable signal I/O units 220, and a plurality of initial detecting signal generation units 210 also are installed in wherein, and these unit correspond respectively to a plurality of bifrequency generating units 110.Because a plurality of enable signal I/O units 220 communicate between mutually, single chip can prevent to produce simultaneously fa.

[second embodiment of the invention]

Figure 10 is the schematic block diagram of description according to the IC 100 of the detection capacitance variations of second embodiment of the invention, and wherein said IC has six pins.Except the 4th pin keeps the input end as incoming frequency, second embodiment of the invention is identical with first embodiment of the invention.Certainly, second embodiment of the invention may be embodied as additional pin (for example the 7th pin) that further installation incoming frequency keeps input in first embodiment of the invention and do not remove the 4th pin.Like this, when the 4th pin is used for incoming frequency maintenance input signal, can suitably select reference frequency fr to follow the speed of differential frequency by this pin.

From top description obviously as seen, because the present invention uses two time-division frequencies rather than single frequency to detect the capacitance variations of target capacitance, it can not be subjected to the influence of the time delay of charge/discharge control module, thereby improves the sensitivity to capacitance variations.And owing to can import a plurality of detection level by single external pin, IC chip of the present invention can reduce size.

When capacitance variations changed in DFM unit 200, the generating period that consumes the frequency f a of more relatively power significantly increased, and reduced the time cycle when electric capacity is close to change, thereby reduced the power consumption of circuit working.And the generating period of fa of a plurality of chips that is electrically connected to a plurality of enable signal I/O ends is not overlapping.Especially, when having serious noise, can reduce the interference of chip chamber.And when the signal with high gap was provided to enable signal I/O end by outside microcomputer etc., chip only was operated in high gap.Therefore, because chip is only worked in the required cycle, current drain can be optimized.

Although for the preferred embodiments of the present invention that disclose of illustrative purpose, those skilled in the art will appreciate that and to make various modifications, interpolation and replacement and do not deviate from scope of the present invention and the essence that proposes in the appended claims.

Claims (14)

1. method that detects capacitance variations comprises step:

Generation is for the detection frequency (fa) of capacitance variations and lag behind and detect frequency (fa) k detection frequency (fb) doubly, and wherein said detection frequency (fa and fb) is based on time format;

Calculate described detection frequency (fa and fb) to produce differential frequency (fd);

Calculate the rate of change of described differential frequency; And

The rate of change of described differential frequency is compared with the predetermined detection level, and if the rate of change of described differential frequency be higher than described detection level then export the signal that shows capacitance variations.

2. method according to claim 1, the step of the rate of change of wherein said calculating differential frequency comprises:

Produce reference frequency (fr (t)), be expressed as following equation,

If fr (t)=fr (t-1)+m-n is fd (t)-fd (t-1)＞m;

If fr (t)=fr (t-1)+g is 0≤fd (t)-fd (t-1)≤m; And

Fr (t)=fr (t-1)+h, if fd (t)-fd (t-1)＜0,

Wherein t and t-1 represent current period and previous cycle, m 〉=1,0＜n＜m, g 〉=1, h 〉=1, and g＞h respectively; And

Calculate rate of change (fr (t)-fd (t))/fr (t) of described differential frequency.

3. integrated circuit (IC) that detects capacitance variations comprising:

The bifrequency generating unit is used to produce for the detection frequency (fa) of the capacitance variations of target capacitance and lags behind and detects frequency (fa) k detection frequency (fb) doubly, and wherein said detection frequency (fa and fb) is based on time format;

The differential frequency arithmetic element is used to calculate described detection frequency (fa and fb) to produce differential frequency (fd);

Differential frequency rate of change computing unit is used to calculate the rate of change of described differential frequency;

Detect the level input block, be used to import the predetermined detection level;

Comparer is used for the detection level that is input to described detection level input block is compared with the rate of change of described differential frequency; And

Output unit is used for its high level being converted to low level and exporting described low level signal during greater than described detection level when the rate of change of differential frequency described in the described comparer.

4. integrated circuit according to claim 3 (IC), wherein said differential frequency rate of change computing unit comprises:

The reference frequency generation unit is used to produce reference frequency (fr (t)), is expressed as following formula,

If fr (t)=fr (t-1)+m-n is fd (t)-fd (t-1)＞m;

If fr (t)=fr (t-1)+g is 0≤fd (t)-fd (t-1)≤m; And

Fr (t)=fr (t-1)+h, if fd (t)-fd (t-1)＜0,

Wherein t and t-1 represent current period and previous cycle, m 〉=1,0＜n＜m, g 〉=1, h 〉=1, and g＞h respectively; And

Computing unit is used to calculate rate of change (fr (t)-fd (t))/fr (t) of described differential frequency.

5. integrated circuit according to claim 4 (IC), it further comprises:

The reference frequency holding unit is used to keep the reference frequency (fr (t)) of the time that depends on, and described reference frequency results from the described reference frequency generation unit.

6. integrated circuit according to claim 5 (IC), wherein said reference frequency holding unit comprises resistance, thus the retention time of reference frequency (fr (t)) is determined according to the resistance of described resistance.

7. integrated circuit according to claim 3 (IC), wherein said output unit comprises integrator, this integrator is used for the comparative result from described comparer output is carried out integration.

8. integrated circuit according to claim 3 (IC), wherein said detection level input block comprises single external pin, internal reference clock, current source and external capacitive (Cd) are connected to this pin, thereby external capacitive (Cd) can be by described current source charging;

The voltage that wherein said detection level input block is measured described external capacitive (Cd) reaches the time of preset reference voltage (Vth) and selects to detect level according to the coding of determining based on the measured time, thereby imports a plurality of detection level by described single pin.

9. integrated circuit according to claim 3 (IC), it further comprises:

Bifrequency modulator (DFM) unit makes that described bifrequency generating unit increased the generating period of described detection frequency (fa) in the given time when rate of change when described differential frequency was greater than or less than described detection level.

10. integrated circuit according to claim 9 (IC), it further comprises:

The enable signal I/O unit, be configured to from outside input high level the time, enter enabled state, and when input low level, enter waiting status, wherein said enable signal I/O unit produces low level signal and not from outside input low level signal in self, and export described low level signal to outside to communicate in DFM operating period and adjacent elements.

11. integrated circuit according to claim 10 (IC), wherein said bifrequency generating unit is disposed in a large number, generate detection frequency (fa and fb), and the enable signal I/O unit identical with the quantity of described bifrequency generating unit is mounted thereto for a plurality of target capacitances.

12. integrated circuit according to claim 3 (IC), wherein said target capacitance serial or parallel connection be connected to sensitivity adjusting electric capacity, and be connected to described bifrequency generating unit.

13. integrated circuit (IC) chip that comprises the described IC of claim 5 comprises:

Voltage V+ input end;

Voltage V-input end;

Output terminal;

Frequency retention time input end;

Detect the level input end; And

Electric capacity (Cs) input end.

14. integrated circuit (IC) chip that comprises the described IC of claim 10 comprises:

Voltage V+ input end;

Voltage V-input end;

Output terminal;

The I/O end of I/O enable signal;

Detect the level input end; And

Electric capacity (Cs) input end.

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