CN1738206B

CN1738206B - Non-anti-phase dominoes register and method for generating non-anti-phase output

Info

Publication number: CN1738206B
Application number: CN 200510106477
Authority: CN
Inventors: 雷蒙·伯特仁
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2004-12-27
Filing date: 2005-09-26
Publication date: 2010-05-05
Anticipated expiration: 2025-09-26
Also published as: CN1738206A; TW200623634A; TWI281319B

Abstract

A domino bumper includes an arithmetic circuit, a write circuit, an inverter, a keeper circuit, and output logic circuit. The arithmetic circuit pre-charges a first node and operates a logic functionfor controlling a state of the first node when the clock signal goes high. The write circuit drives a second node high if the first node is low and drives the second node low if the first node stays high during operation. The inverter inverts the second node to control the state of a third node. The keeper circuit keeps the second node high while the third node and clock signals are both low and keeps the second node low while the third and first nodes are both high. The high and low paths of the keeper circuit are otherwise disabled, including when the write circuit changes state. Thus, the write circuit does not have to overcome a keeper device.

Description

The method of noninverting domino register and the noninverting output of generation

Technical field

The present invention relates to the field of dynamic logic circuit and buffer function, relate in particular to a kind of noninverting domino (domino) buffer, it can solve speed and be the temporary problem of the output of the complex logic circuit of important factor with size.

Background technology

The application has required U.S. Provisional Application No., and its sequence number is 60/553805, and the applying date is on March 17th, 2004; This application is enclosed in for referencial use.The application of the application's case priority number is 11/023,145 according to U.S. patent application case also, and the date of application is 12/27/2004.

The application is the subsequent application of following U.S. Patent application, and this application and the application have common assignee and at least one common inventor, and this application also is enclosed in also for referencial use.

Sequence number	The applying date	Denomination of invention
Sequence number	The applying date	Denomination of invention	10/640369 (CNTR.2200)	8/13/2003	Noninverting domino register Non-inverting domino register

Integrated circuit has used a large amount of buffers, and especially those have the buffer of lock-in tube line structure.Temporary logical circuit is used for making the output of device and circuit to keep a period of time, so that these outputs can be received with circuit by other device.In frequency system (for example pipeline microprocessor), buffer is used for the output signal of the given pipeline stages circuit of breech lock (latch), and keep simultaneously this output a frequency period during, so that the input circuit in the late-class circuit can receive last output signal when this given pipeline stages circuit produces new output just simultaneously.

In the past, in the complicated logical operation circuit, such as the front and back of multiple input multiplexer (muxes), multidigit encoder etc., often utilize buffer to keep and desire to enter input signal of this computing circuit (evaluationcircuits) and the signal of exporting from this computing circuit.In general, the requirement that these buffers all have related setting-up time and hold time, and these two kinds of requirements all can limit the computing circuit in the front stage circuits.In addition, buffer also has the time response of corresponding data-output (data-to-output), and it can limit the computing circuit in the late-class circuit." speed " judgement of typical case's buffer is the time according to its data-output, and promptly its setting-up time adds upper frequency-output time.

Use traditional cache circuit can produce delay in pipeline system in the front and back of logical operation circuit, the result of its accumulation will cause service speed obviously to be slowed down.More particularly, in these postponed, significant source was for corresponding to the demand of the time of output from data terminal, and it need satisfy logical operation circuit, to guarantee stable temporary output.Therefore, the objective of the invention is to how to reduce these and postpone, so that increase the extra time in each grade circuit, and then promote the speed of whole pipeline system.

At this reference number of a document that can be incorporated herein by reference is that the known of being called of CNTR.2200 " noninverting domino register " and relevant announcement can be handled above-mentioned problem. in this prior art, noninverting domino register is to be stated as the logical operation function to be combined with its corresponding cache device, and can reach than not needing the frequency-output time to the conventional method under the output stability compromise is fast. respond with the slower transition of the noninverting domino register of tradition and compare, in the transition meeting of the output signal of the noninverting domino register that this disclosed transition in response to frenquency signal, yet and be shown as very fast., known noninverting domino register can be not flexible especially for the arithmetic logic circuit, it is necessary for the N channel logic circuit. moreover, when (for example being the 90 Silicon-On-Insulator (silicon-on-insulator of rice (nm) how in high leakage current or strong noise technology, when specifically implementing abbreviation SOI)), known noninverting domino register may produce leakage current effects.

What want to propose is a kind of domino register of improvement, and it can produce all advantages of known noninverting domino register, and can be more flexible for the domino level, and can be used for the environment of high leakage current or strong noise best.

Summary of the invention

According to the noninverting domino register of one embodiment of the invention, comprise domino level circuit, write a grade circuit, inverter, high level and low level and keep path and output-stage circuit.This domino level circuit is in order to carry out a domino level, and this domino level is come the arithmetic logic function based at least one input data signal and a frequency signal.When this frequency signal was low level, this domino level can be a high level with the precharged node preliminary filling, if it carries out computing, then can move this precharged node to low level, and if it can't computing, then can make this precharged node remain on high level.If this precharged node becomes low level, then this writes grade circuit and can move the first preliminary output node to high level, and if this precharged node remains on high level, then it can move this first preliminary output node to low level.This inverter can be anti-phase with this first preliminary output node, and can produce the second preliminary output node.High level is kept the path when activation, and it can make this first preliminary output node remain on high level, and this low level is kept the path when activation, and it can make this first preliminary output node remain on low level.When this frequency signal and this second preliminary output node were low level, this high level is kept the path can activation, otherwise it can not activation.When this second preliminary output node and this precharged node were high level, this low level is kept the path can activation, otherwise it can not activation.This output-stage circuit is in order to carry out an output stage, and this output stage produces an output signal based on the state of this precharged node and this second preliminary output node.

Under the stability compromise that does not need its output, the frequency of this noninverting domino register to output time can be quicker than conventional method.And furthermore, this writes, and grade circuit needn't overcome low level or high level is kept the path, and this first preliminary output node is driven into inverse state.For example, when this frequency signal became high level, if this first preliminary output node is high level, and this domino level circuit can't computing, and then this writes grade circuit and can move, and moves this first preliminary output node to low level.In this case,, and make this high level keep not activation of path, needn't overcome this high level and keep the path so this writes grade circuit, and this first preliminary output node is driven into low level because this frequency signal is a high level.In a specific embodiment, this frequency signal can drive the grid that this high level is kept the P element in channel in the path, and wherein when this frequency signal was high level, this P element in channel can be closed.And furthermore, this inverter can respond this this first preliminary output node and switch to low level, and this second preliminary output node is switched to high level, and make this low level keep the path activation, with during remaining cycle, keep the state of this first preliminary output node and this second preliminary output node.

On the other hand, when this frequency signal becomes high level and this domino level circuit and carries out computing, if this first preliminary output node is a low level, then this writes grade circuit and can move, and move this first preliminary output node to high level. in this case, because this precharged node can become low level, and make this low level keep not activation of path, needn't overcome this low level and keep the path so this writes grade circuit, and this first preliminary output node is driven into high level. in a specific embodiment, this precharged node can drive the grid that this low level is kept the N element in channel in the path, wherein when this precharged node is low level, this N element in channel can be closed. and furthermore, this inverter can respond this first preliminary output node and switch to high level, and this second preliminary output node is switched to low level. in this case, when this frequency signal is high level, this precharged node is a low level, it can make this first preliminary output node remain on high level. when this frequency signal then becomes low level, low level is kept path meeting activation, it can keep the state of this first preliminary output node and this second preliminary output node during remaining cycle.

Overcome the element of keeping element by force with other need and compare, this noninverting domino level circuit can use less and element faster, and be implemented on high leakage current environment in.For example, this noninverting domino level circuit can be compromised and not need under the big element speed not needing, and use can produce 90 how rice silicon-on-insulator (silicon-on-insulator) technology or any other downsizing technologies and integrated of dwindling of high leakage problem.

This domino level circuit can a P element in channel, a N element in channel and arithmetic logic circuit are implemented.This P element in channel has in order to receiving the grid of this frequency signal, and is coupled to drain electrode and source electrode between source voltage and this precharged node.This N element in channel has in order to the grid that receives this frequency signal, the drain electrode that is coupled to this precharged node and source electrode.This arithmetic logic circuit is coupled between the source electrode of earth point and this N element in channel.This configuration makes this arithmetic logic circuit can use complementary metal oxide semiconductor (CMOS) logical circuit to implement.

This writes a grade circuit and comprises a P element in channel, and first and second N element in channel.This P element in channel has the grid that is coupled to this precharged node, and is coupled to drain electrode and source electrode between source voltage and this first preliminary output node.The one N element in channel has in order to the grid that receives this frequency signal, is coupled to the drain electrode and the source electrode of this first preliminary output node.The drain electrode of the source electrode that the 2nd N element in channel has the grid that is coupled to this precharged node, be coupled to a N element in channel and the source electrode that is coupled to earth point.In an embodiment of this configuration, this high level is kept the path and is comprised two extra P element in channel.The 2nd P element in channel has the grid that is coupled to this second preliminary output node, the source electrode that is coupled to source voltage and drain electrode.The 3rd P element in channel has in order to receiving the grid of this frequency signal, and is coupled to the drain electrode of the 2nd P element in channel and drain electrode and the source electrode between this first preliminary output node.In another embodiment of this configuration, this low level is kept the path and is comprised the 2nd N element in channel, and the 3rd N element in channel, wherein the 3rd N element in channel has the grid that is coupled to this second preliminary output node, and is coupled to drain electrode and source electrode between the drain electrode of this first preliminary output node and the 2nd N element in channel.

According to the domino register of one embodiment of the invention, comprise computing circuit, write circuit, inverter, holding circuit and output circuit.When a frequency signal was low level, this computing circuit can preliminary filling first node, and when this frequency signal becomes high level, and it understands the logical function of computing in order to a state of controlling this first node.When this frequency signal became high level, if this first node is a low level, then this write circuit can drive Section Point and be high level, and if this first node remains on high level, then it can drive this Section Point and be low level.This inverter has the input that is coupled to this Section Point, and the output that is coupled to the 3rd node.When the 3rd node and this frequency signal were low level, holding circuit can make this Section Point remain on high level, and when the 3rd node and this first node were high level, it can make this Section Point remain on low level.This output circuit produces an output signal based on the state of this first node and the 3rd node.

This computing circuit comprises a P element in channel, one N element in channel and logical circuit. this arithmetic logic circuit comes this logical function of computing based at least one input data signal. when this frequency signal becomes high level, this N element in channel and this P element in channel all can receive this frequency signal, and can jointly make this logical circuit activation, to control this state of this first node. this P element in channel (it is coupled to this first node), when this frequency signal is low level, it can be a high level with this first node preliminary filling. on the one hand, this logic circuits coupled is to this first node, and this N element in channel is coupled between this logical circuit and the earth point. on the other hand, this N element in channel is coupled to this first node, and this logic circuits coupled is between this N element in channel and earth point. aspect the nothing bottom (footless) of this back, this logical circuit can be implemented by cmos element (rather than N element in channel).

This write circuit comprises a P element in channel, and first and second N element in channel.This P element in channel is coupled to this first node and this Section Point, and when becoming low level as if this first node, it can move this Section Point to high level.The one N element in channel is coupled to this Section Point and in order to receiving this frequency signal, and the 2nd N element in channel is coupled to a N element in channel and this first node.When this frequency signal became high level, if this first node remains on high level, then this first and second N element in channel then can jointly be moved this Section Point to low level.In this case, this holding circuit can comprise the second and the 3rd P element in channel, and the 3rd N element in channel.This second is coupled in the 3rd P element in channel, and can be coupled to this second and the 3rd node, it can form high level state jointly and keep the path, when the 3rd node and this frequency signal are low level, its meeting activation, and this Section Point can be moved to high level, otherwise it can not activation.The 3rd N element in channel is coupled to this second and the 3rd node, and can be coupled to the 2nd N element in channel.This second and the 3rd N element in channel can form low level state jointly and keep the path, when this first and the 3rd node is high level, and its meeting activation, and this Section Point can be moved to low level, otherwise it can not activation.

This computing circuit, write circuit, inverter, holding circuit and output circuit can use 90 rice silicon-on-insulator technologies and integrated how of dwindling as discussed previously.

According to the noninverting domino register of another viewpoint of the present invention, comprise a P element in channel, a N element in channel, arithmetic logic circuit, write a grade circuit, holding circuit and output-stage circuit.This P element in channel has in order to receiving the grid of a frequency signal, and is coupled to drain electrode of one between source voltage and the precharged node and source electrode.This N element in channel has in order to the grid that receives this frequency signal, couples the so far drain electrode and the source electrode of precharged node.This arithmetic logic circuit (it comes computing one logical function based at least one input data signal) is coupled between the source electrode and earth point of this N element in channel, and implements with the CMOS logical circuit.This writes grade circuit in order to driving the first preliminary output node, and comprise all can respond this precharged node first on draw the element and first drop down element, and second drop down element that can respond this frequency signal.This holding circuit has the input that is coupled to the first preliminary output node, and in order to drive the output of the second preliminary output node.This output-stage circuit is in order to driving output node, and comprise all can respond this precharged node second on draw element and the 3rd drop down element, and all can respond the second preliminary output node the 3rd on draw element and the 4th drop down element.This arithmetic logic circuit (being imposed in does not have in the domino level circuit of bottom) is implemented with the CMOS logical circuit, can produce thus than the obvious preferable incoming level noise margin of the well-known configurations that needs the N channel logic circuit.

According to the temporary logical function of one embodiment of the invention and produce the method for noninverting output, comprise when a frequency signal is low level, with the first node preliminary filling is high level, when this frequency signal becomes high level, computing one logical function, state with the control first node, when this frequency signal becomes high level, control the state of Section Point with the state of this first node, the state of the 3rd node is defined as the rp state of this Section Point, when this first node and the 3rd node are high level, can make low level state keep the path activation, to keep the low level state of this Section Point, otherwise can make this low level state keep not activation of path, when this frequency signal and the 3rd node are low level, can make high level state keep the path activation, to keep the high level state of this Section Point, otherwise can make this high level state keep not activation of path, and, decide the state of output node based on the state of this first node and the 3rd node.

This method can comprise when this logical function carries out computing, can move this first node to low level, and when this logical function can't computing, can make this first node remain on high level. this method can comprise when this frequency signal becomes high level, if first node is moved low level to, then can move this Section Point to high level, and if this first node remains on high level, then can move this Section Point to low level. this method can comprise respectively with this first node and the 3rd node, control the first serial connection drop down element and the second serial connection drop down element. this method can comprise respectively with this frequency signal and the 3rd node, control to draw on element and this second serial connection on this first serial connection and draw element. the method can comprise with one with non-(NAND) function, the state of this first node and the 3rd node is carried out in logic combination.

Description of drawings

Benefit of the present invention, characteristic and advantage are consulted the following description, and behind the accompanying drawing, will understand more, wherein:

The sketch plan of the noninverting domino register that Fig. 1 implements for the prior art that is incorporated herein by reference according to meeting;

Figure 2 shows that the sequential chart of the operation of Fig. 1,3,4 and 5 noninverting domino register;

Fig. 3 is the sketch plan of the noninverting domino register of the nothing bottom of being implemented according to one example of the present invention embodiment;

Fig. 4 is the sketch plan according to another the noninverting domino register that one example of the present invention embodiment implemented that uses the storage level circuit that improves; And

The sketch plan of the noninverting domino register of the nothing bottom that Fig. 5 is implemented for the storage level circuit of the improvement of using Fig. 4 and according to one example of the present invention embodiment.

Wherein, description of reference numerals is as follows:

100,300,400,500 noninverting domino registers

101,105 nodes

103 1 groups of N nodes

104,301 arithmetic logic circuit

107 first intermediate output nodes

109A, 109B, 401 inverters

111 second intermediate output nodes

113 output nodes

403 NAND gate

Embodiment

The following explanation that is proposed makes generally to be known this operator and can reach and use the present invention, is provided in the content as specific embodiment and demand thereof.Yet the various modifications that this preferred embodiment is made are apparent for knowing this operator, and, in the General Principle of this opinion, also can be applied to other embodiment.Therefore, the present invention is not limited to this place and shows specific embodiment with narration, but has the maximum magnitude that the principle that place therewith discloses conforms to novel feature.

The present inventor realize be used for logical circuit temporary output for speed, the demand of key factors such as size and stability, it is flexible for the arithmetic logic circuit, and it can be used in high leakage current or the high-noise environment. therefore, it proposes a kind of anti-phase domino register then, it is not under needing the output stability compromise, can have data-output time faster, it is flexible for arithmetic logic circuit device for carrying out said, and it can be used in high leakage current or the high-noise environment, as further specifying in following cooperation Fig. 1 to Fig. 5. highly rely on buffer when using, when in circuit at different levels, transmitting the pipeline structure of data, noninverting domino register according to a specific embodiment of the present invention can make the service speed of all elements that tangible lifting is arranged. and all elements can be compromised to speed not needing, and do not need big element to overcome and keep under the element, use comparatively fast or than small components implementing in high leakage current or the strong noise technology.

Fig. 1 is the sketch plan of the noninverting domino register 100 implemented according to prior art CNTR.2200.Noninverting domino register 100 comprises logical operation input stage circuit (or claiming domino level circuit), and it comprises the P element in channel P1 and the N element in channel N2 of storehouse, and arithmetic logic circuit 104.P1 element and N2 element are complementary paired operand spare, and it is coupled to the either side of the arithmetic logic circuit 104 in the storehouse.Arithmetic logic circuit 104 can be the same simple with single N element in channel, or can be comparatively complicated significantly because of any logical function of wanting of computing.The source electrode of P1 is coupled to a voltage source V DD, and its drain electrode is coupled to the node 105 that can produce signal TOP.Arithmetic logic circuit 104 is coupled between the drain electrode of node 105 and N2 (it has the source electrode that is coupled to earth point).Input frequency signal CLK can be via node 101, and is sent to the grid of P1 and N2.One group of N node 103 can be sent to arithmetic logic circuit 104 with the data-signal DATA of N input, and wherein N is any positive integer.

The domino level circuit of noninverting domino register 100 is the storage level circuit and then, and it comprises element P2, N3 and N4, and weak sustain circuit 109.Element P2, N3 and N4 can be considered " writing a grade circuit ", and holding circuit 109 is grade circuit of keeping in the storage level circuit.Node 101 is coupled to the grid of N3, and node 105 is coupled to the grid of P2 and N4.The source electrode of P2 is coupled to VDD, and its drain electrode is coupled to first intermediate output node 107 that can produce the first intermediate output signal QII.Node 107 is coupled to the drain electrode of N3, the input of inverter 109A and the output of another inverter 109B.The output of inverter 109A is coupled to second intermediate output node 111 that can produce the second intermediate output signal QI, and it is the input that is coupled to

inverter 109B.Inverter

109A and 109B are coupled between

node

107 and 111 mutually, and can form weak sustain circuit 109 jointly.The source electrode of N3 is coupled to the drain electrode of N4 (it has the source electrode that is coupled to earth point).

The storage level circuit of noninverting domino register 100 is extra output-stage circuit and then, and it comprises P element in channel P3 and P4, and N element in channel N5 and N6.Node 105 is coupled to the grid of P4 and N6, and node 111 is coupled to the grid of P3 and N5.The source electrode of P3 and P4 is coupled to VDD, and its drain electrode can be coupled in together at output node 113 places that meeting produces output signal Q.Output node 113 is coupled to the drain electrode of N5 (it has the source electrode that is coupled to N6 (it has the source electrode that is coupled to earth point)).The P element in channel generally can be used for being used as drawing element, and the N element in channel generally can be used for being used as drop down element.

Figure 2 shows that the sequential chart of the operation of noninverting domino register 100, wherein CLK, DATAN, TOP, QII, QI and Q signal are to illustrate out with respect to the time.The relative transition time can be estimated, and can ignore postponing.The DATAN signal is shown as the independent signal of the group combination of representing N DATA signal.When colony's state of data-signal can make arithmetic logic circuit 104 generate, when moving TOP to low level thus, the DATAN signal is shown as high level, and when arithmetic logic circuit 104 can not carry out computing (it can make the TOP signal remain on high level), the DATAN signal was shown as low level.In time T 0, when the CLK signal was initially low level, N2 can close, and P1 meeting conducting, to such an extent as to domino level circuit can be a high level with TOP signal preliminary filling.The TOP signal can preliminary filling be high level, behind the rising edge of CLK, can prepare by arithmetic logic circuit 104, comes computing DATAN signal, and wherein the DATAN signal is initially high level.The TOP signal of preliminary filling can make N4 and N6 conducting.The QII signal can remain on original state (being shown as low logic state at first), and can remain in this by holding circuit 109.The QI signal is initially high level and makes the N5 conducting, to such an extent as to the first meeting of Q output signal is via N5 and N6 element and move low level to.

In time T 1, the CLK signal can become high level, because the DATAN signal is a high level, so it can make the discharge of TOP signal and become low level. in particular, N2 meeting conducting, and arithmetic logic circuit 104 can come computing via N2, and move TOP to low level and earth point .QII signal can be moved high level via P2 to, and Q signal can be moved high level .QII via P4 to and Q signal can be moved high level to simultaneously about time T 1, and QI can move low level to by inverter 109A. the rp state meeting driving element P3 of the QI signal of output place of holding circuit 109 and N5. are when QI is high level, P3 can close, and N5 meeting conducting; And when QI is low level, P3 meeting conducting, and N5 can close. in ensuing time T 2, when the CLK signal then became low level, TOP signal again preliminary filling was that high level .P2 and N3 can close, to such an extent as to yet node 107 can be driven into arbitrary state., the state separately of QII and QI signal can remain unchanged via the operation of holding circuit 109, to such an extent as in all remaining half periods of CLK, Q and QII signal can keep high level, and the QI signal can keep low level.

When the CLK signal still was low level, DATAN was shown as in time T 3 and is transformed into low level, and when the DATAN signal was low level, the CLK signal then can become high level in time T 4.Because arithmetic logic circuit 104 can't carry out computing, to such an extent as to when CLK was high level, TOP still was a high level.CLK and TOP signal can make element N3 and N4 conducting respectively, to such an extent as to when making an appointment T4, the QII signal can transfer low level to, so the QI signal can be moved high level to by inverter 109A.The TOP signal is a high level, and makes N6 keep conducting.The QI signal can make the N5 conducting and P3 is closed, to such an extent as to Q signal can be via N5 and N6 and moved low level to.In time T 5, the CLK signal then can become low level, and makes TOP move high level once more to.The state separately of QII and QI signal can remain unchanged via the operation of holding circuit 109.Because QI can make N5 keep conducting, and TOP can make N6 keep conducting, so in all remaining cycles of CLK, Q signal can keep low level.

When arithmetic logic circuit 104 is estimated, and when making the TOP signal be discharged into low level, Q signal can respond the rising edge of CLK signal, and quite apace from the low level transition to high level.But the negligible delay via element N2 and P4 can cause the output transition.When arithmetic logic circuit 104 can't carry out computing, and when making the TOP signal leave high level, Q signal can respond the rising edge of CLK signal, but and after negligible delay via element N3, N5 and inverter 109A, can be from the high level transition to low level.Delay via inverter 109A can minimize by being embodied as quite little element (having minimum capacity), and this is because it need not have size, also need not carry out the function of buffer.It is common that what know that this operator will recognize is that the transition meeting of the output Q signal of noninverting domino register 100 responds the transition of CLK signal very apace.If need or want noninverting output, then with other benefit and advantage in traditional design compare, noninverting domino register 100 can produce superior data to output speed.100 need of noninverting domino register promptly are convertible into anti-phase domino register by increasing output inverters/buffers (not shown).

Prior art CNTR.2200 institute demonstration example and (AND) logical AND or (OR) logic (not showing) at this, it can be used to be used as arithmetic logic circuit 104.Wherein saidly be, will consider any suitable and with or the combination of gate logic, and will consider any other complicated logical operation circuit, comprise it for example being a plurality of input multiplexers, multidigit encoder or the like.Any want simply can under speed that can influence noninverting domino register 100 or relevant Power Limitation, be used for replacing arithmetic logic circuit 104 to the complex calculations logical circuit sharply.And with or logical circuit be example, and in order to show that arithmetic logic circuit 104 can be as the common any complicated logical operation circuit that this operator understands of knowing.Yet may limiting of noninverting domino register 100 is can be not flexible especially with respect to arithmetic logic circuit 104, and it must be embodied as the N channel logic circuit usually.The N channel logic circuit can not make the input noise margin produce optimizing level.

Fig. 3 is the sketch plan of the another kind of noninverting domino register 300 implemented according to one example of the present invention embodiment. except P element in channel P1 and the N element in channel N2 that comprises storehouse, and the logical operation input stage circuit of arithmetic logic circuit 104, or outside the domino level circuit, noninverting domino register 300 is similar with noninverting domino register 100 in fact, it can be recorded as " not having bottom (footless) " configuration, and arithmetic logic circuit 104 is that to replace .P1 and N2 element with arithmetic logic circuit 301 be complementary paired operand spare, it can be coupled in together at node 105 places that meeting produces the TOP signal. in this case, the drain electrode of N2 is coupled to node 105, and its source electrode is coupled to the top or the upper end of arithmetic logic circuit 301. the below or the bottom end of arithmetic logic circuit 301 are coupled to earth point. in this way, arithmetic logic circuit 301 is if be coupled between P1 and the N2, then it can be positioned at P1/N2 bottom of stack (foot). for noninverting domino register 300, move in fact very similarly, and the sequential chart of Fig. 2 is still same effectively.

Arithmetic logic circuit 301 can be configured in identical with arithmetic logic circuit 104 in fact mode.Yet, as know this operator and understand, arithmetic logic circuit 301 alternately uses CMOS (Complementary Metal Oxide Semiconductor) (CMOS) logical circuit (rather than N channel logic circuit) to implement, moreover the sequential chart of Fig. 2 is still effective.When the CMOS logical circuit is used for domino level circuit, the CMOS logical circuit can produce obviously preferable incoming level noise margin than N channel logic circuit, to such an extent as to noninverting domino register 300 can produce obviously preferable incoming level noise margin than noninverting domino register 100.

In the time of in being implemented on high leakage current or strong noise technology (as 90nm SOI and similar technology),

noninverting domino register

100 and 300 all can experience leakage current effects.Circuit is narrowed down to the problem that 90nm can produce relevant leakage current.Because passage length shortens, so higher leakage current can appear in the technology of dwindling.Therefore, for new state being write any the node 107 of storage level circuit in

relevant buffer

100 and 300, in the back coupling inverter, (for example must overcome weak element, in inverter 109B, weak P element in channel can change over low level state, and weak N element in channel can change over high level state).The cost that overcomes element is speed and electric current.In addition, in the technology that high leakage current or strong noise are arranged, weak N and P element in back coupling inverter 109B must become greatly, with when leakage current or noise occurring, can keep the state of output node.

For example be noted that when CLK was low level, storage node 107 (signal QII) can be isolated with input stage circuit.Except keep feedback inverter 109B (it comprises inner weak N and P element (not shown)), can't drive the QII signal.Yet, owing to the leakage current that increases corresponding to reduction process, relatively large leakage current can flow through P2 and N3 element.So N among the inverter 109B and P element must reach greatly, to overcome leakage current.For example, if the QII signal is high level, then leakage current can flow to ground via N3 and N4 element, to such an extent as to the interior P element of inverter 109B must reach greatly, to supply enough electric currents, overcomes this leakage current, and makes the QII signal remain on high level.High leakage current or high electric current are being arranged, and element is in the technology of closing, needs more and more wide element come hold mode.And, because when writing new state, must overcome the wider element that is just keeping this state, so use the element of broad can reduce usefulness in fact.For the reduction of compensation speed, it is bigger that storage level circuit element P2, N3 and N4 can do, and to drive new state, overcomes by the state of keeping among the back coupling inverter 109B that big element kept.Big element can expend the useful space on the integrated circuit (IC).

Fig. 4 is the sketch plan according to the another kind of noninverting domino register 400 that one example of the present invention embodiment implemented that uses the holding circuit that improves. noninverting domino register 400 comprises input domino level circuit, and then be storage level circuit and output-stage circuit. the domino level circuit in the buffer 400, yet and in the initial part of storage level circuit and the buffer 100 those are similar., the holding circuit of buffer 400 overcomes the demand of element by removal, and with regard to the viewpoint of speed and electric current, reduce cost, can improve usefulness and be modified as. domino level circuit comprises the P element in channel P1 and the N element in channel N2 of storehouse, and arithmetic logic circuit 104. is with the same before, P1 and N2 element are complementary paired operand spare, its source electrode that is coupled to the either side .P1 of the arithmetic logic circuit 104 between voltage source V DD and the earth point is coupled to VDD, and its drain electrode is coupled to the node 105. arithmetic logic circuit 104 that can produce the TOP signal and is coupled between the drain electrode of node 105 and N2, and the source electrode of N2 is coupled to earth point. input frequency signal CLK is sent to P1 via node 101, the grid of N2 and N3. one group of N node 103 can be sent to arithmetic logic circuit 104. with the same before with N input data signal DATA, the node 105 that can produce the TOP signal is coupled to the grid of element P2 and N4. and the initial part of storage level circuit is essentially the identical grade circuit that writes, it comprises the element P2 of storehouse, the source electrode of N3 and N4.P2 is coupled to VDD, and its source electrode is coupled to the drain electrode of the node 107.N3 that can produce the first intermediate output signal QII and is coupled to node 107, and its source electrode is coupled to the drain electrode of N4 (having the source electrode that is coupled to earth point).

The storage level circuit of noninverting domino register 400 comprises and writes a grade circuit (comprising element P3, P4 and P5) and keep a grade circuit (comprising element P3, P4 and N3), and inverter 401.In illustrative embodiment, the storage level circuit is an output-stage circuit and then, it comprise two inputs with non-(NAND) door 403.In this case, the source electrode of P3 is coupled to VDD, and its drain electrode is coupled to the source electrode of P4 (its drain electrode is coupled to the drain electrode of the N5 at node 107 places).The source electrode of N5 is coupled to the drain electrode of N4, further can be coupled to the source electrode of N3.The node 101 that can produce the CLK signal is coupled to the grid of P4.The node 107 that can produce the QII signal is coupled to the input of inverter 401 (its output is coupled to the node 111 that can produce the second intermediate output signal QI).Node 111 is coupled to the grid of P3 and N5, and is coupled to an input of NAND gate 403.The node 105 that can produce the TOP signal is coupled to another input of NAND gate 403, and the output of NAND gate 403 can produce the output Q signal.

Have only for sequential in this situation of fine difference, the sequential chart of Fig. 2 can be applicable to noninverting domino register 400, wherein can ignore such time sequence difference and small delay (for example, can ignore the delay of process inverter 401 and NAND gate 403).Moreover, can suppose that the QII signal is initially low level, and can activation be high level.With reference to figure 2, in time T 0, CLK, Q and QII signal are initially low level, and the QI signal is a high level.Because CLK is a low level, thus P1 meeting conducting, and TOP can preliminary filling be a high level, and make the N4 conducting.Because QI and TOP are high level, so the Q signal of output place of NAND gate 403 is initially low level.When CLK is low level and QI when being high level, N5 can conducting, and P3 can close, and P4 can conducting.Therefore, in this case, N5 and N4 all be positioned at provide node 107 to " low level " state of earth point keep the path on, it can make the QII signal remain on low level.When the second preliminary output node 111 and precharged node 105 were high level, the low path of keeping can activation, otherwise can not activation.

When in time T 1, when the CLK signal became high level, N2 can conducting, and can start the computing of DATA operand by arithmetic logic circuit 104.With preceding the same, the first meeting of the DADAN signal of representative input DATA operand is shown as high level, and makes arithmetic logic circuit 104 be couple to node 105, and is coupled to the drain electrode of N2.This can make the TOP signal move low level to via N2.(at short postpone back through NAND gate 403) becomes low level TOP and can make NAND gate 403 conductings when making an appointment T1, is high level and make the Q activation.Moreover, become low level TOP N4 is closed, can make thus from N5, through N4, and down keep not activation of path to the low level of earth point.And, become low level TOP and can make the P2 conducting, to such an extent as to when making an appointment T1, the QII signal can be moved high level to.When in time T 1, when the QII signal became high level, inverter 301 can be moved the QI signal to low level, and it can make the P3 conducting, and N5 is closed.When the QI signal was low level, the Q output signal can remain on low level.

In this example, when the TOP signal becomes low level, because N4 can close, can not activation so keep the path through the low level of N5.And,,, and make the QII signal move high level to so P2 needn't overcome N5 because N4 can close.Whenever the QII signal is a low level, and can respond computing (making TOP move low level to) and when moving high level to, low level is kept the path always can not activation (because N4 can close), to such an extent as to writing grade circuit and needn't overcome and keep element in the storage level circuit.

In time T 2, when CLK then becomes low level, TOP again preliminary filling is a high level. moreover, in time T 2, P4 meeting conducting, and produce from node 107, keep the path via P4 and P3 to " high level " state of VDD, can make the QII signal remain on high level thus. when precharged node 105 and the second preliminary output node 111 are low level, high level is kept path meeting activation, otherwise can not activation. therefore, when in time T 2, when TOP becomes high level, the QII signal can remain on high level, it can make QI remain on low level successively, to keep the state of Q output signal. and at the T2 that makes an appointment, the TOP signal that becomes high level can make the N4 conducting, but because the QI signal is a low level, so N5 can close, during remaining cycle, can make low level keep the path and keep closing or not activation thus.

In time T 3, the DATAN signal can become low level, and in time T 4, the CLK signal then can become high level, and the DATAN signal still is a low level, to such an extent as to arithmetic logic circuit 104 can not carry out computing.Therefore, in time T 4, TOP can remain on high level, to such an extent as to N4 can keep conducting.The CLK signal that becomes high level can make P4 close, and can make the N3 conducting.Because P4 can close, and N3 and N4 all can move the QII signal to low level, so can not activation from the high maintenance path of node 107 to VDD.Because P4 can close,, and can make QII move low level to so N3 and N4 needn't overcome any element (comprising the weak sustain element).Whenever the QII signal is a high level, and can respond can't computing (wherein TOP can remain on high level) and when moving low level to, high level is kept the path always can not activation (because P4 can close), to such an extent as to writing grade circuit and needn't overcome and keep element in the storage level circuit.At the T4 that makes an appointment, inverter 401 can become low level by response QII, and can move QI to high level.Because QI and TOP are high level, so at the T4 that makes an appointment, NAND gate 403 can be moved Q to low level.Moreover the QI that becomes high level can make the N5 conducting, and P3 is closed, to such an extent as to high level keep the path can not activation, and keep path activation again through the low level of N5 and N4.When CLK in time T 5, when then becoming low level, N3 can close, and because N5 and N4 can keep conducting, so QII can keep the path and remain on low level through low level.TOP and QI are and remain on high level, to such an extent as at all the other frequency periods of CLK, Q can remain on low level.

Noninverting domino register 400 is to use the technology of improvement, makes the not activation of weak sustain feedback element, to such an extent as to when just writing new state, needn't overcome the strong element of keeping element internal.Therefore, the broad that P3 and N5 element can be done overcomes leakage current, and with hold mode, but because when new state being write storage node 107 (QII signal), those similar elements P3 and N5 can not activations, so can not influence speed.When writing the new state of QII signal, needn't overcome the back coupling holding circuit, to such an extent as to element P2 and N3 can be the element of normal size." maintainer " of noninverting domino register 400 only can activation be used for storing this state.In particular, feedback element can activation, and keeping this state, and when write new state, it understands not activation.

Fig. 5 uses the improvement of buffer 400 to keep a grade circuit, and the sketch plan that does not have the noninverting domino register 500 in bottom according to the another kind that another example of the present invention embodiment is implemented.Except P element in channel P1 and the N element in channel N2 that comprises storehouse, and the logical operation input stage circuit of arithmetic logic circuit 104, or outside the domino level circuit, noninverting domino register 500 is similar with noninverting domino register 400 in fact, it can be recorded as " not having the bottom " configuration, and arithmetic logic circuit 104 replaces with arithmetic logic circuit 301.From the change of buffer 500 to 400 are the changes that are similar to from buffer 300 to 100.In this way, the arithmetic logic circuit 301 of noninverting domino register 500 can the CMOS logical circuit rather than the N channel logic circuit implement, moreover the sequential chart of Fig. 2 is still available.As described above, when the CMOS logical circuit is used for domino level circuit, the CMOS logical circuit can produce obviously preferable incoming level noise margin than N channel logic circuit, to such an extent as to noninverting domino register 500 can produce preferable a little incoming level noise margin than noninverting domino register 400.

Under not needing the stability of its output Q compromised, frequency to the output time of the noninverting domino register of implementing according to one embodiment of the invention can be quicker than conventional method.In addition, overcome the element of keeping element by force with other need and compare, the storage level circuit can improve further, and makes lessly, and very fast element can be used among the high leakage current environment.Noninverting domino register is implemented in high leakage current or the strong noise technology (as 90nm SOI and similar technology), and can cause usefulness to reduce because of the leakage current factor.Therefore, the advantage of reduction process (comprise and reduce size, voltage, power consumption etc.) can not cause usefulness to reach under reducing corresponding to such reduction process.

Though the present invention and purpose thereof, characteristic and advantage are described in detail, yet the present invention also may also comprise other execution mode and variation.In addition, though disclosed execution mode is that (it comprises CMOS (Complementary Metal Oxide Semiconductor) (CMOS) and similar elements to the element that utilizes metal-oxide-semiconductor (MOS) (MOS) kenel, as NMOS and PMOS transistor etc.), yet it still can utilize the technology kenel and the structure of similar aspect or simulation to implement, for example dual-polarity elements or the like.At last, though the present invention is for realizing the optimal mode of purpose of the present invention, yet what know that this operator should recognize is, it is not breaking away under defined spirit of the present invention of appended claim and the scope, it can use the notion and the particular specific embodiment that are disclosed to be used as the basis immediately, carries out the design identical with purpose of the present invention or is modified as other structure.

Claims

1. noninverting domino register comprises:

One domino level circuit, in order to carry out a domino level, this domino level is based at least one input data signal and a frequency signal, come computing one logical function, wherein when this frequency signal was low level, this domino level can be a high level with a precharged node preliminary filling, if it carries out computing, then can move this precharged node to low level, and, then can make this precharged node remain on high level if it can't computing;

One writes a grade circuit, be coupled to this domino level circuit and write level to carry out one, this writes level and can respond this frequency signal, if this precharged node becomes low level, then it can move one first preliminary output node to high level, and if this precharged node remains on high level, then it can move this first preliminary output node to low level;

One inverter has an input that is coupled to this first preliminary output node, and an output that is coupled to one second preliminary output node;

One high level is kept the path, and when activation, it can make this first preliminary output node remain on high level, and wherein when this frequency signal and this second preliminary output node are low level, this high level is kept the path can activation, otherwise it can not activation;

One low level is kept the path, and when activation, it can make this first preliminary output node remain on low level, and wherein when this second preliminary output node and this precharged node are high level, this low level is kept the path can activation, otherwise it can not activation; And

One output-stage circuit, in order to carry out an output stage, this output stage produces an output signal based on the state of this precharged node and this second preliminary output node.

2. noninverting domino register as claimed in claim 1, wherein this domino level circuit comprises:

One P element in channel has in order to receiving a grid of this frequency signal, and is coupled to drain electrode of one between one source pole voltage and this precharged node and source electrode;

The arithmetic logic circuit is coupled to this precharged node; And

One N element in channel has in order to receiving a grid of this frequency signal, and is coupled to drain electrode of one between this arithmetic logic circuit and the earth point and source electrode.

3. noninverting domino register as claimed in claim 1, wherein this domino level circuit comprises:

One N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this precharged node; And

The arithmetic logic circuit is coupled between this source electrode of earth point and this N element in channel.

4. noninverting domino register as claimed in claim 1, wherein this writes a grade circuit and comprises:

One the one P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between one source pole voltage and this first preliminary output node and source electrode;

One the one N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this first preliminary output node; And

One the 2nd N element in channel, a drain electrode of this source electrode that have the grid that is coupled to this precharged node, is coupled to a N element in channel and the one source pole that is coupled to earth point.

5. noninverting domino register as claimed in claim 4, wherein this high level is kept the path and is comprised:

One the 2nd P element in channel has a grid that is coupled to this second preliminary output node, the one source pole that is coupled to this source voltage and a drain electrode; And

One the 3rd P element in channel has in order to receiving a grid of this frequency signal, and is coupled to this drain electrode of the 2nd P element in channel and a drain electrode and the source electrode between this first preliminary output node.

6. noninverting domino register as claimed in claim 5, wherein this low level is kept the path and is comprised the 2nd N element in channel, and one the 3rd N element in channel, it has a grid that is coupled to this second preliminary output node, and is coupled to a drain electrode and the source electrode between this drain electrode of this first preliminary output node and the 2nd N element in channel.

7. domino register comprises:

One computing circuit, when a frequency signal is low level, its can preliminary filling one first node, and when this frequency signal becomes high level, it understands the logical function of computing in order to a state of controlling this first node;

One write circuit, be coupled to this first node and in order to receive this frequency signal, when this frequency signal becomes high level, if this first node is a low level, then it can drive a Section Point and be high level, and if this first node remains on high level, then it can drive this Section Point and be low level;

One inverter has an input that is coupled to this Section Point, and an output that is coupled to one the 3rd node;

One keeps circuit, be coupled to this Section Point and the 3rd node, and this write circuit, when the 3rd node and this frequency signal are low level, it can make this Section Point remain on high level, and when the 3rd node and this first node were high level, it can make this Section Point remain on low level; And

One output circuit, it produces an output signal based on the state of this first node and the 3rd node.

8. domino register as claimed in claim 7, wherein this computing circuit comprises:

One P element in channel is coupled to this first node and in order to receive this frequency signal, when this frequency signal was low level, it can be a high level with this first node preliminary filling;

One logical circuit is coupled to this first node, and it comes this logical function of computing based at least one input data signal; And

One N element in channel is coupled between this logical circuit and the earth point, and in order to receive this frequency signal;

Wherein when this frequency signal became high level, this P element in channel and this N element in channel can jointly make this logical circuit activation, to control this state of this first node.

9. domino register as claimed in claim 7, wherein this computing circuit comprises:

One N element in channel is coupled to this first node, and in order to receive this frequency signal; And

One logical circuit is coupled between this N element in channel and the earth point, and it comes this logical function of computing based at least one input data signal;

10. domino register as claimed in claim 7, wherein this write circuit comprises:

One the one P element in channel is coupled to this first node and this Section Point, and when becoming low level as if this first node, it can move this Section Point to high level;

One the one N element in channel is coupled to this Section Point and in order to receive this frequency signal; And

One the 2nd N element in channel is coupled to a N element in channel and this first node;

Wherein a N element in channel and the 2nd N element in channel can respond this frequency signal and become high level, if this first node still is a high level, then can jointly move this Section Point to low level.

11. domino register as claimed in claim 7, wherein this holding circuit comprises:

The second and the 3rd P element in channel, be coupled in together, and can be coupled to this Section Point and the 3rd node, it can form a high level state jointly and keep the path, when the 3rd node and this frequency signal are low level, its meeting activation, and this Section Point can be moved to high level, otherwise its not activation of meeting; And

One the 3rd N element in channel, be coupled to this Section Point and the 3rd node, and can be coupled to the 2nd N element in channel, wherein the 2nd N element in channel and the 3rd N element in channel can form a low level state jointly and keep the path, when this first node and the 3rd node are high level, its meeting activation, and this Section Point can be moved to low level, otherwise it can not activation.

12. a noninverting domino register comprises:

One the one P element in channel has in order to receiving a grid of a frequency signal, and is coupled to drain electrode of one between an one source pole voltage and the precharged node and source electrode;

One the one N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this precharged node;

The arithmetic logic circuit is coupled between this source electrode and earth point of a N element in channel, and comprises complementary MOS integrated circuit, and it comes computing one logical function based at least one input data signal;

One writes a grade circuit, write level and drive one first preliminary output node in order to carry out one, this write grade comprise all can respond this precharged node one first on draw element and one first drop down element, and one second drop down element that can respond this frequency signal;

One keeps circuit, has an input that is coupled to this first preliminary output node, and in order to drive an output of one second preliminary output node; And

One output-stage circuit, in order to carry out an output stage and to drive an output node, this output stage comprise all can respond this precharged node one second on draw element and one the 3rd drop down element, and all can respond this second preliminary output node one the 3rd on draw element and one the 4th drop down element.

13. noninverting domino register as claimed in claim 12, wherein this writes a grade circuit and comprises:

One the 2nd P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between this source voltage and this first preliminary output node and source electrode;

One the 2nd N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this first preliminary output node; And

One the 3rd N element in channel, a drain electrode of this source electrode that have the grid that is coupled to this precharged node, is coupled to the 2nd N element in channel and the one source pole that is coupled to earth point.

14. noninverting domino register as claimed in claim 13, wherein this holding circuit comprises the pair of phase inverters that is coupled to mutually between this first preliminary output node and this second preliminary output node.

15. noninverting domino register as claimed in claim 12, wherein this output-stage circuit comprises:

One the 2nd P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between this source voltage and this output node and source electrode;

One the 3rd P element in channel has a grid that is coupled to this second preliminary output node, a drain electrode that is coupled to the one source pole of this source voltage and is coupled to this output node;

One the 2nd N element in channel has a grid that is coupled to this second preliminary output node, a drain electrode and an one source pole that is coupled to this output node; And

16. a temporary logical function and produce the method for noninverting output comprises:

When a frequency signal is low level, be high level with a first node preliminary filling;

When this frequency signal became high level, computing one logical function was to control the state of this first node;

When this frequency signal becomes high level, control the state of a Section Point with the state of this first node;

The state of one the 3rd node is defined as the rp state of this Section Point;

When this first node and the 3rd node are high level, can make a low level state keep the path activation, keeping the low level state of this Section Point, otherwise can make this low level state keep not activation of path;

When this frequency signal and the 3rd node are low level, can make a high level state keep the path activation, keeping the high level state of this Section Point, otherwise can make this high level state keep not activation of path; And

Based on the state of this first node and the 3rd node, decide the state of an output node.

17. method as claimed in claim 16, wherein this computing one logical function comprises when this logical function carries out computing with the state of controlling this first node, can move this first node to low level, and when this logical function can't computing, can make this first node remain on high level.

18. method as claimed in claim 17, wherein this state of controlling this Section Point with the state of this first node comprises when this frequency signal becomes high level, if this first node is moved low level to, then can move this Section Point to high level, and, then can move this Section Point to low level if this first node remains on high level.

19. method as claimed in claim 16, wherein this can make a low level state keep the path activation, comprise respectively with this first node and the 3rd node otherwise can make this low level state keep not activation of path, control the first serial connection drop down element and the second serial connection drop down element.

20. method as claimed in claim 16, wherein this can make a high level state keep the path activation, comprise respectively with this frequency signal and the 3rd node otherwise can make this high level state keep not activation of path, control to draw on first serial connection on the element and second serial connection and draw element.

21. method as claimed in claim 16, wherein this determines the state of an output node to comprise with a NAND function, and the state of this first node and the 3rd node is carried out in logic combination.