CN1734747A - Titanium silicide realization method in CMOS process by means of titanium deposition at normal temperature - Google Patents
Titanium silicide realization method in CMOS process by means of titanium deposition at normal temperature Download PDFInfo
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- CN1734747A CN1734747A CN 200410053733 CN200410053733A CN1734747A CN 1734747 A CN1734747 A CN 1734747A CN 200410053733 CN200410053733 CN 200410053733 CN 200410053733 A CN200410053733 A CN 200410053733A CN 1734747 A CN1734747 A CN 1734747A
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Abstract
The invention relates to realization method for the titanium silicide in CMOS technique, which comprises, first, injecting amorphous compound on CMOS with formed source/drain/grid; then, sputtering to deposit titan at normal temperature for CMOS and adding the sputter and deposit for titanium nitride; annealing quickly for the first time; wet etching by NH4OH/H2O2/H2O; finally, annealing quickly for the second time to form titanium silicide. This method restrains effectively the narrow channel effect, saves time and cost.
Description
Technical field
The implementation method of titanium silicide in CMOS technology of the relevant a kind of deposit titanium of the present invention, the especially a kind of implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium.
Background technology
In the deep-submicron semiconductor technology, live width, contact area and connect face degree of depth etc. and all dwindle gradually, in order to improve the operating efficiency of integrated circuit effectively, reduce resistance and reduce resistance and signal propagation delay that electric capacity (RC) is caused, the application of titanium silicide alloy (metal silicides) is more and more general.
The technology of Silicide (silicide) is after forming grid and source leakage diffusion region, deposit layer of metal in the mode of sputtering sedimentation (sputtering deposition) and (be generally Ti, Co or Ni), handle through short annealing for the first time (lst RTA), make metal and pasc reaction become metal silicide, and the metal on insulating barrier (nitride or oxide) can not form silicide with the insulating barrier reaction, so this process is the autoregistration process.Afterwards, utilize a selectivity wet etching (the general mixed solution of visiting with NH4OH/H2O2/H2O or H2SO4/H2O2) to remove the metal part that unreacted becomes silicide again, stay the silicide that is formed on grid, source and drain surface.Carry out a RTA again and handle the requirement that the further reduction of resistance that makes silicide has reached product.
Along with the live width of device reduces, for titanium silicide, understand some problem and produce, cause the bottleneck of its development.(sheet resistance can increase square resistance after live width is dwindled, and this phenomenon is called (narrow-line-width effect).The mechanism of this phenomenon is complicated, issue after examination and approval now factually, after line widths shrink or the attenuation of silicide thickness, change the process need of C-54 phase place time more of a specified duration or higher temperature at titanium silicide C-49, but contradiction is less live width or thin TiSi2 thermal stability variation.The silicide that forms is the structure of polycrystalline shape (polycrystalline), when too high or high-temperature process time is long slightly when temperature, the phenomenon of agglomerateization (agglomeration) will take place in thin-film material, just silicide can become the dough that a piece does not link, and causes the rising of square resistance.By the above-mentioned reason of what, Tisilicide technology becomes especially difficult in the deep-submicron semiconductor technology.Temperature T 1 is to make TiSi2 be converted to the lowest temperature of C54, and T2 for avoiding the temperature upper limit (supposing that the RTA time is certain) of agglomeration, is process window (process window) between T1 and the T2 then.Live width dwindle or the silicide attenuation after, T1 can rise and T2 descends, and causes narrowing even vanishing from sight of process window.Therefore, when the semiconductor technology size constantly reduces, the selection of metal silicide has been transferred to Co and Ni from Ti, but titanium silicide has cost low, the characteristics that processing compatibility is strong, if can improve narrow-channel effect (Narrow-line-width effect) phenomenon, titanizing silicon is very huge in the application space of deep-submicron.
In order to suppress Narrow-line-width effect phenomenon, can be before silicide process in addition before one decrystallized injection (pre-amorphization implant PAI), generally uses heavy ion, (as As+, Ge+).Discover that also (~ 400 ℃) collocation PAI can obtain better result.Decrystallized meeting diminishes the grain size (crystallite dimension) of TiSi2, point out by researching and analysing, dwindling grain size can reduce C-49 and be converted to the required temperature of the process of C-54 or shorten its time, amplified process window (because T1 reduce) in the equivalence but the sputtering deposit temperature of amorphisation and raising Ti causes the defective of the face of connecing (junction) easily when CMOS technology, can increase the leakage current of shallow junction, and other bad influence.
Summary of the invention
The defective in the prior art for a change, the object of the present invention is to provide a kind of implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium, the narrow-channel effect that suppresses contact resistance effectively, and the low cost of maintenance titanium silicide, the advantage that processing compatibility is strong.
In order to realize goal of the invention of the present invention, the implementation method of titanium silicide in CMOS technology of a kind of normal temperature deposit titanium of the present invention is characterized in that may further comprise the steps:
Preceding decrystallized injection, decrystallized injection before on the CMOS that has formed source/leakage/grid, carrying out;
Normal temperature sputtering deposit titanium passes through common deposition process at ambient temperature to above-mentioned CMOS sputtering deposit titanium;
Short annealing for the first time makes titanium and pasc reaction become titanizing silicon;
The selectivity wet etching is removed unreacted titanium;
Short annealing for the second time forms stable titanium silicide at source/leakage/grid.
Because adopt technique scheme, the present invention suppresses the narrow-channel effect of contact resistance effectively, and keep the low cost of titanium silicide, the advantage that processing compatibility is strong, and the element electric leakage is greatly improved, has improved production capacity simultaneously, save time and cost.
The accompanying drawing simple declaration
Fig. 1 is the flow chart of one embodiment of the present of invention.
Fig. 2 is along with the situation of change schematic diagram of the variation square resistance of live width in one embodiment of the present of invention.
Fig. 3 is the comparison schematic diagram of the silicide of high-temperature deposition method in one embodiment of the present of invention and the traditional handicraft in P type active area junction leakage situation, the electric leakage situation of the device made of the curve representation traditional handicraft method of top wherein, the curve of below then represent to use the electric leakage situation of the device that process of the present invention makes.
Fig. 4 is the comparison schematic diagram of the silicide of high-temperature deposition method in one embodiment of the present of invention and the traditional handicraft at P type active area STI (shallow-trench isolation) edge current leakage, and wherein top curve is represented high temperature process, and lower curve is represented method of the present invention.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
Consult shown in Figure 1ly, it is the flow chart of one embodiment of the present of invention, a kind of implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium, and described CMOS is the logic product of 0.25 micron technology, it is characterized in that may further comprise the steps:
Preceding decrystallized injection, decrystallized injection before on the CMOS that has formed source/leakage/grid, carrying out, utilize As+ to inject, As+ dosage is 3e14atom/cm3, makes to form the regional decrystallized of titanium silicide, its energy forms follow-up titanium silicide and has a significant impact, not changing device property simultaneously, optimize its energy, make it form the most favourable to titanium silicide, if use the Ge+ ion to inject simultaneously, also can reach ideal effect;
Normal temperature sputtering deposit titanium is 300A deposit titanium by common deposition process to above-mentioned CMOS sputtering deposit thickness under 25 ℃ of conditions of room temperature; Append the sputtering deposit that carries out titanium nitride under the normal temperature then, the thickness of the titanium nitride of formation is 100A;
Short annealing for the first time makes titanium and pasc reaction become titanizing silicon, and the temperature of rapid thermal annealing is 710 ℃, and the time is 30 seconds;
The selectivity wet etching is removed unreacted titanium, and the chemical liquid of employing is NH4OH/H2O2/H2O, and temperature is 25 ℃, and the time is 40 minutes;
Short annealing for the second time forms stable titanium silicide at source/leakage/grid, and the temperature of rapid thermal annealing is 850 ℃ for the second time, and the time is 30 seconds.
In above-mentioned treatment step, be 0.25 micron radio frequency products as fruit product, then the thickness of deposit titanium is 350A in above-mentioned steps, and the thickness of titanium nitride is 100A.
The device of making through method of the present invention has suppressed narrow-channel effect effectively, sees also shown in Figure 2ly, and along with constantly reducing of live width, the resulting square resistance of normal temperature titanium sputtering deposit titanium silicide changes little, and narrow-channel effect effectively suppresses.Effectively reduced the electric leakage of P type device, see also Fig. 3 and shown in Figure 4, for the electric leakage of P type device, no matter be from the order of magnitude or from distribution, the normal temperature sputtering sedimentation titanium formation titanium silicide of the curve of below representative is greatly improved than the high temperature titanium sputtering deposit titanium silicide of top curve representative.In addition, the present invention has also improved usage ratio of equipment, has saved time and cost.Titanium silicide technology is the necessary technology that sophisticated semiconductor is produced, and use the equipment of high-temperature deposition titanium to have only two usually on the production line, and the equipment of normal temperature has tens, uses method of the present invention, and its production capacity is than nearly ten times of former technology height.And what original technology was used is deposition process, needs to collimate sieve, and these parts are consumptive materials, and cleaning or changing needs several ten thousand to arrive the expense of hundreds of thousands dollar and also have valuable time.New technology does not then need these parts, has saved the cost and the time of this technology greatly.
Claims (9)
1, a kind of implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium is characterized in that may further comprise the steps:
Preceding decrystallized injection, decrystallized injection before on the CMOS that has formed source/leakage/grid, carrying out;
Normal temperature sputtering deposit titanium passes through common deposition process at ambient temperature to above-mentioned CMOS sputtering deposit titanium;
Short annealing for the first time makes titanium and pasc reaction become titanizing silicon;
The selectivity wet etching is removed unreacted titanium;
Short annealing for the second time forms stable titanium silicide at source/leakage/grid.
2, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 1 is characterized in that: after normal temperature sputtering deposit titanium, append the sputtering deposit that carries out titanium nitride under the normal temperature then.
3, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 2, it is characterized in that: the thickness of deposit titanium is 300A, and the thickness of titanium nitride is 100A.
4, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 2, it is characterized in that: the thickness of deposit titanium is 350A, and the thickness of titanium nitride is 100A.
5, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 1 is characterized in that: adopt heavy ion to inject during preceding decrystallized injection, heavy ion is As+ or Ge+.
6, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 1 is characterized in that: described first time, the temperature of rapid thermal annealing was 710-740 ℃, and the time is 30 ± 5 seconds.
7, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 1 is characterized in that: the chemical liquid that adopts during described selectivity wet etching is NH4OH/H2O2/H2O.
8, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 7 is characterized in that: the temperature during described selectivity wet etching is 25 ℃, and the time is 40 minutes.
9, the implementation method of titanium silicide in CMOS technology of normal temperature deposit titanium as claimed in claim 1, it is characterized in that: the temperature of described normal temperature sputtering deposit titanium is 25 ℃.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184845A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for enhancing on-chip uniformity of titanium silicide square resistor |
| WO2012041056A1 (en) * | 2010-09-29 | 2012-04-05 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103177949A (en) * | 2011-12-23 | 2013-06-26 | 上海华虹Nec电子有限公司 | Forming method of metal silicide gate |
| CN103412423A (en) * | 2013-08-27 | 2013-11-27 | 江西合力泰科技股份有限公司 | Low temperature process for printing titanizing silicon |
| CN105810574A (en) * | 2015-01-20 | 2016-07-27 | 国际商业机器公司 | Metal-insulator-semiconductor (MIS) contacts |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081034A (en) * | 1992-06-12 | 2000-06-27 | Micron Technology, Inc. | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer |
| JPH0722606A (en) * | 1993-06-23 | 1995-01-24 | Nippondenso Co Ltd | Manufacture of semiconductor device |
| JP3033526B2 (en) * | 1997-06-13 | 2000-04-17 | 日本電気株式会社 | Method for manufacturing semiconductor device |
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2004
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012041056A1 (en) * | 2010-09-29 | 2012-04-05 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102437088A (en) * | 2010-09-29 | 2012-05-02 | 中国科学院微电子研究所 | Semiconductor structure and manufacture method thereof |
| US8541280B2 (en) | 2010-09-29 | 2013-09-24 | The Institute Of Microelectronics, Chinese Academy Of Sciences | Semiconductor structure and method for manufacturing the same |
| CN102437088B (en) * | 2010-09-29 | 2014-01-01 | 中国科学院微电子研究所 | Semiconductor structure and manufacture method thereof |
| CN102184845A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for enhancing on-chip uniformity of titanium silicide square resistor |
| CN103177949A (en) * | 2011-12-23 | 2013-06-26 | 上海华虹Nec电子有限公司 | Forming method of metal silicide gate |
| CN103412423A (en) * | 2013-08-27 | 2013-11-27 | 江西合力泰科技股份有限公司 | Low temperature process for printing titanizing silicon |
| CN103412423B (en) * | 2013-08-27 | 2016-05-11 | 江西合力泰科技有限公司 | A kind of technique of low temperature printing titanizing silicon |
| CN105810574A (en) * | 2015-01-20 | 2016-07-27 | 国际商业机器公司 | Metal-insulator-semiconductor (MIS) contacts |
| CN105810574B (en) * | 2015-01-20 | 2018-09-14 | 国际商业机器公司 | Metal-insulator semiconductor (MIS)（MIS）Contact and forming method thereof and transistor |
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| CN100353523C (en) | 2007-12-05 |
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Effective date of registration: 20171214 Address after: Zuchongzhi road 201203 Shanghai Pudong New Area Zhangjiang High Tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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