CN1729578A - Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same - Google Patents

Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same Download PDF

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CN1729578A
CN1729578A CNA2003801069396A CN200380106939A CN1729578A CN 1729578 A CN1729578 A CN 1729578A CN A2003801069396 A CNA2003801069396 A CN A2003801069396A CN 200380106939 A CN200380106939 A CN 200380106939A CN 1729578 A CN1729578 A CN 1729578A
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groove
epitaxial loayer
dopant
conductivity type
drain
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CN100508210C (en
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默罕穆德·N·达维什
凯尔·W·特里尔
祁建海
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HILICONICS CO Ltd
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HILICONICS CO Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional ''drift region'' that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The N-epitaxial layer increases the breakdown voltage of the MIS device.

Description

Have trench metal-insulator-semiconductor device and the manufacture method thereof of injecting drain-drift region and thick bottom oxide
The application is that the part of the 10/326th, No. 311 application continues, and the 10/326th, the part that No. 311 applications are following applications continues: in the 10/317th of submission on December 12nd, 2002, No. 568 applications, it is the part continuation in the 09/898th, No. 652 application of submission on July 3 calendar year 2001; The 10/176th, No. 570 application of submitting on June 21st, 2002; With the 10/106th, No. 812 application of submitting on March 26th, 2002, this application then is that the part of the 09/927th, No. 143 application continues.Above-mentioned each application is all introduced in full with as a reference.
Technical field
The present invention relates to a kind ofly have the remarkable ON resistance and the groove grid-control power MOSFET (trench-gated power MOSFET) of breakdown characteristics, and the invention particularly relates to a kind of groove MOSFET of suitable high frequency operation.The invention still further relates to the method for making such MOSFET.
Background technology
Some metal-insulator semiconductor (MIS) device comprises the grid that is positioned at groove, and this groove extends downwards from the surface of Semiconductor substrate (for example, silicon).Electric current in such device mainly is vertical, and therefore, the unit can more closely be arranged.At other under all identical situations, the ON resistance that this has increased current carrying capacity and has reduced device.The device that is included in this type of MIS device comprises metal-oxide semiconductor fieldeffect transistor (MOSFET), insulated gate bipolar transistor (IGBT) and mos gate control thyristor.
Groove MOSFET for example, can be used high transconductance (g M, max) and low specific-on resistance (R On) make, this linear signal for the best amplifies and switches is important.But one of sixty-four dollar question is the internal capacitance that reduces MOSFET for the high frequency operation.Internal capacitance comprises that grid is to capacitance of drain (C Gd), input capacitance (C Iss) and output capacitance (C Oss), C GdBe also referred to as feedback capacity (C Rss).
Fig. 1 is the cross-sectional view of traditional n type groove MOSFET 10.Among the MOSFET10, n type extension (" N-epi ") layer 14 grows in N +On the substrate 12.N-epi layer 14 can be lightly-doped layer, that is, and and N -Layer.This tagma 16 of P type is with N-epi layer 14 and N +Source area 18 separately.Electric current vertically flows through raceway groove (by the dotted line indication) along the sidewall of groove 20.The bottom of groove 20 and sidewall are lined with thin gate insulator 22 (for example, silicon dioxide).Groove 20 usefulness electric conducting materials are filled, and such as the polysilicon that mixes, it forms grid 24.Groove 20 usefulness insulating barriers 26 comprising grid 24 cover, and insulating barrier 26 can be boron phosphorus silicate glass (BPSG).With electrically contacting of conductor 28 formation that are generally metal or metal alloy and source area 18 and this tagma 16.The ohmic contact that body contact zone 30 promotes between metal 28 and the P body 16.Grid 24 contacts on the third dimension outside the plane of Fig. 1.
The MOSFET10 significant disadvantage is to have formed big overlapping region between grid 24 and N-epi layer 14, and it makes be subjected to the draining effect of operating voltage of the thin gate insulator 22 of part.The big overlapping drain electrode rated voltage that has limited MOSFET10 causes the long-term reliability problems of thin gate insulator 22, and the grid that has greatly increased MOSFET10 is to capacitance of drain C GdIn groove structure, C GdGreater than traditional transversal device, this limits the switching speed of MOSFET10 and therefore limits its use in frequency applications.
Described a kind of possible method of handling this shortcoming in the 09/591st, No. 179 application, this method is shown in Figure 2.Fig. 2 is the cross-sectional view of groove MOSFET 40, and it has the unadulterated polysilicon plug 42 near groove 20 bottoms.Except polysilicon plug 42, MOSFET40 is similar in appearance to the MOSFET10 of Fig. 1, and polysilicon plug 42 is separated and separated from grid 24 by oxide skin(coating) 44 by the bottom of oxide skin(coating) 22 from groove 20.The lamination of oxide skin(coating) 22, polysilicon plug 42 and oxide skin(coating) 44 is used to increase the distance between grid 24 and the N-epi layer 14, reduces C thus Gd
But, in some cases, can preferably have than the better insulating material of undoped polycrystalline silicon and minimize the C that is used for frequency applications in the bottom of groove 19 Gd
Described a kind of possible method of handling this shortcoming in the 09/927th, No. 320 application, this method is shown in Figure 3.Fig. 3 is the cross-sectional view of groove MOSFET 50, and it has the thick oxide layers 52 near groove 20 bottoms.Thick oxide layers 52 separates grid 24 from N-epi layer 14.This has been avoided the problem that produced when separating grid 24 and N-epi layer 14 as the thin gate insulator 15 of having only of Fig. 1.Thick oxide layers 52 is than polysilicon plug shown in Figure 2 42 more effective insulators, and compares with the MOSFET40 of Fig. 2, and this grid that has reduced MOSFET50 is to capacitance of drain C Gd
But the scheme of Fig. 3 still has thin gate oxide area 54 between this tagma 16 and thick oxide layers 52.This be because this tagma 16 by under knot and the top margin of thick oxide layers 52 do not have autoregistration.If this tagma 16 extends beyond the edge of thick oxide layers 52 downwards, MOSFET50 may have high ON resistance R OnAnd high threshold voltage.Because should aim at restively in the mill, so must allow sufficient error span to prevent overlapping between this tagma 16 and the thick oxide layers 52, and this can cause approaching, and grid is overlapping to draining significantly in the gate oxide area 54.Thin gate regions 54 also is present among the MOSFET40 of Fig. 2, between this tagma 16 and polysilicon plug 42.Therefore, C GdCan still may be a problem for frequency applications.Therefore, need have the grid of reduction to capacitance of drain C GdGroove MOSFET with better high frequency performance.
Another problem of groove MIS device relates to the electric field strength in the bight of groove, for example by bight shown in Figure 1 56 representatives.In the bight of groove electric field strength maximum, and therefore this position of taking place of avalanche breakdown normally.Avalanche breakdown generally causes producing hot carrier, and when taking place to puncture near gate oxide level, hot carrier can be injected into gate oxide level.This gate oxide level and cause the long-term reliability problems of device can damaged or rupture.Puncture in the silicon preferably betide matrix and away from gate oxide level.
At United States Patent (USP) the 5th, 072, instructed in No. 266 a kind ofly to be used for reducing the electric field strength of trench corners and to promote the technology of the puncture of matrix silicon away from groove.This technology is shown in Figure 4, and it has shown MOSFET60.MOSFET60 is similar in appearance to the MOSFET10 of Fig. 1, except dark P+ diffusion 62 extends downward plane below the bottom of groove 20 from P body 16.Dark P+ diffusion 62 has the electric field that is shaped in such a way, makes the intensity at 56 places, bight of groove reduce.
Though United States Patent (USP) the 5th, 072, technology in No. 266 has been improved the breakdown performance of MOSFET, but it is to being provided with lower limit on the cell pitch, shown in " d " among Fig. 4, because if cell pitch is reduced too much, then the dopant from dark P+ diffusion will enter the trench area of MOSFET and increase its threshold voltage.Reducing cell pitch can increase the overall circumference of the unit of MOSFET, provides bigger grid width for electric current, and reduces the ON resistance of MOSFET thus.Therefore, the clean effect of utilizing the technology of Bulucea patent to improve the breakdown characteristics of MOSFET then is to become to be difficult to reduce the ON resistance of MOSFET.
In a word, for providing low ON resistance and threshold voltage and MIS structure that still can high-frequency operation that clear and definite demand is arranged.
Summary of the invention
According to MIS device of the present invention, cover the substrate of first conductivity type by extension (" the epi ") layer of second conductivity type.Form groove in the epi layer, and in groove grid is set, this grid separates from the epi layer by oxide or other insulating barrier.
In order to minimize grid to capacitance of drain C Gd, thick dielectric layer is preferably oxide, is formed on the bottom of groove.This groove is lined with the layer of thick relatively for example nitride, and to this nitride layer directionally etching come to remove this nitride layer from the bottom of groove.This moment, the dopant that injects first conductivity type by the bottom of groove forms the drain-drift region of extending from channel bottom to substrate.
Thick dielectric layer can form in several modes.Can be by for example chemical vapor deposition (CVD) deposition oxide or other insulating barrier, and can this thick dielectric layer of etching until having only " embolism " to stay on the bottom of groove.Oxide skin(coating) can heat grow on the bottom of groove.Deposition process can make the material (for example, oxide) of deposition preferentially be deposited at the material (for example, nitride) of the sidewall of groove with respect to lining on the silicon of bottom of groove in such a way.
After on the bottom of groove, having formed thick dielectric layer, remove the material of lining at the sidewall of groove.On the sidewall of groove, form the gate oxide level of relative thin, and the conductive gate material filling of groove such as the polysilicon that mixes.Can carry out threshold value adjustment or body and inject, and form the source area of first conductivity type in the surface of epi layer.
Drain-drift region can form in several modes.The dopant of second conductivity type can inject with dosage and energy by the bottom of groove, makes it extend to substrate and not diffusion from the bottom of groove.Perhaps, the dopant of second conductivity type can inject with lower energy by channel bottom, make its at first just form zone of second conductivity type down, and dopant can diffuse to substrate downwards by this structure being placed at high temperature preset time in channel bottom.Perhaps, the layer of second conductivity type can be infused in the interface between epi layer and the substrate or near the position at interface, and dopant can upwards diffuse to the bottom of groove.Can merge above technology: the zone of second conductivity type can form just in channel bottom down and the layer of second conductivity type can be infused between epi layer and the substrate the interface or near the position at interface, and can heat this structure and cause this zone and this also laminated.Can carry out the drain-drift region that a series of injection produces " lamination " that be included in the second conductivity type district between channel bottom and the substrate.
The MIS device that is produced by this method has at thick-oxide or other insulating barrier of the bottom of groove and has the drain-drift region that extends to substrate from the bottom of groove.The knot of drain-drift region preferably with the edge autoregistration of thick dielectric layer.This minimizes grid to capacitance of drain, and does not damage the threshold voltage of device or the danger of ON resistance.Center in the MOSFET unit, the P-epi layer extends under the plane of channel bottom, guarantees that any puncture will take place away from gate oxide level.But at United States Patent (USP) 5,072, do not instruct the dark doping of any kind of in No. 266, the dopant that need not be concerned about second conductivity type so can cell pitch be set will enter channel region and influence the threshold voltage of device unfriendly.
In order to increase the puncture voltage of device, on the top of substrate, can form the light dope epi layer of first conductivity type.
Description of drawings
Fig. 1 shows the traditional groove MOSFET that is formed in the N-epi layer that covers the N+ substrate.
Fig. 2 demonstration has the groove MOSFET near the undoped polycrystalline silicon embolism of the bottom of groove.
Fig. 3 demonstration has the groove MOSFET near the thick oxide layers of the bottom of groove.
Fig. 4 shows that the center have near the unit extends downward the MOSFET of the dark P+ diffusion under the base plane of groove.
Fig. 5 A shows according to MIS device of the present invention.
The MIS device of Fig. 5 B displayed map 5A formed therein depletion region when this device is reverse biased.
Fig. 6 shows that wherein the epi layer is divided into two sublayers with different levels of doping according to MIS device of the present invention.
Fig. 7 A and 7B are the curve charts that utilizes computer simulator SUPREME preparation, respectively the concentration of dopant at the vertical cross-section place of the bottom by channel region and groove among the MOSFET of displayed map 5A.
Fig. 8 A and 8B are the curve charts that utilizes computer simulator MEDICI preparation, respectively the concentration of dopant at the vertical cross-section place of the bottom by channel region and groove among the MOSFET of displayed map 5A.
Fig. 9 A is the curve chart of the dopant profiles of getting by the vertical cross-section of the raceway groove of all traditional MOSFET as shown in Figure 1, has shown that the doping content in the channel region is descending rapidly on the direction of drain electrode.
The curve chart of the dopant profiles that Fig. 9 B gets by the vertical cross-section of the raceway groove of MOSFET, the doping content that is illustrated in the channel region is a relative fixed.
Figure 10 A and 10B are the dopant profiles curve charts similar in appearance to the curve chart of Fig. 9 B, illustrate respectively to add threshold value adjustment injection and body injection.
Figure 11 shows the general shape when the dopant profiles of the vertical cross-section under groove by the injection deep layer and when upwards spreading deep layer.
Figure 12 A-12G illustrates by inject the method that dopant forms drain-drift region between the trenched side-wall spacer and by the bottom of groove.
Figure 12 H and 12I illustrate by between the trenched side-wall spacer dopant being injected below being right after of groove and diffusing to the method that substrate forms drain-drift region downwards.
Figure 12 J and 12K illustrate the method that forms drain-drift region by the deep layer of injection dopant below groove and diffusing, doping agent to the groove that makes progress.
Figure 12 L and 12M illustrate by shallow relatively zone below being formed on being right after of groove at injection dopant between the trenched side-wall spacer and the deep layer under the groove, and the diffusing, doping agent merges and the method for formation drain-drift region until shallow zone and deep layer then.
Figure 12 N illustrates by form the method that stack region forms drain-drift region between the trenched side-wall spacer and by a series of injections that different-energy is carried out in the bottom of groove.
Figure 12 O shows the embodiment with the heavily doped region that injects in drain-drift region.
Figure 13 A-13C illustrates the method that forms thick bottom oxide by deposition oxide between the trenched side-wall spacer.
Figure 14 illustrates the method that forms thick bottom oxide by thermal growth oxide between the trenched side-wall spacer.
Figure 15 A-15C illustrates the method for Figure 14 of the sidewall spacers with different-thickness.
Figure 16 A illustrates the method that forms thick bottom oxide by utilization different deposition velocity on various materials with 16B.
Figure 17 A-17I is illustrated in and forms the method that the thick bottom oxide layer continues to make the MIS device afterwards.
Figure 18 A and 18B show epi layer wherein initial with or N type or p type impurity light dope and P type be injected into embodiment as bulk dopant.
Figure 19 A and 19B illustrate the generation how the present invention is reduced at the petiolarea in the MIS device.
Figure 20 has shown and has wherein omitted drain-drift region and groove extend into substrate by the epi layer embodiment.
Figure 21-25 shows that the light dope epi layer identical with the substrate conductivity type is formed at the embodiment of the puncture voltage that increases device on the substrate.
Figure 26 shows the MOSFET similar in appearance to MOSFET shown in Figure 21, except that having omitted the thick bottom oxide.
Embodiment
Fig. 5 A shows according to typical MIS device 70 of the present invention.MIS device 70 is MOSFET, but it can be the MIS device of other type, such as insulated gate bipolar transistor (IGBT) or mos gate control thyristor.
MIS device 70 is formed in extension (" the epi ") layer 102, and this epitaxial loayer 102 generally mixes with p type impurity and it is positioned at the top of N+ substrate 100.The N+ substrate 100 that forms the drain electrode of device can have for example from 5 * 10 -4Ω-cm to 5 * 10 -3The resistivity of Ω-cm, and P-epi layer 102 can be doped into from 1 * 10 with boron 15Cm -3To 5 * 10 17Cm -3 Concentration.N+ substrate 100 typically is about 200 micron thickness, and epi layer 102 can for from 2 microns to 5 micron thickness.
Groove 110 is formed in the P-epi layer 102, and groove 110 is lined with gate oxide level 170 and is used as the polysilicon filling of grid 174.N+ source area 178 and P+ contact zone 180 are formed at the surface of P-epi layer 102.The remainder of P-epi layer 102 forms P type base stage or body 103.Body 103 forms knot with the N+ substrate, and it is basic consistent with the interface of P-epi layer 102 and N+ substrate 100.
Make electrically contacting by metal level 184 to N+ source area 178 and P+ body contact zone 180.Boron phosphorus silicate glass (BPSG) layer 182 is with grid 174 and metal level 184 insulation.Grid 174 electrically contacts on the third dimension outside the plane, accompanying drawing place.
According to the present invention, the drain electrode of device 70 comprises: (a) N type drain-drift region 16, and it extends between the bottom of groove 110 and N+ substrate 100; (b) thick bottom oxide district 150, it forms in adjacent to the groove 110 of drain-drift region 116.Knot 105 between N drain-drift region 116 and the P body 103 extends between N+ substrate and groove 110.N drain-drift region 116 can be for example with phosphorus doping to from 5 * 10 15Cm -3To 5 * 10 17Cm -3Concentration.
Fig. 7 A is the curve chart of doping content among the MOSFET70.This curve chart is by computer simulator SUPREME preparation, and obtains by channel region is designated as I-I in Fig. 5 A vertical cross-section place.The shown curve display arsenic and the doping content of boron, and the 3rd curve display net dopant concentration.Fig. 7 B is similar curve chart, and the bottom of crosscut groove is designated as II-II in Fig. 5 A vertical cross-section place obtains.The transverse axis of Fig. 7 A is the distance in micron under the bottom of groove; The transverse axis of Fig. 7 B is in the distance of micron below the bottom of groove.The longitudinal axis of Fig. 7 A and Fig. 7 B is with atom/cm 3The denary logarithm of the doping content of meter.Note among Fig. 7 A, more smooth as the concentration ratio of the boron of the background doped agent in the P-epi layer 102, and in channel region, occupy an leading position.When moving into source electrode or drain electrode from channel region, the doping content of arsenic increases.
Fig. 8 A and Fig. 8 B are respectively the curve charts of the doping content of identical section, as Fig. 7 A and Fig. 7 B.But Fig. 8 A and Fig. 8 B utilize computer simulator MEDICI preparation and only show or the net dopant concentration of N type or P type.
SUPREME only considers the doping content at single vertical cross-section place with the different SUPREME of being of MEDICI simulation, and does not consider the effect at the dopant of other lateral shift position, and MEDICI considers dopants all in the two dimensional surface of accompanying drawing.
Below be some in the advantage of MOSFET70:
1. avalanche breakdown will generally betide the interface between N+ substrate 100 and the P-epi layer 102, away from groove (for example, the position shown in 72 in Fig. 5 A).This avoided from the hot carrier that the zone that punctures, produced to the damage of gate oxide level 170,
2. the gate oxide 170 that reaches the bight of maximum groove at electric field is protected and can not ruptures.
3. can obtain higher punch-through breakdown for given threshold voltage.Knot 105 between N drain-drift region 116 and the P body 103 extends downward N+ substrate 100.Shown in Fig. 5 B, when PN junction 105 is reverse biased, as they when MOSFET70 is in off status and block current flow, extend along the whole length of knot 105 by the indicated depletion region of dotted line 105A, 105B, and therefore the depletion region in channel region can not expanded fast to source area.Depletion region is the condition that causes punch-through breakdown towards the expansion of source area.
4. in addition, can obtain higher punch-through breakdown voltage for given threshold voltage.Shown in Fig. 9 A, in the conventional MOS FET of the body with diffusion, when near N-epi (drift region), the doping content of body descends rapidly.Threshold voltage is by peak doping concentration N The A peakDecision.Punch-through breakdown voltage is by the total charge dosage Q in the channel region Raceway grooveDecision (by the Regional Representative under this body curve of P among Fig. 9 A).In MOSFET of the present invention, the dopant profiles in this tagma of P is more smooth, shown in Fig. 9 B.Therefore, when the total electrical charge in the raceway groove is big, N The A peakCan be identical, higher punch-through breakdown voltage is provided.
5. because in each unit, there is not dark bulk diffusion (at United States Patent (USP) the 5th, 072, the type of being instructed in No. 266), is indifferent to additional P type dopant so can reduce cell pitch and will enters channel region, improved the threshold voltage of MOSFET.Therefore can increase arrangements of cells density.This has reduced the ON resistance of device.
6. in traditional groove MOSFET, light dope " drift region " often is formed between raceway groove and the heavy doping substrate.Doping content in the drift region must remain under the certain level.Otherwise can not obtain effectively to exhaust and excessive in the electric field strength at the place, bight of groove.But low doping content will increase the ON resistance of device in the maintenance drift region.On the contrary, N drain-drift region 116 of the present invention more important place is mixed, and exhausts because the length of the knot 105 between this tagma 103 of the shape of N drain-drift region 116 and N drain-drift region 116 and P provides more effective.More heavily doped N drain-drift region 116 has reduced the ON resistance of device.
7. shown in Figure 19 A, in the petiolarea of MOSFET, P type diffusion is not independently needed, because P-epi layer 102 extends to the N+ substrate 100 except N drain-drift region 116 places are set.Figure 19 B shows the petiolarea of the traditional MOSFET that comprises P type diffusion 75.The elimination of a diffusion of P type petiolarea or a ring has reduced the quantity of masks.For example, only need five masks here in the described method.
The formation of drain-drift region
Figure 12 A-12N is the cross-sectional view of demonstration according to an embodiment of the method for manufacturing of the present invention such as the groove MOSFET of the MOSFET70 among Fig. 5 A.Shown in Figure 12 A, this method is the lightly doped P-epi layer 102 of growth (about 6 to 8 μ m are thick usually) on heavily doped N+ substrate 100 at first.By the dry oxidation that continues 10 minutes at 950 ℃, hot grown pad oxide 104 (for example, 100-200 is thick) on P-epi layer 102.Shown in Figure 12 B, by chemical vapor deposition (CVD) nitride layer 106 (for example, 200-300 is thick) on pad oxide 104.Utilize common photoetching process and first (groove) mask, composition nitride layer 106 and pad oxide 104 form opening 108, in opening 108 groove will be set.Shown in Figure 12 C, by opening 108 etched trench 110, use dried plasma etching usually, for example reactive ion etching (RIE).Groove 110 can be dark for the wide and about 1-2 μ of about 0.5-1.2 μ m m.
In the sidewall and bottom heat growth second pad oxide 112 (for example, 100-200 is thick) of groove 110, shown in Figure 12 D.On the sidewall of groove 110 and the bottom and on the top of nitride 106 by CVD deposition of thick nitride layer 114 (for example, 1000-2000 ) conformally, shown in Figure 12 E.Utilize directed dried plasma etching,, use and compare the etchant that oxide has high selectivity for nitride layer 114, nitride etching layer 114 such as RIE.Nitride etch is along the spacer 115 of the sidewall reservation nitride layer 114 of groove 110, and the centre bottom at groove 110 exposes pad oxide 112 simultaneously, shown in Figure 12 F.Can over-etch nitride layer 114 to a kind of like this degree make from the top removal nitride layer 106 of pad oxide 104.
Keep sidewall spacers 115 in position, produce N drain-drift region 116 (Figure 12 G) by injecting N type dopants in the pad oxide 112 of the bottom of groove 110.For example, can be with 1 * 10 13Cm -2To 1 * 10 14Cm -2Dosage and the energy of 300KeV to 3.0MeV inject phosphorus.For fear of the remarkable diffusion of phosphorus and the expansion subsequently of N drain-drift region 116, this structure is exposed to thereafter and is limited to and about 950 ℃ of heat budgets that continue 60 minutes equivalences, or this structure can stand at 1050 ℃ of rapid thermal annealings (RTA) of lasting 90 seconds.In two kinds of situations, N drain-drift region 116 keeps compact shape basically, shown in Figure 12 C.Advantageously, in the cross-sectional view of Figure 12 G, at least 75% and preferred 90% of N drain-drift region 116 is located immediately under the groove 110.
Perhaps, can form N drain-drift region 116 like this, by below groove 110 immediate, forming N type district 118 (Figure 12 H) with the low-yield injection phosphorus of 30KeV to 300KeV (usually 150KeV), then by at 1050 to 1150 ℃ of heating (usually 1100 ℃ continue 90 minutes) diffusion in 10 minutes to 120 minutes phosphorus, make N type district 118 and the drain-drift region 120 that form extending transversely downwards with the class shape shown in Figure 12 I.
In another variant of this method, with high relatively energy deep layer 122 (for example, phosphorus) is injected in the position under the groove, shown in Figure 12 J, and use thermal process upwards to spread the bottom of phosphorus until its arrival groove, produce drain-drift region 124, shown in Figure 12 K.This is with above different in conjunction with the described method of Figure 12 G, and wherein N type dopant extends to interface between N+ substrate and the P-epi layer from the bottom of groove 110 after injecting; Or with different in conjunction with the described method of Figure 12 H, wherein after injecting, dopant only is positioned at below the bottom of groove.When forming deep layer 122 with high relatively energy injection N type dopant, the thickness of gash depth, P-epi layer 102 and the variation of injecting energy can cause layer 122 or above the interface between N+ liner 100 and P-epi layer 102 (for example, if P-epi layer 102 is thick and/or gash depth is little), perhaps be arranged in N+ substrate 100 (for example, if P-epi layer 102 is thin and/or gash depth big).
Figure 11 shows the general shape of the dopant profiles in the vertical cross-section that is starting from channel bottom when upwards spreading dark implanted layer formation drain-drift region.As shown in the figure, the concentration of the N type dopant in drain-drift region increases monotonously with the increase of distance under the bottom of groove.This is different from and utilizes the dopant profiles under the groove among the formed MOSFET of low-energy method, and shown in Fig. 8 B, wherein doping content is initial reduces and near the increase N+ substrate then.
Utilize the method shown in Figure 12 J and the 12K, a kind of N drain-drift region is provided, it mainly is restricted to just zone below groove and the littler cell pitch of permission.The also easier expansion of this method and bigger output is provided.
Perhaps, can use the combination of upwards diffusion, diffusion downwards to form drain-drift region.Shown in 12L, form dark N layer 122 (for example, phosphorus) by the high energy method for implanting at the interface at N+ substrate 102 and P-epi layer 100.In conjunction with Figure 12 H such as above-mentioned, inject N type dopant by the bottom of groove and come below groove, to form N+ district 118.Heat this structure then, for example, to 900 to 1100 ℃.Dark N floor 122 upwards spreads and N district 118 diffusion downwards merges until them, forms N type drain-drift region 126, shown in Figure 12 M.
Another optional method is for forming drain-drift region with a series of three times or more N injection with the lamination that the energy that increases continuously forms overlapping injection region 128, shown in Figure 12 N.Lamination 128 comprises four injection region 128A-128D, forms lamination but also can use to be less than or to inject more than four times.Lamination can form (that is, not heating) basically under the situation that does not have diffusion, or it can be heated the lap between diffusing, doping agent and the increase district 128A-128D.
Alternatively, in order to be increased in electric current of propagating in the drain-drift region and the ON resistance that further reduces device, heavy doping N+ district 130 can be injected, shown in Figure 12 O in drain-drift region 116.
No matter last in this method is high-energy or low-yield, and the N drain-drift region extends to the bottom of groove from the N+ substrate.In many cases, the knot between N drain-drift region and the P-epi layer extends to the sidewall of groove from substrate.If utilize low-yield method for implanting and thermal diffusion dopant subsequently, the knot between drain-drift region and the P-epi layer has the shape of arc, its internal recess to drain-drift region (Figure 12 I).
Can use above-mentioned any method to form drain-drift region.Following to the explanation that how to form thick bottom insulation layer in, will hypothesis use the method for implanting of Figure 12 G representative.However, it should be understood that this also can use any optional method.
The formation of thick bottom oxide
As shown in FIG. 13A, this method is deposition of thick insulating barrier 150 at first, and for example it can be thick for 2-4 μ m.Selected deposition process is non-conformal, filling groove 110 and being spilled on the top surface of P-epi layer 102.Thick dielectric layer 150 can for example be low temperature oxide (LTO), chemical vapor deposition (CVD) oxide, phosphosilicate glass (PSG), boron phosphorus silicate glass (BPSG) or other insulating material.In the following description, insulating barrier 150 is assumed to be the CVD oxide skin(coating).
Oxide skin(coating) 150 is etched back in the groove 110, carries out wet etching by adopting for oxide than the etchant that nitride has high selectivity usually.Etching oxide layer 150 is stayed in the groove 110 until the 0.1-0.2 μ m that only has an appointment, and shown in Figure 13 B, forms thick bottom oxide layer 151.
Remove nitride layer 106 and spacer 115, carry out wet etching by adopting than the etchant that oxide has high selectivity usually for nitride.Usually remove pad oxide 104 by wet etching, and pad oxide 112 exposed portions.This wet etching is removed on a small quantity but inessential part thick oxide layers 151.Resulting structure is shown in Figure 13 C, and thick oxide layers 151 remaines in the bottom of groove 110.
According to another variant of the present invention, between the gate oxide bed thickness and thin part, form the transition of gradual change.
This method can be with identical by the described method of step shown in Figure 12 F, and wherein nitride etch keeps sidewall spacers 115 along the sidewall of groove 110, and the centre bottom at groove 110 exposes pad oxide 112 simultaneously.But, after step in, be not the deposition of thick insulating barrier, but by thermal process grow thick oxide skin(coating).When so carrying out, the silicon of thermal oxide consumption part and the edge of incision sidewall spacers 115 thus cause nitride " to be peeled off " by the surface of groove.This forms a kind of structure of " beak " in traditional LOCOS (localized oxidation of silicon) method, and the LOCOS method often is utilized to produce field oxide region at the top surface of semiconductor device.
The bottom that Figure 14 is presented at groove 110 structure after the thermal oxide layer 158 of having grown.Shown this structure among Figure 15 A in detail.The edge of thermal oxide layer 158 be pushed to sidewall spacers 115 below, and therefore become inclination or gradually thin.
The thickness that changes sidewall spacers allows the edge of oxide skin(coating) is arranged at different positions.Figure 15 A shows thick relatively sidewall spacers 115, and therefore the edge of oxide skin(coating) 158 is positioned on the bottom of groove 110.Figure 15 B shows thin sidewall spacers 115A, and the edge of oxide skin(coating) 158A is positioned at the bight of groove 110 substantially.Figure 15 C shows thinner sidewall spacers 115B, and the edge of oxide skin(coating) 158B is positioned on the sidewall of groove 110.
In a similar manner, the edge of oxide skin(coating) can be arranged at different points placed in the middle by the thickness that changes sidewall spacers.The thickness of sidewall spacers is independent of the width or the degree of depth of groove.For example, if sidewall spacers in the thick scope of 1,500 to 2,000 , the edge of oxide skin(coating) is positioned at most probable the bottom (Figure 15 A) of groove.If thick 500 of sidewall spacers or littler, the edge of oxide skin(coating) will be usually located on the sidewall of groove (Figure 15 C) so.
For example, by can grown oxide layer from 1,000 ℃ to 1,200 ℃ temperature heating silicon structure 20 minutes to 1 hour.
Show the other method that forms thick oxide layers among Figure 16 A and Figure 16 B again.After forming drain-drift region 116 and sidewall spacers 115, as mentioned above with shown in Figure 12 A-12G, oxide skin(coating) 160 optionally is deposited on the silicon that is exposed in the bottom of groove 110 but not the method on sidewall spacers 115 is come deposited oxide layer 160 by a kind of.Operable a kind of method is sub-atmospheric pressure chemical vapour deposition (CVD) (SACVD) method, utilizes ozone to drive chemical reaction.During reaction, ozone decomposes easily and discharges elemental oxygen, its with such as the compound silicon dioxide that forms of the presoma of TEOS.This structure can be annealed then.
Table 1 illustrates the exemplary processes parameter of the TEOS SACVD formation thick dielectric layer 21 of ozone activation.
Table 1
Temperature 400℃
Pressure 600Torr
The ozone flow velocity 5000sccm
Helium flow speed 4000sccm
The TEOS flow velocity 325mgm
GDP is to the wafer interval 250mm
Spacer 115 can comprise the material outside the denitrify.Select the employed material of spacer to make silicon dioxide preferentially be deposited on the silicon than spacer.The selection of spacer material is according to employed oxide deposition method.Table 2 illustrates the deposition selectivity of different materials during the TEOS SACVD that ozone activates.
Table 2
Material The deposition selectivity
Si: nitride 5∶1
Si: thermal oxide 3∶1
Si:TEOS PECVD oxide 2∶1
Si：SiH 4The PECVD oxide 1∶1
Si：PECVD BPSG 1∶1
As shown in table 2, during the TEOS SACVD that ozone activates, silica deposit is in being deposited on the nitride fast five times than it on the silicon.Therefore, during utilizing nitride sidewall spacers 115 to make device, the silicon dioxide that is deposited on the bottom of groove 110 is thicker than any silicon dioxide that is deposited on the nitride sidewall spacers 115 with about five times.In fact, for the oxidation film growth of 3000 on silicon face, on nitride surface, do not observe oxide growth.The deposition selectivity may be because silicon nitride be compared low surface energy with silicon.As shown in table 2, when the deposition of layer 160 is the TEOS SACVD of ozone activation, the silicon dioxide of the silicon dioxide of heat growth or TEOS PECVD deposition also can be used as the suitable material of spacer, because silicon dioxide also will preferentially be deposited on the silicon than these materials.SiH 4The BPSG of the silicon dioxide of PECVD deposition or PECVD deposition will not be suitable for the spacer material of the TEOS SACVD that ozone activates, because silicon dioxide is not to more preferably silicon of these materials.If use the deposition process the TEOS SACVD that activates except ozone, can use so except the material shown in the table 2 to be used for sidewall spacers.
After deposited oxide layer 160, use buffer oxide etch to remove any lip-deep oxide that is deposited on nitride sidewall spacers 115, and use wet nitride etch to remove nitride sidewall spacers 115 and nitride layer 106.In order to guarantee to remove all nitride, can carry out another annealing, for example, come any remaining nitride of oxidation at 1000 ℃ of lasting 5-10 minutes, and after annealing, carry out oxide etching.Oxide etching is removed any oxidized nitride, but but can not remove the oxide skin(coating) 160 of signal portion.
Pad oxide 104,112 also is removed by wet etching usually.This wet etching is removed a spot of but inessential partial oxide layer 160.Shown resulting structure among Figure 16 B, partial oxide layer 160 is stayed the bottom of groove 110.
Finishing of device
After having formed thick bottom oxide, can in the sidewall of groove, grow and remove the sacrificial oxide layer (not shown) by above a kind of method.This assists in removing any lens lesion that is caused during the etching of groove.Sacrificial oxide layer can be thick for about 500 , and can for example pass through in the heat growth in 20 minutes of 1050 ℃ of dry oxidations, and remove by wet etching.The wet etching that keeps short sacrifice gate oxide is to minimize the etching in the bottom oxide layer of groove.
Afterwards, shown in Figure 17 A, gate oxide level 170 or other insulating barrier (for example, about 300-1000 is thick) are formed on the top surface of the sidewall of groove 110 and P-epi layer 102.For example, can for example come hot grow gate oxide layer 170 in 20 minutes at 1050 ℃ of dry oxidations.
Shown in Figure 17 B, the layer 172 of deposit spathic silicon or other electric conducting material (for example, by low pressure chemical vapor deposition (LPCVD) method) come filling groove 110 and overflow the horizontal surface of oxide skin(coating) 170.Polysilicon layer 172 for example can be in-situ doped polysilicon, or the unadulterated polysilicon layer that is injected into subsequently and anneals, or interchangeable electric conducting material.Usually utilize reactive ion etching to come etching polysilicon layer 172 roughly fair, therefore form grid 174, shown in Figure 17 C with the top of P-epi layer 102 until the top surface of polysilicon layer 172.In N type MOSFET, grid 174 for example can be for phosphorus doping to 1 * 10 19Cm -3The polysilicon layer of concentration.In certain embodiments, polysilicon layer 172 can be etched surpasses the top of groove 110, and recessed thus grid 174 minimizes grid to the source electrode overlap capacitance, and oxide or other insulating barrier can be formed on the grid 174.In many cases, by the opening etching polysilicon layer 172 in second (grid polycrystalline silicon) mask, make to allow part polysilicon layer 172 to keep in position, wherein the gate metal by metal level 184 partly contacts grid 174 (referring to Figure 17 I).
Alternatively,, then can carry out the threshold value adjustment and inject, for example by boron is injected through the surface of P-epi layer 102 if adjust threshold voltage.Can be with 5 * 10 12Cm -2Dosage and the energy of 150KeV inject boron, in the part of the P-epi of the raceway groove that will form MOSFET layer 102, produce 1 * 10 17Cm -3The concentration of P type atom.As above-mentioned, Figure 10 A shows the dopant distribution by the vertical cross-section place of raceway groove, has shown threshold value adjustment injection.As shown in the figure, the threshold value adjustment is injected and is usually located at the just zone of the raceway groove below source area.The peak doping concentration N that the threshold voltage of MOSFET is injected by the threshold value adjustment The A peakDecision.If the threshold voltage of device does not need to be adjusted, can omit this step so.
If of course, the P type dopant that can inject so such as boron forms this tagma 176, shown in Figure 17 D.The dopant profiles that typical body injects shown in the curve chart of Figure 10 B.Some injects bulk doped similar in appearance to the threshold value adjustment, but employed energy is higher and therefore body inject the plane that extends to more near the knot between P-epi layer and the N drain-drift region.The peak doping concentration N that the threshold voltage of MOSFET is injected by body The A peakDecision.Perhaps, can drive the P body and be injected into following but plane on the interface between P-epi layer 102 and the N+ substrate 100, the bottom of groove 110, shown in the body regions among Figure 17 E 186 like that.
Afterwards, can cover the top surface of P-epi layers 102, and the N type dopant that can inject such as phosphorus forms N+ source area 178, shown in Figure 17 F with the 3rd (source electrode) mask 190.Remove source mask 190.Bpsg layer 182 is deposited on the top surface of device, and deposits and etching the 4th (contact) mask 183 on the surface of bpsg layer 182, shown in Figure 17 G.By the opening etching bpsg layer 182 in the contact mask 183, inject P type dopant by the resulting opening in the bpsg layer 182 and form P+ body contact zone 180, shown in Figure 17 H.For example can be with 5 * 10 15Cm -2Dosage and the energy of 80KeV inject N+ source area 178 with arsenic, produce 1 * 10 20Cm -3Concentration; Can be with 1 * 10 15Cm -2Dosage and the energy of 60KeV inject P+ source area 180 with boron, produce 5 * 10 19Cm -3Concentration of dopant.
Depositing metal layers 184 is preferably aluminium, shown in Figure 17 I, sets up short circuit between source area 178 and body contact zone 180.Use the 5th (metal) mask (not shown) that metal level 184 compositions and etching are become the source metal part, shown in Figure 17 I, and be used for creating the gate metal part that electrically contacts with grid.This finishes the manufacturing of MOSFET70.
Among another embodiment, initial usefulness of epi layer or N type or p type impurity are lightly doped, and inject as bulk dopant such as the p type impurity of boron, and are driven the interface between dopant arrival epi layer and substrate.Such embodiment shown in Figure 18 A and the 18B.Shown in Figure 18 B, when boron had been injected into and has spread, this tagma of P was formed on the N+ substrate 102.
Can use the structure that comprises P body 176, the P body 186 shown in Figure 17 E and the P body 104 shown in Figure 18 B shown in Figure 17 D in conjunction with any method of formation drain-drift region described here.This comprises: the method shown in Figure 12 J and the 12K comprises the upwards diffusion of dark implanted layer; Method shown in Figure 12 L and the 12M is included in the upwards diffusion of the dark implanted layer under the bottom of groove and the downward diffusion of injection region; With the method shown in Figure 12 N, comprise with different energy and inject the lamination that a plurality of N types district forms overlapping district.
Fig. 6 shows interchangeable embodiment.The P-epi layer is divided into sublayer P-epi1 and P-epi2 in MOSFET95.Utilize well-known method, can when growing the epi layer, form epi layer with sublayer by the flow velocity that changes dopant gas.Perhaps, can assign to form sublayer P-epi1 by the top of dopant being injected the epi layer.
The concentration of dopant of sublayer P-epi1 can or be greater than or less than the concentration of dopant of sublayer P-epi2.The threshold voltage of MOSFET and punch-through breakdown are the functions of the doping content of sublayer P-epi1, and the puncture voltage of MOSFET and ON resistance are the functions of the doping content of sublayer P-epi2.Therefore, among the MOSFET of present embodiment, can be independent of avalanche breakdown voltage and ON resistance design threshold voltages and punch-through breakdown voltage.The P-epi layer can comprise the sublayer with different levels of doping more than two.
MOSFET95 comprises the gate electrode 202 that is arranged in the groove 204, and it is lined with oxide skin(coating).The upper surface of grid 202 is recessed into groove 204.Oxide skin(coating) comprises: thickness portion 206 forms according to the present invention, and generally is positioned at the bottom of groove 204; Relative thin part 210 is adjacent with the sidewall of groove 204.Be transition region 208 between thickness portion 206 and the thin part 210, wherein the thickness of oxide skin(coating) successively decreases gradually from thickness portion 206 to thin part 210.MOSFET100 also comprises PN junction, and it intersects with groove 204 in transition region 208.As mentioned above, during making MOSFET95,, can change the position of transition region 208 by changing the thickness of nitride layer.
MOSFET95 also comprises the thick oxide layers 218 of N+ source area 214, P+ body contact zone 216, overlapping gate electrode 202 and the metal level 220 that electrically contacts with N+ source area 214 and P+ body contact zone 216.Shown in dotted line, MOSFET95 comprises high doped district 222 in the bottom of groove 204.Be shown in as Figure 12 O and form after the nitride layer,, can produce high doped district 222 by injecting N type dopant such as arsenic or phosphorus.
Figure 20 shows another interchangeable embodiment.In MOSFET98, omitted drain-drift region, and groove 230 extends in the N+ substrate 100 by P-epi layer 102 fully.Present embodiment is particularly suitable for low pressure (for example, 5V or littler) MOSFET.
In order to increase the puncture voltage of this device, can be below the top of N+ substrate 100, P-epi layer 102 the lightly doped N type of growth epi layer.Figure 21-Figure 25 shows several embodiment of this structure.
Figure 21 shows the MOSFET250 similar in appearance to the MOSFET70 shown in Fig. 5 A, except that having grown N-epi layer 252 at the top of N+ substrate 100.N-epi layer 252 is can be for from 1 to 50 μ m thick and can be with phosphorus doping to from 1 * 10 15/ cm -3To 1 * 10 17/ cm -3Concentration.The doping content of N-epi layer 252 can be than the doping content or the height or low of P-epi layer 102.
Except growth N-epi layer 252, the method for making MOSFET250 is similar in appearance to top method in conjunction with the described manufacturing of Figure 12 A-12G MOSFET70.Particularly, shown in Figure 12 G, can inject phosphorus by the bottom of groove and form drain-drift region 116.But energy and dosage that phosphorus doping is set guarantee that drain-drift region 116 extends downward the coboundary of N-epi layer 252, but not to the coboundary of N+ substrate 100.
Figure 22 shows MOSFET260, and it has similar in appearance to the drain-drift region 120 of the drain-drift region 120 shown in Figure 12 I.MOSFET260 forms like this, forms N type district (referring to Figure 12 H) by injecting phosphorus below being right after of groove, and spreads phosphorus by heating then and makes N type district and the drain-drift region 120 that forms extending transversely downwards, as shown in figure 22.
Figure 23 shows MOSFET270, and it has similar in appearance to the drain-drift region 124 of the drain-drift region 124 shown in Figure 12 K.MOSFET270 forms like this, by injecting phosphorus in the N of formation at the interface type district (referring to Figure 12 J) near N-epi floor 252 and P-epi floor 102, spread phosphorus by heating then and make N type district downwards and the drain-drift region 124 that forms extending transversely, as shown in figure 23.
Figure 24 shows MOSFET280, and it has similar in appearance to the drain-drift region 126 of the drain-drift region 126 shown in Figure 12 M.In order to make MOSFET280, by the high energy method for implanting, dark N layer (for example, phosphorus) is formed at the interface of N-epi layer 252 and P-epi layer 100.Bottom by groove is injected N type dopant and is come to form the 2nd N district below being right after of groove.Heat this structure then, for example to 900 to 1100 ℃.The diffusion downwards of diffusion and the 2nd N district merges until them on the dark N course, forms N type drain-drift region 126, as shown in figure 24.
Figure 25 shows to comprise by a series of N and injects the MOSFET290 that forms, and the lamination of the injection region 128 that this injection overlaps with the energy that increases continuously is similar in appearance to the structure shown in Figure 12 N.Lamination 128 comprises four injection regions, is less than or forms lamination more than four injections but can use.Can not spread (that is, not heating) significantly and form this lamination, or it can be heated the lap of diffusing, doping agent and increase injection region.
Embodiment is similar in appearance to shown in Figure 21-25 those for another group, and except the bottom of omitting thick bottom oxide district 150 and groove studs with the oxide skin(coating), this oxide skin(coating) has the oxide skin(coating) 170 essentially identical thickness that the wall with groove 110 studs with.In order to make this device, inject N type dopant through the bottom 110 of groove in the stage of the technology shown in Figure 12 C, and omit the deposition of the nitride layer 114 shown in Figure 12 E and 12F and the formation of sidewall spacers 115 such as phosphorus.N type dopant is feasible to be extended downwards from the bottom of groove if inject, and shown in Figure 12 G, forms MOSFET300 so, as shown in figure 26.Perhaps, can make the drain-drift region of kind shown in those figure by following in conjunction with the method shown in Figure 12 H-12I, 12J-12K, 12L-12M and the 12N.In all situations, drain-drift region extends to the knot of N-epi layer 252 from the bottom of groove 110.
Though described several specific embodiments of the invention, these embodiment only are illustrative.It should be appreciated by those skilled in the art that according to wide principle of the present invention and can make a lot of additional embodiment.For example, though the above embodiments are N-channel MOS FET, can make the P channel mosfet according to the present invention by the conductivity in various zones among the counter-rotating MOSFET.

Claims (54)

1. method of making trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type is provided;
Form first epitaxial loayer on described substrate, described first epitaxial loayer is doped into doping content less than the doping content of described substrate with the dopant of first conductivity type;
Form second epitaxial loayer on described first epitaxial loayer, described second epitaxial loayer is generally second conductivity type;
In described second epitaxial loayer, form groove;
In described groove, form sidewall spacers;
Between described sidewall spacers and inject the dopant of described first conductivity type by the bottom of described groove;
In forming bottom insulation layer on the bottom at described groove between the described sidewall spacers;
Remove described sidewall spacers;
Form gate insulator on the sidewall of described groove, described gate insulator is thinner than described bottom insulation layer; With
Electric conducting material is introduced described groove.
2. the method for claim 1, wherein, thereby the formation of described sidewall spacers be included in the groove conformally depositing insulating layer and directionally the described insulating barrier of etching remove the described insulating barrier of part in the bottom of described groove, the wall place near described groove stays sidewall spacers thus.
3. method as claimed in claim 2, wherein, described insulating barrier comprises nitride.
4. the method for claim 1, wherein, the injection of the dopant of described first conductivity type comprises with a dosage and energy injects dopant, makes after the described injection and does not have substantially under the situation of thermal diffusion, and described dopant extends to described first epitaxial loayer from the bottom of described groove.
5. the method for claim 1, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make dopant after the described injection form below the bottom that is positioned at groove and do not extend to the zone of first conductivity type of described first epitaxial loayer, described method comprises that also described first epitaxial loayer of heating spreads described dopant downwards, is formed on the drain-drift region of extending between described groove and described first epitaxial loayer thus.
6. the method for claim 1, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make that described dopant forms the deep layer of separating from described groove substantially after the described injection, described method comprises that also described first epitaxial loayer of heating upwards to spread described dopant, is formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer thus.
7. the injection of the dopant of the method for claim 1, wherein described first conductivity type comprises:
With the first that a dosage and energy inject dopant, make the first of described dopant after the described injection form the zone of first conductivity type, the zone of described first conductivity type is positioned at the bottom of described groove and does not extend to described first epitaxial loayer; With
Inject the second portion of dopant with a dosage and energy, make the second portion of described dopant after the described injection form basically the deep layer of separating with described groove;
Described method also comprises:
Heat described first epitaxial loayer and make described first and described second portion merge, be formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer thus with the first of the described dopant of downward diffusion and the second portion that upwards spreads described dopant.
8. the method for claim 1, wherein, the injection of the dopant of described first conductivity type comprises the dopant of the different-energy of at least three parts respectively, with the lamination in the continuous zone that forms described first conductivity type, described lamination is formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer.
9. as the arbitrary described method of claim 1 to 8, wherein, the formation of described bottom insulation layer comprises that sedimentary deposit and the described layer of etching form described bottom insulation layer.
10. method as claimed in claim 9, wherein, the deposition of described layer comprises deposited oxide layer.
11. method as claimed in claim 10, wherein, the deposition of described layer comprises by chemical vapour deposition (CVD) comes sedimentary deposit.
12. method as claimed in claim 9, wherein, described bottom insulation layer is a low temperature oxide layer.
13. method as claimed in claim 9, wherein, the deposition of described layer comprises the deposition glassy layer.
14. as the arbitrary described method of claim 1 to 8, wherein, the formation of described bottom insulation layer is included in thermal growth oxide layer on the bottom of described groove.
15. as the arbitrary described method of claim 1 to 8, wherein, the formation of described bottom insulation layer comprises deposition materials, described material is compared the bottom that preferentially is deposited on described groove with described sidewall spacers.
16. trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type;
First epitaxial loayer of first conductivity type on described substrate, described first epitaxial loayer mixes gentlyer than described substrate;
Second epitaxial loayer of second conductivity type on described first epitaxial loayer, channel shaped are formed in described second epitaxial loayer;
Grid in described groove;
Along the gate insulator of the sidewall of described groove, described grid by described gate insulator from the described second epitaxial loayer electric insulation;
In the bottom insulation layer of described channel bottom, described bottom insulation layer is thicker than described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described first epitaxial loayer, and forms PN junction with described second epitaxial loayer, and described PN junction extends between described groove and described first epitaxial loayer.
17. trench metal-insulator as claimed in claim 16-semiconductor device, wherein, described PN junction is with respect to the internal recess of described drain-drift region.
18. trench metal-insulator as claimed in claim 16-semiconductor device, wherein, described PN junction extends between the sidewall of described first epitaxial loayer and described groove.
19. trench metal-insulator as claimed in claim 16-semiconductor device, wherein, described PN junction is aimed at the edge of described bottom insulation layer.
20. a groove metal oxide semiconductor field effect transistor comprises:
The substrate of first conductivity type;
First epitaxial loayer of first conductivity type on described substrate, described first epitaxial loayer mixes gentlyer than described substrate;
Second epitaxial loayer of second conductivity type on described first epitaxial loayer, channel shaped are formed in described second epitaxial loayer;
Grid in described groove;
Along the gate insulator of the sidewall of described groove, described grid is isolated from described second epitaxial loayer electricity by described gate insulator;
In the bottom insulation layer of described channel bottom, described bottom insulation layer is thicker than described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described substrate, and forms PN junction with described second epitaxial loayer, and described PN junction extends between described groove and described first epitaxial loayer,
Source area is adjacent to the top surface setting of the sidewall and the described epitaxial loayer of described groove.
21. groove metal oxide semiconductor field effect transistor as claimed in claim 20 comprises the threshold value adjustment injection region of described second conductivity type.
22. groove metal oxide semiconductor field effect transistor as claimed in claim 21 comprises this tagma of described second conductivity type, described this tagma is mixed heavylier than described epitaxial loayer.
23. a method of making trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type is provided;
Form first epitaxial loayer on described substrate, described first epitaxial loayer is doped into doping content less than the doping content of described substrate with the dopant of first conductivity type;
Form second epitaxial loayer on described first epitaxial loayer, described second epitaxial loayer is generally second conductivity type;
In described second epitaxial loayer, form groove;
Inject the dopant of described first conductivity type by the bottom of described groove;
On the bottom of described groove and sidewall, form gate insulator;
Electric conducting material is introduced described groove.
24. method as claimed in claim 23, wherein, the injection of the dopant of described first conductivity type comprises with a dosage and energy injects dopant, makes after the described injection and does not have substantially under the situation of thermal diffusion, and described dopant extends to described first epitaxial loayer from the bottom of described groove.
25. method as claimed in claim 23, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make dopant after the described injection form below the bottom that is positioned at groove and do not extend to the zone of first conductivity type of described first epitaxial loayer, described method comprises that also described first epitaxial loayer of heating with the described dopant of downward diffusion, is formed on the drain-drift region of extending between described groove and described first epitaxial loayer thus.
26. method as claimed in claim 23, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make that described dopant forms the deep layer of separating from described groove substantially after the described injection, described method comprises that also described first epitaxial loayer of heating upwards to spread described dopant, is formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer thus.
27. method as claimed in claim 23, wherein, the injection of the dopant of described first conductivity type comprises:
With the first that a dosage and energy inject dopant, make the first of described dopant after the described injection form the zone of first conductivity type, the zone of described first conductivity type is positioned at the bottom of described groove and does not extend to described first epitaxial loayer; With
Inject the second portion of dopant with a dosage and energy, make that the second portion of described dopant forms the deep layer of separating from described groove substantially after the described injection;
Described method also comprises:
Heat described first epitaxial loayer and make described first and described second portion merge, be formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer thus with the first of the described dopant of downward diffusion and the second portion that upwards spreads described dopant.
28. method as claimed in claim 23, wherein, the injection of the dopant of described first conductivity type comprises the dopant of the different-energy of at least three parts respectively, with the lamination in the continuous zone that forms described first conductivity type, described lamination is formed on the drain-drift region of extending between the bottom of described groove and described first epitaxial loayer.
29. trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type;
First epitaxial loayer of first conductivity type on described substrate, described first epitaxial loayer mixes gentlyer than described substrate;
Second epitaxial loayer of second conductivity type on described first epitaxial loayer, channel shaped are formed in described second epitaxial loayer;
Grid in described groove;
Along the bottom of described groove and the gate insulator of sidewall, described grid is isolated from described second epitaxial loayer electricity by described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described first epitaxial loayer, and forms PN junction with described second epitaxial loayer, and described PN junction extends between described groove and described first epitaxial loayer.
30. trench metal-insulator as claimed in claim 29-semiconductor device, wherein, described PN junction is with respect to the internal recess of described drain-drift region.
31. trench metal-insulator as claimed in claim 29-semiconductor device, wherein, described PN junction extends between the sidewall of described first epitaxial loayer and described groove.
32. a groove metal oxide semiconductor field effect transistor comprises:
The substrate of first conductivity type;
First epitaxial loayer of first conductivity type on described substrate, described first epitaxial loayer mixes gentlyer than described substrate;
Second epitaxial loayer of second conductivity type on described first epitaxial loayer, channel shaped are formed in described second epitaxial loayer;
Grid in described groove;
Along the bottom of described groove and the gate insulator of sidewall, described grid is isolated from described second epitaxial loayer electricity by described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described substrate, and forms PN junction with described second epitaxial loayer, and described PN junction extends between described groove and described first epitaxial loayer,
Source area is adjacent to the top surface setting of the sidewall and the described epitaxial loayer of described groove.
33. a method of making trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type is provided;
Form epitaxial loayer on described substrate, described epitaxial loayer is generally second conductivity type;
In described epitaxial loayer, form groove;
In described groove, form sidewall spacers;
Between described sidewall spacers and inject the dopant of described first conductivity type by the bottom of described groove;
Forming bottom insulation layer on the bottom at described groove between the described sidewall spacers;
Remove described sidewall spacers;
Form gate insulator on the sidewall of described groove, described gate insulator is thinner than described bottom insulation layer; With
Electric conducting material is introduced described groove.
34. method as claimed in claim 33, wherein, the formation of described sidewall spacers is included in conformally depositing insulating layer and the directionally next described insulating barrier of removing part in the bottom of described groove of the described insulating barrier of etching in the described groove, and the wall near described groove stays sidewall spacers thus.
35. method as claimed in claim 34, wherein, described insulating barrier comprises nitride.
36. method as claimed in claim 33, wherein, the injection of the dopant of described first conductivity type comprises with a dosage and energy injects dopant, makes after the described injection and does not have substantially under the situation of thermal diffusion, and described dopant extends to described substrate from the bottom of described groove.
37. method as claimed in claim 33, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make described dopant after the described injection form below the bottom that is positioned at groove and do not extend to the zone of first conductivity type of described substrate, described method comprises that also the described epitaxial loayer of heating spreads described dopant downwards, is formed on the drain-drift region of extending between described groove and the described substrate thus.
38. method as claimed in claim 33, wherein, the injection of the dopant of described first conductivity type comprises with dosage and energy injects dopant, make that described dopant forms the deep layer of separating from described groove substantially after the described injection, described method comprises that also the described epitaxial loayer of heating upwards to spread described dopant, is formed on the drain-drift region of extending between the bottom of described groove and the described substrate thus.
39. method as claimed in claim 33, wherein, the injection of the dopant of described first conductivity type comprises:
With the first that a dosage and energy inject dopant, make the first of described dopant after the described injection form the zone of first conductivity type, the zone of described first conductivity type is positioned at the bottom of described groove and does not extend to described substrate; With
Inject the second portion of dopant with dosage and energy, make that the second portion of described dopant forms the deep layer of separating from described groove substantially after the described injection;
Described method also comprises:
Heat described epitaxial loayer and make described first and described second portion merge, be formed on the drain-drift region of extending between the bottom of described groove and the described substrate thus with the first of the described dopant of downward diffusion and the second portion that upwards spreads described dopant.
40. method as claimed in claim 33, wherein, the injection of the dopant of described first conductivity type comprises the described dopant of the different-energy of at least three parts respectively, with the lamination in the continuous zone that forms described first conductivity type, described lamination is formed on the drain-drift region of extending between the bottom of described groove and the described substrate layer.
41. as arbitrary described method in the claim 33 to 40, wherein, the formation of described bottom insulation layer comprises that sedimentary deposit and the described layer of etching form described bottom insulation layer.
42. method as claimed in claim 41, wherein, the deposition of described layer comprises deposited oxide layer.
43. method as claimed in claim 42, wherein, the deposition of described layer comprises by chemical vapour deposition (CVD) comes sedimentary deposit.
44. method as claimed in claim 41, wherein, described bottom insulation layer is a low temperature oxide layer.
45. method as claimed in claim 41, wherein, the deposition of described layer comprises the deposition glassy layer.
46. as arbitrary described method in the claim 33 to 40, wherein, the formation of described bottom insulation layer is included in thermal growth oxide layer on the bottom of described groove.
47. as arbitrary described method in the claim 33 to 40, wherein, the formation of described bottom insulation layer comprises deposition materials, described material is compared the bottom that preferentially is deposited on described groove with described sidewall spacers.
48. trench metal-insulator-semiconductor device comprises:
The substrate of first conductivity type;
The epitaxial loayer of second conductivity type on described substrate, channel shaped are formed in the described epitaxial loayer;
Grid in described groove;
Along the gate insulator of the sidewall of described groove, described grid is isolated from described second epitaxial loayer electricity by described gate insulator;
In the bottom insulation layer of described channel bottom, described bottom insulation layer is thicker than described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described substrate, and forms PN junction with described epitaxial loayer, and described PN junction extends between described groove and described substrate.
49. trench metal-insulator as claimed in claim 48-semiconductor device, wherein, described PN junction is with respect to the internal recess of described drain-drift region.
50. trench metal-insulator as claimed in claim 48-semiconductor device, wherein, described PN junction extends between the sidewall of described substrate and described groove.
51. trench metal-insulator as claimed in claim 48-semiconductor device, wherein, described PN junction is aimed at the edge of described bottom insulation layer.
52. a groove metal oxide semiconductor field effect transistor comprises:
The substrate of first conductivity type;
The epitaxial loayer of second conductivity type on described substrate, channel shaped are formed in described second epitaxial loayer;
Grid in described groove;
Along the gate insulator of the sidewall of described groove, described grid is isolated from described epitaxial loayer electricity by described gate insulator;
In the bottom insulation layer of described channel bottom, described bottom insulation layer is thicker than described gate insulator;
The drain-drift region of first conductivity type, described drain-drift region is extended between the bottom of described groove and described substrate, and forms PN junction with described epitaxial loayer, and described PN junction extends between described groove and described substrate,
Source area is adjacent to the top surface setting of the sidewall and the described epitaxial loayer of described groove.
53. groove metal oxide semiconductor field effect transistor as claimed in claim 52 comprises the threshold value adjustment injection region of described second conductivity type.
54. groove metal oxide semiconductor field effect transistor as claimed in claim 53 comprises this tagma of described second conductivity type, described this tagma is mixed heavylier than described epitaxial loayer.
CNB2003801069396A 2002-12-19 2003-12-15 Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same Expired - Lifetime CN100508210C (en)

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