CN1720617A - Metal core substrate packaging - Google Patents
Metal core substrate packaging Download PDFInfo
- Publication number
- CN1720617A CN1720617A CN200380105243.1A CN200380105243A CN1720617A CN 1720617 A CN1720617 A CN 1720617A CN 200380105243 A CN200380105243 A CN 200380105243A CN 1720617 A CN1720617 A CN 1720617A
- Authority
- CN
- China
- Prior art keywords
- dielectric
- conductive
- hole
- metal
- sheet metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
The present invention provides an apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus for elasticity of the carrier substrate to greater than 20 Gpa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 m and a flexural modulus of elasticity of at least 20 Gpa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.
Description
Invention field
The present invention relates to be used for the carrying substrate of microelectronics Packaging, relate in particular to and have metal-cored carrying substrate.
Background of invention
Microelectronics Packaging comprises the microelectronic core (die) that is electrically connected with the carrying substrate and other elements that are associated, such as electric interconnection, tube core lid (lid), radiating element, and other.An example of microelectronics Packaging is an integrated circuit microprocessor.The carrying substrate provides conductive channel, and the microcircuit of microelectronic core is communicated with (communicate) by these passages with system substrate.System substrate, for example motherboard is the platform that electronic component (such as microelectronics Packaging) interconnects in the above.Described system board provides electrical path, and element is by these channel connections.
Present employed great majority carryings substrates all are based on the organic double compound core, go back the oxygen composite core substrate such as what glass fibre strengthened.This core is as basis or central core, and substrate thin layer (lamina) is applied in thereon.The substrate thin layer is meant material layer or the material sheet that is used to set up the carrying substrate.Have movement carrying substrate that the central cores of dielectric substance is provided, it has outstanding dielectric property, but has the engineering properties that specific encapsulation technology is not expected.Especially, (stiffness) is low for rigidity, and thermal coefficient of expansion (CTE) is higher relatively.Because operation and CTE mismatch, this has caused burden in the interconnection between the carrying substrate of microelectronic core and contained structure load.
There is movement carrying substrate to have the modulus of elasticity of typical 9Gpa.This modulus be not enough to resist microelectronic component in preparation and test process and from the consumer operate and the plug activity the structural load situation that stood.Under some load condition, the carrying substrate is crooked under the rigidity microelectronic core, is added in tension stress, shear stress and/or compression on the interconnection material that element is coupled and on this microelectronic core.For example, the typical load that is suffered from encapsulation assembling can surpass the intensity of interconnection material and the inefficacy that causes being electrically connected, perhaps surpasses the intensity of microelectronic core and causes tube core layering (delaminate).The modulus of elasticity in static bending (flexural modulus ofelasticity) (index of material stiffness) mismatch between microelectronic core and carrying substrate presents in the challenge aspect the microelectronics Packaging reliability.
In addition, having movement carrying substrate not have is enough to resist because the modulus of elasticity in static bending of the bending that mismatch caused of CET between microelectronic core that interconnects and carrying substrate; Usually, warpage (warpage) can be observed.Microelectronic core typically has the CET of about 3ppm/C, has CET in about 16 to 21ppm/C scopes based on the carrying substrate of going back oxygen glass, and this depends on glass fabric, resin system and copper content.The hot driving stress of mismatch affects on CET (thermally driven stress) and can influence the reliability of encapsulation in many aspects.
In some mode, the stress influence that all microelectronic packaging technologies all are subjected to structural load and are caused by the CET mismatch.And opposite with high I/O number of needs and big microelectronics Packaging and microelectronic die sizes, these hot driving stress increase with chip size.Different in conjunction with (TAB) connection (attachment) automatically with wire bond (wirebond) or belt, flip chip array (FCA) encapsulation, for example, require encapsulation technology at the electric interconnection that forms and maintain on whole of microelectronic core between microelectronic core and the carrying substrate.
The stiffener (stiffening plate) that is coupled to the carrying substrate has been used to strengthen the carrying substrate to resist the influence of machinery and heat load.But the use of external reinforcing structure has increased the cost of microelectronics Packaging, and has reduced the total amount that can be used for the surface area that microelectronic core is connected with components and parts on the carrying substrate.
The design and the material characteristics of carrying substrate are played the part of crucial role in the electric property of microelectronics Packaging.Power delivery, voltage decline and electromagnetic interference (EMI) are three in the main misgivings that need to handle on the carrying substrate level.Measure over time by (di/dt) or switching noise with electric current for the performance that exchanges (AC).The core power supply noise is measured in some occasion, and these occasions are called as " first fails ", " second fails " and " the 3rd fails ".First fails usually, and the decoupling capacitance device of (on-package) is eased in decoupling capacitance device by (on-die) on the Gao Frequency tube core effectively is set and the Zhong Frequency encapsulation.Second decoupling zero of failing packed level (package-level) and Di Frequency system substrate influences, and the 3rd fails is influenced by being provided with of system substrate decoupling zero and Voltage Regulator Module (VRM).Require decoupling capacitance and microelectronic core closely approaching, this has reduced the space that can be used for microelectronic core on the carrying substrate.
Because voltage noise and Ldi/dt that the di/dt switch is produced are proportional, the L here represents the electric power loop inductance.Design is critical for microelectronics Packaging to be used to alleviate the power delivery network design of this inductance.In carrying substrate design process, the design aspect of the dish in power supply and ground plane, power supply and grounded circuit (via) and electric capacity correctly are set (in-capacitor pad) requires careful consideration, to guarantee the power delivery loop of low inductance.
The loop inductance of power delivery network is subjected to the position of discrete capacitor and the influence of orientation, and described discrete capacitor is to be used for the various elements of decoupling zero microelectronics Packaging.But at electric capacity, interconnect pads, power supply and ground plane, and the mutual inductance between power supply and the earth bus can reduce total effective inductance of electric capacity significantly.And, need other electric capacity to come the control loop inductance, this has improved the cost and the complexity of microelectronics Packaging.
Because above-mentioned reason and the other reasons of stating below, when reading and understanding this specification, for the person of ordinary skill of the art, it is obvious that following content will become, promptly, just need a kind of microelectronics carrying substrate that can solve limitation that is associated with composite core substrate and the feature of not expecting in significant demand of existence of this area.
The accompanying drawing summary
Fig. 1 is the profile of rigid metal core carrier substrate according to embodiments of the present invention;
Fig. 2 is the profile that known 2-2-2 has movement carrying substrate;
Fig. 3 is the profile according to the rigid metal core carrier substrate of another embodiment of the present invention;
Fig. 4 is the profile according to the rigid metal core carrier substrate of another embodiment of the present invention;
Fig. 5 is the flow chart according to the embodiment of rigid metal core carrier substrate manufacture method of the present invention;
Fig. 6 A-C is according to the rigid metal core carrier substrate of embodiment of the present invention manufacturing profile in the various stages of producing;
Fig. 7 is for movement carrying substrate being arranged and according to metal core carrier substrate of the present invention, simulation and record the performance data table; And
Fig. 8 is to movement carrying substrate and the measured performance data table that gets of metal core carrier substrate according to the present invention are arranged.
Embodiment
In the following detailed description, with reference to the accompanying drawing as this paper part, wherein, same numeral is represented same part all the time, and has shown the specific embodiments that the present invention can implement therein in the mode of explanation.Be to be understood that the embodiment that to utilize other, and under the situation that does not depart from the scope of the invention, can carry out the variation of structure or logic.
Provide carrying substrate and manufacturing to be used for the method that microelectronics Packaging contains the carrying substrate of rigid metal core according to embodiment of the present invention.The movement that has that this carrying substrate is suitable for having than routine carries the bigger modulus of elasticity in static bending of substrate.This carrying substrate comprises sheet metal (metal sheet), and described sheet metal has at least one conductive layer and at least one to make the dielectric layer of described conductive layer and described sheet metal electric insulation at each mask.Conductive layer on each face of sheet metal is by plating through hole (PTH) interconnection, and these through holes extend through sheet metal and dielectric layer, and insulate with described sheet metal.
Fig. 1 is the profile according to the rigid metal carrier substrate 10 of embodiment of the present invention.Carrying substrate 10 comprises metal-cored 110; A dielectric layer 120, first wicking surface, 112 adjacency of it and conductive layer 130 and metal-cored 110; A dielectric layer 121, second wicking surface, 113 adjacency of it and conductive layer 131 and metal-cored 110; And at least one plating through hole (PTH) 100.Each PTH 100 comprises dielectric liner 102, core through-hole wall 114 adjacency of it and conductive liner (liner) 103 and core through hole (CTH) 117.Conductive liner 103 is suitable for setting up electric interconnection between the corresponding conductive layer 130,131 on metal-cored 110 the opposite side.Dielectric liner 102 is suitable for making conductive liner 103 and metal-cored 110 insulation.Provide conductive layer 130,131 on dielectric layer 120,121, to produce predetermined conductive pattern, PTH 100 is isolated mutually.Metal-cored 110 are suitable for having the modulus of elasticity in static bending above 20Gpa.
Fig. 2 is the profile that known 2-2-2 has movement carrying substrate 20.Form contrast with the metal core carrier substrate 10 shown in Fig. 1, this has movement carrying substrate to comprise dielectric core 210; Be formed on 230,232,234 and three dielectric layers 220,222,224 of three conductive layers on the first dielectric core surface 212; Be formed on 231,233,235 and three dielectric layers 221,223,225 of three conductive layers on the second dielectric core surface 223; And at least one PTH 200.Each conductive layer 230,231,232,233,234 is set up and at least one dielectric layer 220,221,222,223,224,225 and/or the first and second dielectric core surfaces, 212,223 adjacency.
Each PTH 200 is included in the conductive liner 203 on the dielectric core through-hole wall 214 of dielectric core through hole 217.Conductive liner 203 is suitable for setting up electric interconnection between the corresponding conductive layer 230,231 on the opposite side of dielectric core 210.Conductive layer 230,231,232,233,234 and dielectric layer 220,221,222,223,224,225 are provided to produce predetermined conductive pattern, described conductive pattern be suitable for carrying substrate 30 inside with and above generation single with the conductive path of isolating.Each PTH200 that forms in dielectric core 210 fills with the bolt 204 of dielectric substance.
The carrying substrate is discerned with the mark of three bit digital usually.For example, be used for the number that as shown in Figure 2 " 2-2-2 " mark that movement carrying substrate is arranged is used to indicate the conductive layer that appears at specific carrying substrate.Second-order digit shows the number of conductive layer in the zone of being crossed by the length of PTH, comprises two conductive layers that directly contact with PTH.The number of the first and the 3rd bit digital representative conductive layer outside the zone of being crossed by PTH.With reference to movement carrying substrate 20 is arranged, middle numeral can identify along the length of PTH 200 two conductive layers 230,231.The conductive layer 232,234 of the either side of the first and the 3rd bit digital representative outside PTH200; 233,235 number.
Referring again to Fig. 1, rigid metal core carrier substrate 10 according to the present invention has the 3 conductive layer marks (X-3-X) of contiguous PTH, and has movement carrying substrate to have 2 (X-2-X).For movement carrying substrate was arranged, such setting provided the benefit of numerous structural and electric aspects, and this is discussed below.
Fig. 3 is the profile according to the 1-3-1 rigid metal core carrier substrate 30 of another embodiment of the present invention.Carrying substrate 30 comprises metal-cored 110; Three dielectric layers 120,122,124 with first wicking surface, 112 adjacency of two conductive layers 130,132 and/or metal-cored 110; Three dielectric layers 121,123,125 with second wicking surface, 123 adjacency of two conductive layers 131,133 and/or metal-cored 110; And at least one PTH 100.Each dielectric layer 120,121,122,123,124,125 is set between a conductive layer 130,131,132,133 and/or metal-cored 110.
Each PTH 100 comprises the dielectric liner 102 with CTH wall 114 adjacency of conductive liner 103 and CTH 117.Conductive liner 103 is adapted at setting up electric interconnection between the corresponding conductive layer 130,131 on metal-cored 110 the opposite side.Dielectric liner 102 is suitable for making conductive liner 103 and metal-cored 110 electric insulations.Each PTH 100 usefulness dielectric substance bolt 104 that are formed in metal-cored 110 is filled.Conductive layer 130,131,132,133 and dielectric layer 120,121,122,123,124,125 are provided to produce predetermined conductive pattern, this conductive pattern be suitable for carrying substrate 30 inside with and above generation single with the conductive path of isolating.Metal-cored 110 are suitable for having the modulus of elasticity in static bending above 20Gpa.
Especially, among a plurality of PTH 100, a PTH 100A is through the 132A of the first electric connection of conductive layer 130 and inter-level interconnects 139 and conductive layer 132 exposures.The one PTH 100A is through the second portion 133A electric connection of conductive layer 131 and inter-level interconnects 139 and conductive layer 133 exposures, and this provides the electrical communication path between carrying substrate first side 32 and carrying substrate second side 34.The interconnection that the 132A of first that exposes and the second portion 133A of exposure are well-suited for electronic component provides interconnect pads (pad), these electronic components such as, but be not limited to: the microelectronic core of formation microelectronic component; Form the interconnection material of BGA Package; And the interconnecting line (pin) that forms the lead-in wire Background Grid array packages.Dielectric layer 124,125 on first and second side 32,34 of carrying substrate is used as anti-layer (solder resist) in some application of carrying substrate 30.
Fig. 4 is the profile according to the 2-3-2 rigid metal core carrier substrate 40 of another embodiment of the present invention.Carrying substrate 40 comprises metal-cored 110; Four dielectric layers 120,122,124,126, first wicking surface, 112 adjacency of they and three conductive layers 130,132,134 and/or metal-cored 110; Four dielectric layers 121,123,125,127, second wicking surface, 123 adjacency of they and three conductive layers 131,133,135 and/or metal-cored 110; And at least one PTH100.Each dielectric layer 120,121,122,123,124,125,126,127 is set between a conductive layer 130,131,132,133,134,135 and/or metal-cored 110.
Each PTH 100 comprises the dielectric liner 102 with CTH wall 114 adjacency of conductive liner 103 and CTH117.Conductive liner 103 is suitable for setting up electric interconnection between the corresponding conductive layer 130,131 on metal-cored 110 the opposite side.Dielectric liner 102 is suitable for making conductive liner 103 and metal-cored 110 electric insulations.Each PTH100 that is formed in metal-cored 110 fills with dielectric substance bolt 104.Conductive layer 130,131,132,133,134,135 and dielectric layer 120,121,122,123,124,125,126,127 are provided to produce predetermined conductive pattern, and this conductive pattern is suitable for inner and/or produce single and the conductive path of isolating above it at carrying substrate 40.Metal-cored 110 are suitable for having the modulus of elasticity in static bending above 20Gpa.
Predetermined pattern in the outer dielectric layer 126,127 forms opening to expose the part of following conductive layer 132,133.The 134A of the first electric connection that the one PTH 100A exposes through conductive layer 130, inter-level interconnects 139 and conductive layer 132 and conductive layer 134.The second portion 135A that conductive layer 135 exposes provides electrical communication path through conductive layer 131, inter-level interconnects 139 and conductive layer 133 between carrying substrate first surface 42 and carrying substrate second surface 44.The 134A of first that exposes and the second portion 135A of exposure are well-suited for the electronic component interconnection interconnect pads are provided, these electronic components such as, but be not limited to: the microelectronic core that forms microelectronic component; Form the interconnection material of BGA Package; And the interconnecting line that forms the lead-in wire Background Grid array packages.
In according to embodiment of the present invention, the metal-cored 110 part 130C through inter-level interconnects 139 and conductive layer 130 are in electric connection.Metal-cored 110 can be used to heat is conducted away from the element that the part 130C with conductive layer 130 interconnects, and the element that interconnects for the part 130C with conductive layer 130 provides power supply, ground connection or bias voltage.
The embodiment of metal core carrier substrate 10,30,40 has been described as dielectric layer and the conductive layer that comprises concrete number.But the number of dielectric layer and conductive layer can suitably be revised according to desired configuration.
Fig. 5 is the flow chart of embodiment of the method for the metal core carrier substrate 10 of explanation shown in Fig. 1 constructed in accordance.This method comprises that the form with sheet metal provides rigid metal core, and this sheet metal has the modulus of elasticity in static bending (502) above 20Gpa.This sheet metal is provided with one or more core through holes (CTH) (504).All deposit dielectric material layer or thin layer (506) in the both sides of sheet metal.Solidify this dielectric substance, wherein dielectric substance at high temperature flows and complete filling CTH, forms dielectric plugs (508) therein.Each dielectric plugs is provided with dielectric via (DTH), and described through hole is arranged in the center (510) of the dielectric plugs of CTH.DTH less than CTH, stays the lining of one deck dielectric substance as CTH on diameter.
Dielectric cover metal-cored (surface that comprises each DTH) deposits conductive material in the predetermined figure, to generate plating through hole (PTH), described through hole is isolated with metal-cored electricity by the dielectric material layer as CTH lining, but with each metal-cored face of dielectric covering on conductive layer electric connection (512).
Fig. 6 A-C is according to the metal core carrier substrate 10 of the embodiment of the inventive method of Fig. 5 profile in each stage of making, as shown in figure 10.Fig. 6 A is metal-cored 110 the profile that is provided with CTH 117.Fig. 6 B is the profile that forms the dielectric substance of dielectric layer 120,121 and the dielectric plugs 111 in each CTH 117.Fig. 6 C is the profile that is provided with each dielectric plugs 111 of DTH 118.DTH 118 has defined dielectric liner 102 on the wall 114 of CTH.Fig. 1 is after dielectric liner 102 and dielectric layer 120,121 have been plated with the electric conducting material that forms PTH 100 and conductive layer 130,130 respectively, the profile of completed rigid metal core carrier substrate.
In according to a further embodiment of the present invention, one or more carrying substrates 10 that other are used from Fig. 1 of dielectric layer and conductive layer are established, to produce rigid metal core carrier substrate, such as the rigid metal core carrier substrate shown in Fig. 3 and 4 30,40, perhaps be suitable for other structures of specific purpose.
Metal-cored 110 provide with the form that has certain thickness, and this thickness has been given the 20Gpa or the bigger modulus of elasticity in static bending.The rigidity of the carrying substrate 10,30,40 that is obtained depends on the modulus of elasticity in static bending and the thickness of material.The embodiment that is suitable for metal-cored 110 metal includes, but are not limited to, and steel, stainless steel, aluminium, copper, and metal laminate plate such as copper-invar (invar)-copper, copper-tungsten-copper, have the thickness that surpasses about 0.2mm.
Selection is used for metal-cored metal and also depends on concrete application.For example, with by the microelectronic core of electrical couplings have metal-cored 110 of roughly the same thermal coefficient of expansion and can reduce thermic stress (thermal inducedstress) to carrying substrate 110.In the another application of rigid metal core carrier substrate, it is selected because of its preferred heat conduction property to be used for metal-cored 110 material.
Use suitable method metal-cored 110 and dielectric plugs 111 in generate CTH 117 and DTH118 respectively, these methods include, but not limited to boring, etching, punching and laser ablation.Machine drilling is not suitable for generating the through hole less than about 150 μ m.Therefore machine drilling only is suitable for large diameter through hole and bigger spacing (pitch) (interval between the through hole).Concerning some are used,, require to adopt advanced person's laser drilling process owing to require diameter under 50mm and littler situation, to have 10,000 PHT 100 of surpassing.Laser drill provides the positional precision of the high production rate of through hole and approximately ± 10 microns.Known laser drilling process can also generate the through hole with minimum wall tapering (wall taper).
Conductive layer comprises the material that is suitable for specific purpose, and these materials include, but not limited to copper, aluminium, gold and silver-colored.Use proper method known in the art with on the dielectric substance of conductive layer deposition in predetermined pattern.Three kinds of suitable methods, and other method comprise addition, half add and subtraction lithographic printing (lithographic technique).Illustrate, semi-additive lithographic technique is used to provide on dielectric liner 102 in the conductive liner 103, and conductive layer also is provided on dielectric layer.(negative) figure photoresist mask (photoresist mask) of bearing is applied on the dielectric layer, for the selective electroplating of electric conducting material provides groove.Plating is deposits conductive material in groove, and conductive liner 103 is provided on dielectric liner 102 simultaneously.After electroplating technology, photoresist mask is removed.
Use the proper method dielectric layer deposition in predetermined pattern in this area, these methods include, but not limited to electrophoretic deposition and lamination.Illustrate, in a kind of method of using lamination, dielectric substance comprises one or more pieces epoxy resin preimpregnation (prepreg) materials, in the hot setting processing procedure, described epoxy resin flows covering metal-cored or conductive layer, and is full of CTH fully, forms dielectric plugs therein.
According to the present invention, dielectric layer is formed by the known dielectric material that is suitable for using.The selection of dielectric substance is according to some desired material properties and device application and fixed.Material character also comprises dielectric constant, thermal endurance except that other.Suitable dielectric substance comprises, but be not limited to, combination, the organic material of thermoplastic layer's stampings (laminates), ABF, BT, polyimides and polyimide laminate, epoxy resin, epoxy resin and other resin materials, above-mentioned combination independent or any and filler comprises textile fabric matrix (woven fiber matrices).
The embodiment of rigid metal core provides to have the metal-cored carrying substrate that modulus of elasticity is at least 20Gpa according to embodiments of the present invention.Carrying substrate according to the present invention has high resistance for deflection under desired load condition, this allows carrying substrate and microelectronic component subsequently and microelectronics Packaging, in the Integration Assembly And Checkout process and in by consumer's plug process, can be processed under the situation that does not need outside reinforcement.Need not to use outside reinforcement the carrying substrate on as microelectronic core and additional device, such as capacitor, provide bigger surface area.
In another embodiment according to the present invention, the rigid metal core with low CTE is used to mate better the CTE of the microelectronic core that is coupled to substrate.This CTE coupling is used for reducing because the die stress that heat load causes.There is the CTE of movement carrying substrate high to about 40ppm/C.The CTE of microelectronic core can be low to moderate about 7ppm/C.Except that other, comprise copper (CTE is 16ppm/C) or comprise that the combination of the rigid metal core of copper alloy (CTE is low to moderate 4.5ppm/C) can be used in the rigid metal core carrier substrate, thereby closer mate the CTE that carries substrate and microelectronic core.
Design and the material characteristics of carrying substrate played the part of the role of key in the electrical property that microelectronics Packaging obtained.Fail (1 with first
StDroop), the noise on the core power supply that records in second decline and the 3rd decline drops to the consideration that minimum is a principle.
Owing to voltage noise and L di/dt (L represents the electric power loop inductance) that the di/dt switch produces are proportional, therefore the power delivery network design of carrying out in order to reduce stray inductance is another crucial aspect of power delivery design, especially at package level.The design of carrying substrate needs careful consideration to guarantee low electric induction power source transmission loop.
Rigid metal core carrier substrate also provides buried capacitance (buried capacitance), and it helps to be reduced in produced simultaneously switching noise on the microelectronic core.Rigid metal core provides low-resistance power supply or ground plane, and it has improved microprocessor the 3rd decline performance.In addition, metallic core means is that the convenience of hole mesopore (via-in-via) design is integrated provides the plating through hole, thereby obtains improved encapsulation loop inductance and the improved microprocessor first decline performance.
The flexibility of improved performance of metal core substrate and design can be so that have possibility that be designed to of less layer, thus the cost of reduction substrate.For example, the 1-3-1 rigid metal core carrier substrate can replace 2-2-2 with lower cost movement carrying substrate.
The flexibility of improved performance of metal core carrier substrate and design can be so that the minimizing of power delivery capacitors becomes possibility.Rigid metal core carrier substrate has than the lower inductance of movement carrying substrate is arranged, and wherein, on a fixing horizontal of properties of product, the quantity of decoupling capacitance device is with respect to there being movement carrying substrate to reduce.
In one embodiment of the invention, rigid metal core provides the path owing to have high-termal conductivity for heat dissipation.In the application that requires thermal management, rigid metal core can be used to disperse and distribute heat.With heat energy from be coupled to the carrying substrate surface the element sucking-off and flow to metal-cored by the conduction approach that forms by metal level and inter-level interconnects.
Fig. 3 and 4 rigid metal core carrier substrate 30,40 are evaluated and compare with the polyimide core carrier substrate 20 (such as shown in Figure 2) of routine.Measure and compare electric performance and whether surmount conventional carrying substrate with the benefit of determining metal core carrier substrate.
The 2-2-2 that Fig. 7 and 8 has presented display standard has movement to carry the data form that substrate is compared with the 2-3-2 rigid metal core carrier substrate of the instruction according to the present invention.Fig. 7 is simulation and measured result's a form, has shown the loop inductance for the reduction of a model unit cell (model unit cell).Also have, rigid metal core carrier substrate presents higher capacitance, lower resistance, and higher resonance frequency.
Fig. 8 is the 2-3-2 rigid metal core carrier substrate, has movement carrying substrate to compare with 2-2-2, along with capacitor is removed, and its first decline, second decline and the 3rd performance comparison result's who fails form.Clearly illustrated for first and failed that the rigid metal core carrier substrate performance of having lacked 5 capacitors is with to have movement to carry substrate similar.In the 3rd decline performance, also seen the advantage of metal core carrier substrate.
Method of the present invention be used for the existing equipment infrastructure compatibility that substrate is made, therefore without any need for the cost of main new equipment.
Though, for the purpose of describing embodiment preferred, illustrate and described specific embodiment for example at this, but those skilled in the art will recognize that a variety of variations and/or be equal to realization, they have been considered to reach same purpose, can substitute shown and the specific embodiments described and do not depart from scope of the present invention.Those skilled in the art will recognize easily that the present invention can carry out in very many embodiments.The application is all modifications or the variation that will cover the embodiment of this discussion.Therefore, should think expressly and only limit the present invention by claims and their equivalent.
Claims (23)
1, a kind of method of making rigid metal core carrier substrate comprises:
Form with sheet metal provides metal-cored, and described sheet metal has first side, relative second side, and at least one through hole, the described metal-cored modulus of elasticity in static bending of 20Gpa at least that has;
Form dielectric layer with the predetermined pattern deposit dielectric material, described deposition is to carry out on described first side, described second side and each through hole, to form dielectric plugs in described through hole;
In described dielectric plugs, form through hole, the diameter of described through hole less than described core through hole to form dielectric liner;
By defining deposits conductive material formation conductive liner on the described dielectric liner of plating through hole, described dielectric liner makes described conductive liner and described metal-cored insulation; And
With predetermined pattern deposits conductive material on described dielectric layer.
2, method as claimed in claim 1, wherein deposit dielectric material on described first side, described second side and described through hole forms dielectric layer on described first side, described second side, and the step of formation dielectric plugs comprises:
Laminated product with dielectric substance covers described first and second sides; And
At high temperature solidify described laminated product, form dielectric layer on described first and second sides, the part layer stampings flow into and fill described through hole.
3, method as claimed in claim 1, also be included on described first and second sides form one or more conductive traces and with predetermined one or more plating through hole electric connections.
4, method as claimed in claim 3 wherein forms one or more conductive traces and comprises with step that predetermined one or more plating through holes conduct on described first and second sides:
Use addition, half add or subtraction plating technic on described first and second sides, forms one or more conductive traces and with one or more plating through hole electric connections of being scheduled to.
5, method as claimed in claim 3 also comprises:
Other one or more dielectrics and/or the conductive layer of deposition on described first and second sides;
Between one or more conductive layers, produce one or more inter-level interconnects; And
Use addition, half add or subtraction plating technic on the predetermined one or more dielectric layers on described first and second sides, form one or more conductive traces and with described one or more inter-level interconnects electric connections.
6, method as claimed in claim 1 wherein provides the step of sheet metal to comprise providing to have the thick sheet metal of at least 200 μ m, and described sheet metal comprises the material that is selected from the group of being made up of copper, silver, aluminium, steel and gold.
7, a kind of method of making metal core substrate comprises:
Form with sheet metal provides metal-cored, and described sheet metal has first side, relative second side, and at least one through hole, the described metal-cored modulus of elasticity in static bending of 100Gpa at least that has;
Laminated product with dielectric substance covers described first and second sides, and each through hole;
At high temperature solidify described laminated product, form dielectric layer on described first and second sides, the part layer stampings flow into and fill described through hole;
Form dielectric via in described bolt, the diameter of described through hole is less than described conductive through hole; And
Depositing conducting layer on each dielectric liner that forms the plating through hole, described dielectric liner makes described conductive layer and described metal-cored insulation.
8, method as claimed in claim 7, also be included on described first and second sides form one or more conductive traces and with predetermined one or more plating through hole electric connections.
9, method as claimed in claim 8 wherein forms one or more conductive traces and comprises with the step of predetermined one or more plating through hole electric connections on described first and second sides:
Use addition, half add or subtraction plating technic on described first and second sides, forms one or more conductive traces and with one or more plating through hole electric connections of being scheduled to.
10, method as claimed in claim 7 wherein provides the step of sheet metal to comprise providing to have the thick sheet metal of at least 200 μ m, and described sheet metal comprises the material that is selected from the group of being made up of copper, silver, aluminium, steel and gold.
11, a kind of method of making metal core carrier substrate comprises:
Form with sheet metal provides metal-cored, and described sheet metal has first side, relative second side, and at least one core through hole, the described metal-cored modulus of elasticity in static bending of 20Gpa at least that has;
Deposit dielectric material on described first side, described second side and in each core through hole forms dielectric layer on described first and second layers, and forms dielectric plugs in each core through hole;
By providing dielectric via to form dielectric liner in described dielectric plugs in each core through hole, described dielectric via is positioned at the center of described core through hole and diameter less than described core through hole; And
Deposits conductive material defines the conductive liner of plating through hole with formation on each dielectric liner, and described dielectric liner makes described conductive liner and described metal-cored insulation.
12, as the method for claim 11, deposit dielectric material on described first side, described second side and described core through hole wherein, forming dielectric layer on described first side, described second side, and the step that forms dielectric plugs in each core through hole comprises:
Laminated product with dielectric substance covers described first and second sides; And
At high temperature solidify described laminated product, to form dielectric layer on described first and second sides, the part layer stampings flow into and fill described through hole.
13, as the method for claim 11, also be included on described first and second sides form one or more conductive layers and with predetermined one or more plating through hole electric connections.
14, as the method for claim 13, wherein be included in and form one or more conductive traces on described first and second sides, to form circuitous pattern in the step that forms one or more conductive layers on described first and second sides.
15, as the method for claim 14, on described first and second sides, form one or more conductive traces, comprise with the step that forms circuitous pattern and to use the technology that is selected from the group of forming by discrete wiring, subtraction, half add and addition lithography technique on described first and second sides, to form one or more conductive traces, with the formation circuitous pattern.
16, as the method for claim 13, also comprise:
Other one or more dielectrics and/or the conductive layer of deposition in the alternative graphic on described first, second side;
Between one or more conductive layers, generate one or more borings;
Deposits conductive material in described boring is so that a conductive layer and another conductive layer electric interconnection; And
Use addition, half add or subtraction plating technic on the predetermined one or more dielectric layers on described first and second sides, form one or more conductive traces and with electric conducting material electric connection in predetermined one or more borings.
17, as the method for claim 11, wherein provide the step of sheet metal to comprise providing to have the thick sheet metal of at least 200 μ m, described sheet metal comprises the material that is selected from the group of being made up of copper, silver, aluminium, steel and gold.
18, a kind of rigid metal core carrier substrate comprises:
Metal-cored, the described metal-cored sheet metal with first side and second side that comprises, described sheet metal have and comprise the thickness in the 200-500 mu m range and have the modulus of elasticity in static bending of 20Gpa at least;
At least one dielectric layer, described at least one dielectric layer cover described first side and described second side;
At least one conductive layer, described at least one conductive layer cover the described dielectric layer on described first side and described second side; And
A plurality of plating through holes, described plating through hole comprises dielectric liner and the conductive liner of lining at the tubulose of described dielectric liner inner surface, described plating through hole extends through described sheet metal and covers described dielectric layer on first and second sides, described conductive liner and the described conductive layer electric connection on first and second sides, described dielectric liner make described sheet metal and the insulation of described conductive liner.
19, as the rigid metal core carrier substrate of claim 18, also comprise:
In addition one or more dielectrics and/or conductive layer, described other one or more dielectrics and/or conductive layer are on described first and second sides; And
At least one inter-level interconnects, described at least one inter-level interconnects between one or more conductive layers or described sheet metal, and with described one or more conductive layers or described sheet metal electric connection.
20, as the rigid metal core carrier substrate of claim 18, wherein said sheet metal comprises the material that is selected from the group of being made up of copper, silver, aluminium, steel and gold.
21, a kind of microelectronic component of the high modulus of elasticity in static bending comprises:
Metal-cored, have at least one on metal-cored and be formed on wherein surplus described, affiliated metal-coredly have the thickness that comprises in the 200-500 mu m range, and the modulus of elasticity in static bending of 20Gpa at least;
At least one dielectric layer, described at least one dielectric layer are arranged on each face of described metal-cored end face and bottom surface;
At least one conductive layer, described at least one conductive layer are arranged on each described dielectric layer;
At least one conductive path, described at least one conductive path is electrically connected described conductive layer, and with described metal-cored electric insulation, described substrate be suitable for microelectronic core electrically with mechanically interconnected; And
Microelectronic core, at least one in described microelectronic core and described at least one conductive layer is electric and mechanically interconnected.
22, as the microelectronic component of the high modulus of elasticity in static bending of claim 21, also comprise at least one inter-level interconnects, described at least one inter-level interconnects between one or more conductive layers or described sheet metal, and with one or more conductive layers or described sheet metal electric connection.
23, as the microelectronic component of the high modulus of elasticity in static bending of claim 21, wherein said sheet metal comprises the material that is selected from the group of being made up of copper, silver, aluminium, steel and gold.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/313,932 US20040107569A1 (en) | 2002-12-05 | 2002-12-05 | Metal core substrate packaging |
| US10/313,932 | 2002-12-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1720617A true CN1720617A (en) | 2006-01-11 |
Family
ID=32468377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200380105243.1A Pending CN1720617A (en) | 2002-12-05 | 2003-10-27 | Metal core substrate packaging |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20040107569A1 (en) |
| EP (1) | EP1568079A1 (en) |
| CN (1) | CN1720617A (en) |
| AU (1) | AU2003302851A1 (en) |
| TW (1) | TWI236098B (en) |
| WO (1) | WO2004053983A1 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409986B (en) * | 2007-10-12 | 2011-03-23 | 富士通株式会社 | Core substrate and manufacturing method thereof |
| WO2013107406A1 (en) * | 2012-01-20 | 2013-07-25 | Huawei Technologies Co., Ltd. | Methods and apparatus for a substrate core layer |
| CN104160497A (en) * | 2011-12-20 | 2014-11-19 | 英特尔公司 | Microelectronic package and stacked microelectronic assembly and computing system containing same |
| CN104661434A (en) * | 2013-11-20 | 2015-05-27 | 昆山苏杭电路板有限公司 | Double-faced aluminum substrate manufacturing process |
| CN105390284A (en) * | 2014-09-01 | 2016-03-09 | 普因特工程有限公司 | Capacitor |
| CN103298243B (en) * | 2006-07-14 | 2016-05-11 | 斯塔布科尔技术公司 | There is the increasing layer printed substrate substrate of the core layer of a forming circuit part |
| CN111199888A (en) * | 2018-11-20 | 2020-05-26 | 奥特斯奥地利科技与***技术有限公司 | Component carrier comprising a PID and method for manufacturing a component carrier |
| CN111224317A (en) * | 2020-04-20 | 2020-06-02 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| WO2021212289A1 (en) * | 2020-04-20 | 2021-10-28 | 深圳市汇顶科技股份有限公司 | Laser emitting apparatus |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060256531A1 (en) * | 2005-05-13 | 2006-11-16 | Intel Corporation | Thermal solution with isolation layer |
| USRE45637E1 (en) | 2005-08-29 | 2015-07-28 | Stablcor Technology, Inc. | Processes for manufacturing printed wiring boards |
| US7701052B2 (en) * | 2005-10-21 | 2010-04-20 | E. I. Du Pont De Nemours And Company | Power core devices |
| KR100797719B1 (en) * | 2006-05-10 | 2008-01-23 | 삼성전기주식회사 | Process for build-up printed circuit board |
| US7935568B2 (en) * | 2006-10-31 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
| US20080302564A1 (en) * | 2007-06-11 | 2008-12-11 | Ppg Industries Ohio, Inc. | Circuit assembly including a metal core substrate and process for preparing the same |
| US20100275971A1 (en) * | 2008-04-04 | 2010-11-04 | Arthur R Zingher | Scalable Dense PV Solar Receiver for High Concentration |
| US8513792B2 (en) * | 2009-04-10 | 2013-08-20 | Intel Corporation | Package-on-package interconnect stiffener |
| TWI449136B (en) * | 2011-04-20 | 2014-08-11 | Cyntec Co Ltd | Metal core printed circuit board and electronic package structure |
| US20120286416A1 (en) * | 2011-05-11 | 2012-11-15 | Tessera Research Llc | Semiconductor chip package assembly and method for making same |
| US10096544B2 (en) * | 2012-05-04 | 2018-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor interconnect structure |
| US9368439B2 (en) * | 2012-11-05 | 2016-06-14 | Nvidia Corporation | Substrate build up layer to achieve both finer design rule and better package coplanarity |
| CN103260345B (en) * | 2013-04-24 | 2016-08-03 | 广东生益科技股份有限公司 | A kind of Metal Substrate metal-clad foil plate and preparation method thereof |
| US9332632B2 (en) | 2014-08-20 | 2016-05-03 | Stablcor Technology, Inc. | Graphene-based thermal management cores and systems and methods for constructing printed wiring boards |
| CN106356351B (en) * | 2015-07-15 | 2019-02-01 | 凤凰先驱股份有限公司 | Board structure and preparation method thereof |
| TWI559410B (en) * | 2016-05-09 | 2016-11-21 | Method for suppressing warpage of materials by differential pressure method | |
| TW201817280A (en) * | 2016-07-06 | 2018-05-01 | 亮銳公司 | Printed circuit board for integrated LED driver |
| US10643943B2 (en) * | 2018-06-25 | 2020-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure, package-on-package structure and manufacturing method thereof |
| CN113261092A (en) * | 2019-03-07 | 2021-08-13 | Skc株式会社 | Package substrate and semiconductor device including the same |
| EP3916771A4 (en) | 2019-03-12 | 2023-01-11 | Absolics Inc. | Packaging substrate and semiconductor device comprising same |
| EP3916772A4 (en) | 2019-03-12 | 2023-04-05 | Absolics Inc. | Packaging substrate, and semiconductor device comprising same |
| US11981501B2 (en) | 2019-03-12 | 2024-05-14 | Absolics Inc. | Loading cassette for substrate including glass and substrate loading method to which same is applied |
| KR102545168B1 (en) * | 2019-03-26 | 2023-06-19 | 삼성전자주식회사 | Interposer and semiconductor package including the same |
| JP7087205B2 (en) | 2019-03-29 | 2022-06-20 | アブソリックス インコーポレイテッド | Packaging glass substrate for semiconductors, packaging substrate for semiconductors and semiconductor devices |
| WO2021040178A1 (en) | 2019-08-23 | 2021-03-04 | 에스케이씨 주식회사 | Packaging substrate and semiconductor device comprising same |
| US11632860B2 (en) * | 2019-10-25 | 2023-04-18 | Infineon Technologies Ag | Power electronic assembly and method of producing thereof |
| EP3855490A3 (en) * | 2020-01-22 | 2021-10-13 | Delta Electronics (Shanghai) Co., Ltd. | Power module |
| EP3855872A1 (en) * | 2020-01-22 | 2021-07-28 | Delta Electronics (Shanghai) Co., Ltd. | Carrier board comprising a metal block |
| CN112739043B (en) * | 2020-11-27 | 2022-04-12 | 惠州市特创电子科技股份有限公司 | Deep etching hole control device of circuit board and preparation method of circuit board |
| CN113260155A (en) * | 2021-04-28 | 2021-08-13 | 珠海越亚半导体股份有限公司 | Substrate with customizable copper core and method of making same |
| CN115621243B (en) * | 2022-12-15 | 2023-04-07 | 北京唯捷创芯精测科技有限责任公司 | Substrate capable of reducing warping stress, packaging structure, electronic product and preparation method |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3934335A (en) * | 1974-10-16 | 1976-01-27 | Texas Instruments Incorporated | Multilayer printed circuit board |
| US5309632A (en) * | 1988-03-28 | 1994-05-10 | Hitachi Chemical Co., Ltd. | Process for producing printed wiring board |
| US5153986A (en) * | 1991-07-17 | 1992-10-13 | International Business Machines | Method for fabricating metal core layers for a multi-layer circuit board |
| JP2819523B2 (en) * | 1992-10-09 | 1998-10-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Printed wiring board and method of manufacturing the same |
| US5509200A (en) * | 1994-11-21 | 1996-04-23 | International Business Machines Corporation | Method of making laminar stackable circuit board structure |
| US5774336A (en) * | 1996-02-20 | 1998-06-30 | Heat Technology, Inc. | High-terminal conductivity circuit board |
| US5847327A (en) * | 1996-11-08 | 1998-12-08 | W.L. Gore & Associates, Inc. | Dimensionally stable core for use in high density chip packages |
| US6229174B1 (en) * | 1997-12-08 | 2001-05-08 | Micron Technology, Inc. | Contact structure for memory device |
| US6225687B1 (en) * | 1999-09-02 | 2001-05-01 | Intel Corporation | Chip package with degassing holes |
| US6430058B1 (en) * | 1999-12-02 | 2002-08-06 | Intel Corporation | Integrated circuit package |
| US6413849B1 (en) * | 1999-12-28 | 2002-07-02 | Intel Corporation | Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor |
| JP2001320171A (en) * | 2000-05-08 | 2001-11-16 | Shinko Electric Ind Co Ltd | Multilayer wiring board and semiconductor device |
| US6826830B2 (en) * | 2002-02-05 | 2004-12-07 | International Business Machines Corporation | Multi-layered interconnect structure using liquid crystalline polymer dielectric |
-
2002
- 2002-12-05 US US10/313,932 patent/US20040107569A1/en not_active Abandoned
-
2003
- 2003-10-27 TW TW092129788A patent/TWI236098B/en not_active IP Right Cessation
- 2003-10-27 EP EP03812777A patent/EP1568079A1/en not_active Withdrawn
- 2003-10-27 AU AU2003302851A patent/AU2003302851A1/en not_active Abandoned
- 2003-10-27 CN CN200380105243.1A patent/CN1720617A/en active Pending
- 2003-10-27 WO PCT/US2003/034159 patent/WO2004053983A1/en not_active Application Discontinuation
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103298243B (en) * | 2006-07-14 | 2016-05-11 | 斯塔布科尔技术公司 | There is the increasing layer printed substrate substrate of the core layer of a forming circuit part |
| US9408314B2 (en) | 2006-07-14 | 2016-08-02 | Stablcor Technology Inc. | Build-up printed wiring board substrate having a core layer that is part of a circuit |
| CN101409986B (en) * | 2007-10-12 | 2011-03-23 | 富士通株式会社 | Core substrate and manufacturing method thereof |
| CN104160497A (en) * | 2011-12-20 | 2014-11-19 | 英特尔公司 | Microelectronic package and stacked microelectronic assembly and computing system containing same |
| WO2013107406A1 (en) * | 2012-01-20 | 2013-07-25 | Huawei Technologies Co., Ltd. | Methods and apparatus for a substrate core layer |
| US10212818B2 (en) | 2012-01-20 | 2019-02-19 | Futurewei Technologies, Inc. | Methods and apparatus for a substrate core layer |
| CN104661434A (en) * | 2013-11-20 | 2015-05-27 | 昆山苏杭电路板有限公司 | Double-faced aluminum substrate manufacturing process |
| CN105390284A (en) * | 2014-09-01 | 2016-03-09 | 普因特工程有限公司 | Capacitor |
| CN105390284B (en) * | 2014-09-01 | 2019-01-04 | 普因特工程有限公司 | Capacitor |
| CN111199888A (en) * | 2018-11-20 | 2020-05-26 | 奥特斯奥地利科技与***技术有限公司 | Component carrier comprising a PID and method for manufacturing a component carrier |
| CN111224317A (en) * | 2020-04-20 | 2020-06-02 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| WO2021212289A1 (en) * | 2020-04-20 | 2021-10-28 | 深圳市汇顶科技股份有限公司 | Laser emitting apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004053983A1 (en) | 2004-06-24 |
| TWI236098B (en) | 2005-07-11 |
| TW200416950A (en) | 2004-09-01 |
| EP1568079A1 (en) | 2005-08-31 |
| AU2003302851A1 (en) | 2004-06-30 |
| US20040107569A1 (en) | 2004-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1720617A (en) | Metal core substrate packaging | |
| JP4546415B2 (en) | Wiring board, ceramic capacitor | |
| JP4119205B2 (en) | Multilayer wiring board | |
| US7682972B2 (en) | Advanced multilayer coreless support structures and method for their fabrication | |
| US6281446B1 (en) | Multi-layered circuit board and method of manufacturing the same | |
| CN100380637C (en) | Wiring board and semiconductor package using the same | |
| US7683266B2 (en) | Circuit board and circuit apparatus using the same | |
| TWI389608B (en) | Component built-in wiring substrate and manufacturing method thereof | |
| US8163642B1 (en) | Package substrate with dual material build-up layers | |
| JP5932056B2 (en) | Method for manufacturing a substrate core layer | |
| US6399896B1 (en) | Circuit package having low modulus, conformal mounting pads | |
| KR20080084800A (en) | Novel integrated circuit support structures and the fabrication thereof | |
| WO2005022965A2 (en) | Expansion constrained die stack | |
| GB2437465A (en) | Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board | |
| KR20090089267A (en) | Semiconductor device manufacturing method, semiconductor device and wiring board | |
| CN108231609A (en) | It will be in component built in items load-bearing part by part fixing structure | |
| CN101192542A (en) | Circuit board structure and its manufacture method | |
| CN101364581A (en) | Loading board construction embedded with chip and preparation thereof | |
| US20200128669A1 (en) | Z-Axis Interconnection With Protruding Component | |
| US6720502B1 (en) | Integrated circuit structure | |
| US20080030965A1 (en) | Circuit board structure with capacitors embedded therein and method for fabricating the same | |
| US11462461B2 (en) | System in package for lower z height and reworkable component assembly | |
| JP2024037141A (en) | Semiconductor package structure with hybrid core structure and method for manufacturing the same | |
| KR20050001930A (en) | Hidensity chip scale package and the manufacturing method thereof | |
| CN1560911A (en) | Manufacturing method of circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |