CN1716908A - Slave device - Google Patents
Slave device Download PDFInfo
- Publication number
- CN1716908A CN1716908A CNA2005100780714A CN200510078071A CN1716908A CN 1716908 A CN1716908 A CN 1716908A CN A2005100780714 A CNA2005100780714 A CN A2005100780714A CN 200510078071 A CN200510078071 A CN 200510078071A CN 1716908 A CN1716908 A CN 1716908A
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- CN
- China
- Prior art keywords
- regularly
- data
- latch
- control signal
- latching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Information Transfer Systems (AREA)
Abstract
The slave device is connected to a master device via a data transfer bus and performs data transfer to/from the master device in accordance with an operation control signal controlled by the master device. The slave device comprises an automatic latch timing setting unit for generating a delay value corresponding to a latch timing used to latch data on the data transfer bus by measuring the time spent until the reference data transmitted from the master device on activation of the slave device is latched, and a latch timing adjustment unit for adjusting the latch timing of the operation control signal based on the delay value generated by the automatic latch timing setting unit.
Description
Technical field
The present invention relates to a kind ofly from device, it carries out/from the transfer of data of the main device that connects via data transmission bus.
Background technology
Fig. 9 is the schematic block diagram according to the generic interface system of correlation technique that uses at main device with under the situation of carrying out transfer of data between the device.As shown in Figure 9, for (inter-device) interface between common unit according to correlation technique, main device 901 is finished data on the data transmission bus as CPU, and control operation control signal such as write operation control signal are with to from installing 902 (for example memories and auxiliary (companion) chips) issue operational order.From installing 902 instructions according to operating control signal, in inside with data latching on transfer bus, thereby realize transfer of data.
In the device of correlation technique, in (intra-device) interface, comprise interface 903 and internal circuit 904 from installing 902.For example, if from main device 901 to carrying out transfer of data from installing 902, then use operating control signal as latching regularly the data latching on the data transmission bus in interface circuit 903, and store latched data in the internal circuit 904 (for example, with reference to JP11-341001A).
The main device 901 that uses in the inter device interface for correlation technique, figure 10 illustrates the system that guarantees data DATA, ADR (address) on (guarantee) data transmission bus at the rising edge of operating control signal (CS, WE), and the trailing edge that figure 11 illustrates at operating control signal (CS, WE) guarantees the data DATA on data transmission bus, the system of ADR.
Thereby, for make from install 902 in data assurance period of main device 901 data on the latch data transfer bus correctly, the system that must consider main device 901 when this device of design specifies and latchs timing.
If the period when being used for the timing of control operation control signal and being different from data on guaranteeing data transmission bus, even on the main device 901 of identical systems, correctly latch data latch regularly also different.
If to each main device 901 and especially customized development is from installing 902, each main device 901 design of then having nothing for it but are latched regularly.If a plurality of main type of device use single from installing 902, unless the period that main device 901 guarantees the data on data transmission bus 920 be complementary from the timing of installing 902 latch datas, otherwise can not be connected to main device from device.Therefore, from install 902 to latch regularly be to reduce from installing the principal element of 902 versatility.
Summary of the invention
The purpose of this invention is to provide a kind of by at random change latch regularly can strengthen from the versatility of device from device.
According to of the present inventionly be one from device and carry out/from the transfer of data of the main device that connects via data transmission bus from device, should comprise from device: latch regularly adjustment component, be used for adjusting main device from the operating control signal of the operation of device and being used for the timing of the data on the latch data transfer bus based on being used for controlling; And memory unit, be used to store the parameter regularly that latchs that is used for postponing by latching regularly adjustment component adjustment via the setting of independently installing.
Utilize this configuration, might be by being provided with delayed data to latch regularly and at random changing and latch regularly via what independently install, this has strengthened from the versatility of device.
According to of the present inventionly be one from device and carry out/from the transfer of data of the main device that connects via data transmission bus from device, should comprise from device: latch regularly adjustment component, be used for adjusting main device from the operating control signal of the operation of device and being used for the timing of the data on the latch data transfer bus based on being used for controlling; And latch and regularly parts are set, be used for the parameter regularly that latchs that is used for postponing by latching regularly adjustment component adjustment being set based on the time of latching in the reference data of when device is activated, measuring.
Utilize this configuration, might regularly and at random change by delayed latch based on the time of latching in the reference data of measuring when device is activated and latch regularly, this has strengthened from the versatility of device.
According to the present invention, latching regularly, adjustment component comprises: be used for via at least one trigger delayed control signal first path, be used to the selector walking around second path in first path and be used between first path and second path, switching.
Utilize this configuration, might dispose under the situation of not using decoder or delay circuit and latch regularly adjustment component, this has reduced from the cost of device.
According to the present invention, need not design from device interface at the main device of each connection, this has strengthened from the versatility of device.
Description of drawings
Fig. 1 is the block diagram that is used to describe the interface system of the first embodiment of the present invention;
Fig. 2 shows the trailing edge that uses operating control signal in the first embodiment of the present invention and changes the situation regularly that latchs as a reference;
Fig. 3 is the block diagram that is used to describe the interface system of the second embodiment of the present invention;
Fig. 4 shows the regularly example configuration of adjustment unit that latchs according to second embodiment;
Fig. 5 shows the regularly configuration of adjustment unit of latching that includes only trigger and selector according to second embodiment;
Fig. 6 latchs the block diagram that the unit regularly is set automatically according to second embodiment;
Fig. 7 latchs the block diagram that unit (8 bit data) regularly is set automatically according to second embodiment;
Fig. 8 shows according to latching automatically in the interface system of second embodiment sequence regularly is set;
Fig. 9 shows the configuration according to the generic interface system of correlation technique;
Figure 10 is illustrated in the sequential chart of the rising edge latch data of operating control signal; And
Figure 11 shows the sequential chart at the trailing edge latch data of operating control signal.
Embodiment
Fig. 1 is the block diagram that is used to describe the interface system of the first embodiment of the present invention.The interface system from device that comprises present embodiment comprises: main device 101 is as CPU and from installing 102 as memory and companion chip.Comprise from installing 102: latch regularly adjustment unit 105, internal storage 106, interface circuit 103 and internal circuit 104.
Latch regularly adjustment unit 105 according to stored parameters in operating control signal such as write operation control signal and the internal storage 106, produce latching regularly of the data that are used on the latch data transfer bus, and will latch and regularly be sent to interface circuit 103.In this practice, by stored parameters in the default internal storage 106 of parameter signalization.Data on the interface circuit 103 latch data transfer bus, and with storage to internal circuit 104.
Fig. 2 shows the trailing edge that uses operating control signal and changes the situation regularly that latchs as a reference.As shown in Figure 2, according to this embodiment, the trailing edge that uses operating control signal CS, WE changes by the inner parameter that changes storage in the internal storage 106 and to latch regularly as a reference.This is DATA, the ADR on the latch data transfer bus stably, and DATA and ADR are merged to from the internal circuit 104 that installs 102.
According to present embodiment, might connect in device, rather than design this in device, latching regularly from device is set.This has strengthened from the versatility of device.
Fig. 3 is the block diagram that is used to describe the interface system of the second embodiment of the present invention.The interface system from device that comprises present embodiment comprises: main device 301 is as CPU and from installing 302 as memory and companion chip.Comprise and latch regularly adjustment unit 305, latch unit 307, interface circuit 303 and internal circuit 304 regularly are set automatically from installing 302.
According to present embodiment be connected to main device 301 from installing 302 via data transmission bus, and according to carry out by the operating control signal of main device 301 controls/from the transfer of data of main device 301.Comprise from installing 302: latch automatically unit 307 regularly is set, be used for by measuring up to having latched when from installing for 302 times that are activated and spent till the reference data that the transmission of Shi Congzhu device comes, produce corresponding to be used on the latch data transfer bus data latch length of delay regularly; With latch regularly adjustment unit 305, be used for the length of delay that unit 307 produced regularly is set adjusts latching regularly of operating control signal based on latching automatically.
According to this embodiment, measurement is up to having latched when from installing for 302 times that are activated and spent till the reference data that the transmission of Shi Congzhu device comes, generation is corresponding to the length of delay that latchs timing that is used for the data on the latch data transfer bus, and latching regularly based on length of delay adjustment operating control signal.This allow system designer main device and from the visit between the device design interface under the transparent situation regularly to the designer.
Fig. 4 shows the regularly example configuration of adjustment unit that latchs according to this embodiment.As shown in Figure 4, latching regularly, adjustment unit 400 comprises: the decoder 404 that the trailing edge that is used for the edge of detecting operation control signal detects piece 402, be used for the setting of parameter 410 to 424 is decoded, be used for the synchronous trigger 451,542,453 of timing that postpones the delay circuit 403 at edge and be used to make signal according to the length of delay by decoder 404 decodings.
Latch regularly the edge of adjustment unit 400 detecting operation control signal in trailing edge detection piece 402, and, be used for latching regularly of latch operation control signal thereby adjust according to postponing the edge by the length of delay that obtains that the setting of parameter 410 to 424 is decoded.
Fig. 5 shows and comprises trigger and as the regularly adjustment unit 500 that latchs of the selector of the circuit that latchs regularly adjustment unit 400.Latch timing adjustment unit 500 and do not comprise delay circuit 403 shown in Fig. 4 and decoder 404, and comprise: 16 grades of triggers 510 of the trigger 554,555 that is connected in series etc.; Be used for by selecting signal through the signal path of 16 grades of triggers 510 with walk around the selector 556 that switches between the signal path of 16 grades of triggers 510; 8 grades of triggers 511 of trigger 557,558 etc. are connected in series; Be used for by selecting signal through the signal path of 8 grades of triggers 511 with walk around the selector 559 that switches between the signal path of 8 grades of triggers 511; 4 grades of triggers 512 of trigger 560,561 etc. are connected in series; Be used for by selecting signal through the signal path of 4 grades of triggers 512 with walk around the selector 562 that switches between the signal path of 4 grades of triggers 512; 2 grades of triggers 513 of trigger 563,564 are connected in series; Be used for by selecting signal through the signal path of 2 grades of triggers 513 with walk around the selector 565 that switches between the signal path of 2 grades of triggers 513; The single-stage trigger 514 that comprises trigger 566; And be used for by selecting signal through the signal path of single-stage trigger 514 with walk around the selector 567 that switches between the signal path of single-stage trigger 514.
The adjustment unit that latchs regularly as shown in Figure 5 is provided with time of delay in conjunction with each that select signal for multistage trigger, thereby does not use decoder or delay circuit just to dispose simple timing adjustment unit.
Fig. 6 illustrates and latchs the example configuration that unit 600 regularly is set automatically according to this embodiment.Automatically latch and regularly unit 600 is set and comprises: input data comparison block 610, the nargin (margin) that has connected data transmission bus keeps delay block 620, latch and parameter IOB (length of delay IOB) 630 regularly is set and to the counter block of its input operation control signal.
Input data comparison block 610 is the data on the latch data transfer bus in order, and in case have latched predetermined data and just keep delay block 620 to nargin and notify and started data latching.Nargin keeps delay block 620 delayed latches and starts regularly, so that keep that allow data stable latchs and parameter IOB 630 regularly is set transmits the timing of latching initiate notification to latching.From nargin keep delay block 620 receive latch initiate notification after, latchs regularly the Counter Value that parameter IOB 630 reads counter block 640 is set, and the output counter value regularly is provided with parameter as latching.The edge of counter block 640 reset operation control signals, and latch automatically in operation and constantly to count when regularly unit 307 being set.
By above operation, automatically latch and unit 307 regularly is set measures the time that till being complementary, is spent as a reference, and the result regularly is provided with parameter and exports as latching from data transmission bus latched data and predetermined data by using operating control signal.
Fig. 7 shows and latchs the example configuration that unit (8 bit data) regularly is set automatically.Regularly be provided with in the unit 700 latching automatically of this embodiment, input data comparison block 710 comprises: the trigger 711a that is used to latch the data that provide from data transmission bus is to 711h; In case with trigger 711a to 711h latched tentation data just open its " with " (AND) circuit 712a, 712b.Nargin keeps delay block 720 and comprises: be used for delayed latch start trigger 712a regularly to 712d, "AND" circuit 722, trigger 723a to 723d and "AND" circuit 724.
Latch and regularly parameter IOB 730 is set and comprises: trigger 731,732, length of delay 1 register 733, length of delay 2 registers 734, comparator 735 and delay time register 736.Comparator 735 compares the value of length of delay 1 register 733 and the value of length of delay 2 registers 734.If length of delay 1 is less than length of delay 2, then comparator 735 stores the value of length of delay 2 registers 734 in the delay time register 336 into.If length of delay 1 is equal to or greater than length of delay 2, then comparator 735 stores the value of length of delay 1 register 733 into delay time register 736.The data that store delay time register 736 into regularly are provided with parameter 702 outputs as latching.
Fig. 8 show by latch automatically regularly be provided with that unit 700 carries out latch the example that sequence regularly is set automatically.As shown in Figure 8, regularly be provided with in the sequence latching automatically, to latching automatically circuit " open-minded " (ON) (step S1) be set regularly from the device notice from main device.Next, notice is used for the auxiliary input (0x55) (step S2) that nargin keeps.Then, the input 1 (0xAA) (step S3) that is used to be provided with, the input 2 (0x55) (step S4) that is used to be provided with, notice latchs automatically circuit " shutoff " (OFF) (step s5) regularly is set.Subsequently, so that being set automatically, definite the latching of circuit regularly come latch data.
According to this embodiment, measurement is up to having latched when from installing for 302 times that are activated and spent till the reference data that the transmission of Shi Congzhu device comes, generation corresponding to be used on the latch data transfer bus data latch length of delay regularly, and adjust latching regularly of operating control signal based on length of delay.This allow system designer main device and from the visit between the device design interface under the transparent situation regularly to the designer.
Adopt the interface system of also supporting from the input of so main device according to of the present invention from device, the data that described main device has operating control signal and data transmission bus guarantee period and are somebody's turn to do from the different specification of device.This interface system is useful as general interface system from device (companion chip).
Claims (3)
1. one kind from device, and it carries out/from the transfer of data of the main device that connects via data transmission bus, should comprise from device:
Latch regularly adjuster, adjust main device from the operating control signal of the operation of device and be used for the timing of the data on the latch data transfer bus based on being used for controlling; With
Memory is used to store and is used for postponing by the parameter regularly that latchs that latchs regularly adjuster adjustment by the setting of independently installing.
2. one kind from device, and it carries out/from the transfer of data of the main device that connects via data transmission bus, should comprise from device:
Latch regularly adjuster, adjust main device from the operating control signal of the operation of device and be used for the timing of the data on the latch data transfer bus based on being used for controlling; With
Latch device regularly is set, the parameter regularly that latchs that is used for postponing by latching regularly adjuster adjustment was set based on the time of latching in the reference data of measuring when device is activated.
3. as claimed in claim 1 or 2 from device, wherein latching regularly, adjuster comprises: be used for via at least one trigger delayed control signal first path, be used to the selector walking around second path in first path and be used between first path and second path, switching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP175103/04 | 2004-06-14 | ||
| JP2004175103A JP2005352936A (en) | 2004-06-14 | 2004-06-14 | Slave device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1716908A true CN1716908A (en) | 2006-01-04 |
Family
ID=35513869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100780714A Pending CN1716908A (en) | 2004-06-14 | 2005-06-14 | Slave device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20060002430A1 (en) |
| JP (1) | JP2005352936A (en) |
| CN (1) | CN1716908A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868567A (en) * | 2011-07-05 | 2013-01-09 | 瑞昱半导体股份有限公司 | Primary and secondary judgment device and primary and secondary judgment method applied in network device |
| CN103259702A (en) * | 2012-02-15 | 2013-08-21 | 英飞凌科技股份有限公司 | System comprising bus, and method to transmit data over bus system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3723340B2 (en) * | 1997-06-26 | 2005-12-07 | 富士通株式会社 | Semiconductor memory device |
| US6556583B1 (en) * | 1998-02-24 | 2003-04-29 | Yokogawa Electric Corporation | Communication system and communication control method |
| US6665316B1 (en) * | 1998-09-29 | 2003-12-16 | Agilent Technologies, Inc. | Organization of time synchronization in a distributed system |
| JP3348432B2 (en) * | 1999-09-14 | 2002-11-20 | 日本電気株式会社 | Semiconductor device and semiconductor storage device |
-
2004
- 2004-06-14 JP JP2004175103A patent/JP2005352936A/en active Pending
-
2005
- 2005-06-10 US US11/149,269 patent/US20060002430A1/en not_active Abandoned
- 2005-06-14 CN CNA2005100780714A patent/CN1716908A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868567A (en) * | 2011-07-05 | 2013-01-09 | 瑞昱半导体股份有限公司 | Primary and secondary judgment device and primary and secondary judgment method applied in network device |
| CN102868567B (en) * | 2011-07-05 | 2015-05-20 | 瑞昱半导体股份有限公司 | Primary and secondary judgment device and primary and secondary judgment method applied in network device |
| CN103259702A (en) * | 2012-02-15 | 2013-08-21 | 英飞凌科技股份有限公司 | System comprising bus, and method to transmit data over bus system |
| CN103259702B (en) * | 2012-02-15 | 2017-06-09 | 英飞凌科技股份有限公司 | System including bus and the method via bus system transmission data |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060002430A1 (en) | 2006-01-05 |
| JP2005352936A (en) | 2005-12-22 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |