CN1716452A - Method for programing single layer compound crystal silicon read-only storage unit - Google Patents
Method for programing single layer compound crystal silicon read-only storage unit Download PDFInfo
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- CN1716452A CN1716452A CN 200410050095 CN200410050095A CN1716452A CN 1716452 A CN1716452 A CN 1716452A CN 200410050095 CN200410050095 CN 200410050095 CN 200410050095 A CN200410050095 A CN 200410050095A CN 1716452 A CN1716452 A CN 1716452A
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Abstract
The present invention provides the operation process of the single layer compound crystal EPROM, and the single layer compound crystal EPROM unit includes P-channel floating grid transistor on N-type well of P-type substrate and N-channel coupling module. The P-channel floating grid transistor includes P+ drain, P+ source, P-channel defined with the P+ drain and the P+ source, tunneling oxide layer on the P-channel and doped polysilicon floating grid on the tunneling oxide layer. The N-channel coupling module includes one polysilicon floating electrode connected electrically to the doped polysilicon floating grid of the P-channel floating grid transistor and coupled capacitively to the controlled doped region formed on the P-type substrate electrically insulated with the N-type well.
Description
Technical field
The present invention is about non-volatile (non-volatile) internal memory of individual layer compound crystal silicon (single-poly) and method of operating thereof, refer to especially that a kind of individual layer compound crystal silicon can electric programmable read-only memory (electricalprogrammable read only memory, EPROM) and the low voltage operating method.Individual layer compound crystal silicon of the present invention can electric programmable read-only memory has the advantage of high density, low voltage operating (can carry out write operation under ± Vcc voltage conditions) and high-speed procedureization.
Background technology
Can electric programmable read-only memory (EPROM) be a kind of non-volatile internal memory of rewritable, that is power supply can also keep the internal memory of the numerical data that writes after removing.But need in the time of will writing data again earlier to do the action eliminated with ultraviolet ray, afterwards just can be on the EPROM cd-rom recorder burned again new content.Its external form can find out obviously that there is a glass sunroof top, is to touch with lighttight paster usually, and data is disappeared.The non-volatile internal memory of this type " single write (One-Time Programmable, the OTP) " internal memory that is otherwise known as sometimes.
Individual layer compound crystal silicon EPROM since can with CMOS processing procedure compatibility, therefore often be used in embedded memory (embedded memory) field, for example, embedded non-volatile internal memory in mixed-signal (mixed-mode) circuit or the microcontroller (micro-controller) or the like.The existing skill that is relevant to individual layer compound crystal silicon EPROM can be considered United States Patent (USP) the 5th in light of actual conditions, 761, No. 126 " adopting the low individual layer compound crystal silicon EPROM memory cell (SINGLE POLY EPROM CELL THAT UTILIZES A REDUCEDPROGRAMMING VOLTAGE TO PROGRAM THE CELL) that voltage writes that writes "; United States Patent (USP) the 6th, 130, No. 840 " tool can erase the transistorized memory cell of this basic internal memory of Fu Laman-bancor (MEMORY CELL HAVING ANERASABLE FROHMANN-BENTCHKOWSKY MEMORY TRANSISTOR) "; And United States Patent (USP) the 6th, 509, No. 606 " with advanced CMOS processing procedure compatible and have reduced size and than the individual layer compound crystal silicon EPROM memory cell (SINGLE POLY EPROM CELL HAVING SMALLER SIZE ANDIMPROVED DATA RETENTION COMPATIBLE WITH ADVANCED CMOS PROCESS) of long letter breath storage power ".
Existing individual layer compound crystal silicon EPROM internal memory still has many shortcomings to wait to improve.At first, existing individual layer compound crystal silicon EPROM internal memory needs to operate under the higher voltage state, at least 6 to 7 volts coupling well (couple well) voltage for example, so just be able to produce enough electric field intensity between tunnel oxide (tunnel oxide) layer, write (programming) that carry out data moves.Because it is many that these operating voltages often are higher than Vcc supply voltage (for example 3.3 volts Vcc for input/output circuitry supplies voltage), therefore only has the tunnel oxide of tens of dusts to cause reliability issues for thickness.In addition, produce these relative higher voltage, just need provide extra high voltage (high-voltage) assembly to cooperate with interlock circuit.Moreover existing individual layer compound crystal silicon EPROM internal storage location accounts for chip area, also denounces greatly for one in its application.
Summary of the invention
Fundamental purpose of the present invention is promptly in the method for operating that a kind of individual layer compound crystal silicon EPROM internal memory is provided, make internal memory be operable in ± the Vcc voltage status under, and need not extra high potential assembly, and occupy less internal storage location area.
According to preferred embodiment of the present invention, the invention provides the method that a kind of sequencing individual layer compound crystal silicon can electric programmable read-only memory (EPROM) unit, this individual layer compound crystal silicon EPROM unit pack contains the aboveground P channel floating grid transistor of N type that is formed at a P type substrate, and a N channel couples assembly; This P channel floating grid transistor includes P
+Drain electrode, P
+Source electrode, by this P
+Drain electrode and P
+The defined P channel of source electrode, be located at the tunnel oxide on this P channel, and be located at the doped polycrystalline silicon floating grid on this tunnel oxide; This N channel couples assembly includes the polysilicon electrode of floating, it is electrically connected the doped polycrystalline silicon floating grid of this P channel floating grid transistor, and this polysilicon is floated electrode capacitance coupling (capacitive couple) to being formed at the suprabasil controlled doping of this P type district, and this controlled doping district and this N type well are electrically isolated.
The inventive method includes: make this P type substrate ground connection (grounding); Make this N type well ground connection; Provide a negative voltage to give this P of this P channel floating grid transistor
+Drain electrode; Make this P of this P channel floating grid transistor
+Source ground (grounding) or float (floating); And provide a positive voltage to give this controlled doping district, and make this Vcc voltage be coupled to this doped polycrystalline silicon floating grid, and produce a coupled voltages near Vcc voltage thereon, cause the P channel of this P channel floating grid transistor closing under (OFF) state, this P
+Drain electrode produces exhaustion region also because band is right to band tunnelling (BTBT) mechanism generation electronics electricity hole with the face that connects of this N type well, and wherein electronics is quickened to inject this P type doped polycrystalline silicon floating grid by this exhaustion region electric field, finishes write activity.
According to another preferred embodiment of the present invention, the inventive method includes: make this P type substrate ground connection; Make this N type well ground connection; Provide-Vcc voltage gives this P of this P channel floating grid transistor
+Drain electrode; Provide a positive voltage to give this P of this P channel floating grid transistor
+Source electrode; And provide+Vcc voltage gives this controlled doping district, makes this Vcc voltage be coupled to this doped polycrystalline silicon floating grid.Wherein, be connected to this P of this P channel floating grid transistor
+Its size of this positive voltage of source electrode needs foot to make this P of this P channel floating grid transistor
+Source electrode, P
+Drain electrode produces parasitic two-carrier transistor (parasiticbipolar junction transistor) with this N type well; This P
+Source electrode is considered as the transistorized emitter of this parasitism two-carrier (Emitter), and this N type well is considered as the transistorized base stage of parasitic two-carrier (Base), and this P
+Drain electrode is considered as the transistorized collector of this parasitism two-carrier (Collector), can produce a collection utmost point-emitter current I simultaneously when this parasitism two-carrier transistor forms
CE, make a large amount of electron streams to this P
+Drain electrode end, and then significantly lifting writes efficient.
Description of drawings
Fig. 1 is for looking synoptic diagram on the individual layer compound crystal silicon EPROM internal memory of the present invention;
Fig. 2 be among Fig. 1 individual layer compound crystal silicon EPROM internal memory along the diagrammatic cross-section of tangent line AA;
Fig. 3 be among Fig. 1 individual layer compound crystal silicon EPROM internal memory along the diagrammatic cross-section of tangent line BB;
Fig. 4 be among Fig. 1 individual layer compound crystal silicon EPROM internal memory along the diagrammatic cross-section of tangent line CC;
Fig. 5 and Fig. 6 illustrate the quick low-voltage write operation method of the individual layer compound crystal silicon EPROM internal memory of another preferred embodiment of the present invention.
Graphic explanation
100 individual layer compound crystal silicon EPROM internal memory 101P channel floating grid transistor
102N channel capacitive coupling assembly 120N type well
122 doped polycrystalline silicon floating grid 124P
+Source electrode
126P
+128 tunnel oxides drain
129P channel 130N channel couples zone
132 polysilicon floating gate 134N
+The control gate polar region
136N
+Control gate polar region 138 dielectric layers
139 contact assembly 142N
-Doped region
152P
+The 200P type substrate of doping contact region
300 parasitic two-carrier transistors
Embodiment
The present invention is about a kind of method of operating of internal memory, the method for operating that is meant especially that the quick low-voltage of individual layer compound crystal silicon EPROM internal memory writes (programmed at high speed and low voltages).Introducing before the low voltage operating method of the present invention, environment and the memory subassembly structure of implementing at the inventive method done a clear explanation earlier.
See also Fig. 1 to Fig. 4, wherein Fig. 1 is for looking synoptic diagram on the individual layer compound crystal silicon EPROM internal memory 100 of the present invention; Fig. 2 is individual layer compound crystal silicon EPROM internal memory 100 diagrammatic cross-sections along tangent line AA among Fig. 1; Fig. 3 is individual layer compound crystal silicon EPROM internal memory 100 diagrammatic cross-sections along tangent line BB among Fig. 1; Fig. 4 is individual layer compound crystal silicon EPROM internal memory 100 diagrammatic cross-sections along tangent line CC among Fig. 1.
At first, as Fig. 1, Fig. 2 and shown in Figure 3, individual layer compound crystal silicon EPROM internal memory 100 of the present invention includes the P that separately is arranged on two spaces in the N type well 120
+ Source electrode 124 and P
+Drain electrode 126, and be defined in P
+Source electrode 124 and P
+ P channel region 129 between the drain electrode 126.P
+Source electrode 124 and P
+(field oxide FOX) completely cuts off with field oxide for drain electrode 126 and P channel region 129.In other embodiments, field oxide also can be by shallow trench isolation layer (shallow trench isolation, STI) replacement.According to preferred embodiment of the present invention, N type well 120 is formed on the P type silicon base 200.Individual layer compound crystal silicon EPROM internal memory 100 includes a tunnel oxide (tunnel oxide) layer 128 in addition, is formed at P
+Source electrode 124 and P
+On the P channel region 129 between the drain electrode 126.One doped polycrystalline silicon floating grid (floating gate) 122 is arranged on tunnel oxide 128.See Fig. 3, P
+Source electrode 124 and P
+Drain electrode 126 promptly is defined in the N type well 120 of doped polycrystalline silicon floating grid 122 both sides.The thickness of tunnel oxide 128 is about 65 dusts (angstrom).
As Fig. 1, Fig. 2 and shown in Figure 4, doped polycrystalline silicon floating grid 122 extends on the field oxide (FOX), and is connected mutually with a polysilicon floating gate 132.According to preferred embodiment of the present invention, polysilicon floating gate 132 is a N type doped polycrystalline silicon.The field oxide (FOX) of polysilicon floating gate 132 cover parts, and stride across a N channel couples zone (N channel coupling area) 130.N channel couples zone 130 is defined in the P type silicon base 200 by field oxide (FOX).Between polysilicon floating gate 132 and P type silicon base 200, be dielectric layer 138, for example a silicon dioxide.According to preferred embodiment of the present invention, dielectric layer 138 is the silicon dioxide layer of thickness 65 dusts, and itself and tunnel oxide 128 form simultaneously.In N channel couples zone 130, lay respectively in the P type silicon base 200 of polysilicon floating gate 132 both sides, be doped with N
+Control grid (control gate) district 134 and 136, wherein N
+Control gate polar region 134 and 136 is electrical connected each other.A plurality of contact assemblies 139 are formed at N
+On the control gate polar region 134 and 136, be connected with outside signal.According to preferred embodiment of the present invention, in the P type silicon base 200 below polysilicon floating gate 132, other is doped with N
-Doped region 142.See Fig. 1 and Fig. 2, P type silicon base 200 sees through a P
+Doping contact region 152 external basic voltage V
SubThus, enforcement environment of the present invention is basically by a P channel floating grid transistor 101, and its floating grid is connected in series a N channel capacitive coupling assembly 102.
Below by Fig. 2 to Fig. 4 the quick low-voltage write operation method of the individual layer compound crystal silicon EPROM internal memory of preferred embodiment of the present invention is described.When writing (programming) operation, the P of P channel floating grid transistor 101
+ Source electrode 124 external one source pole voltage V
SOURCE, P
+126 external drain voltage V drain
DRAIN, N type well 120 external well voltage V
NW, N
+Control gate polar region 134 and 136 external coupled voltages V
COUPLE, and P type silicon base 200 meets a basic voltage V
SubThe preferred embodiment one of according to the present invention, wherein source voltage V
SOURCEBe ground connection (grounded) or float (floating), drain voltage V
DRAINBe negative voltage (Vcc), well voltage V
NWBe ground connection, and coupled voltages V
COUPLEBe positive voltage (Vcc) that wherein Vcc is an input/output voltage, approximately between 3.3 volts to 5 volts.
With input/output voltage Vcc=+3.3 volt is example, and the voltage status when carrying out write operation is as follows: V
COUPLE=+3.3V, V
SOURCE=0V, V
DRAIN=-3.3V, V
NW=0V, and P type silicon base 200 ground connection.Because the area in N channel couples zone is many greater than the area of P channel floating grid transistor 101, therefore, coupling efficiency (coupling ratio) can level off to 1.0.Therefore, by N
+Control gate polar region 134 and 136 is coupled to the voltage of polysilicon floating gate 132 also approaching+3.3V.And because polysilicon floating gate 132 is electrically connected doped polycrystalline silicon floating grid 122 so both equipotentials.Under above-mentioned voltage conditions, see Fig. 3, the P channel 129 of P channel floating grid transistor 101 is still for closing (OFF) state, and because P
+Drain electrode 126 adds negative voltage and (Vcc) forms " counter-rotating bias voltage (reversebias) ", at the P near P channel floating grid transistor 101
+Drain electrode-N type well can produce exhaustion region (depletion region) near connecing face, electronics electricity hole to therefore since band to band tunnelling (band-to-bandtunneling, BTBT) effect produces, wherein electronics quickens to obtain enough kinetic energy via the exhaustion region electric field, pass tunnel oxide 128 and inject doped polycrystalline silicon floating grid 122, finish the action that writes.
See also Fig. 5 and Fig. 6.Individual layer compound crystal silicon EPROM internal memory 100 is along the section diagrammatic sketch of tangent line BB and CC in Fig. 5 and Fig. 6 difference displayed map 1.The quick low-voltage write operation method of the individual layer compound crystal silicon EPROM internal memory of another preferred embodiment of the present invention below promptly is described by Fig. 5 and Fig. 6.Similarly, when carrying out write operation, the P of P channel floating grid transistor 101
+ Source electrode 124 external one source pole voltage V
SOURCE, P
+126 external drain voltage V drain
DRAIN, N type well 120 external well voltage V
NW, N
+Control gate polar region 134 and 136 external coupled voltages V
COUPLE, and P type silicon base 200 meets a basic voltage V
SubAccording to another preferred embodiment of the present invention, wherein source voltage V
SOURCEFor+V
BE, drain voltage V
DRAINBe negative voltage (Vcc), well voltage V
NWBe ground connection (V
NW=0V), and coupled voltages V
COUPLEBe positive voltage (Vcc) that wherein Vcc is an input/output voltage, approximately between 3.3 volts to 5 volts; V
BEIt is a positive voltage greater than 0V.
Be example with input/output voltage Vcc=+3.3 volt equally, the voltage status when carrying out write operation is as follows: V
COUPLE=+3.3V, V
SOURCE=+0.7V, V
DRAIN=-3.3V, V
NW=0V, V
Sub=0V.By N
+Control gate polar region 134 and 136 is coupled to polysilicon floating gate 132+3.3V approaching with the voltage of doped polycrystalline silicon floating grid 122.Under above-mentioned voltage conditions, see Fig. 5, the P channel 129 of P channel floating grid transistor 101 still is a closed condition, and at the P near P channel floating grid transistor 101
+Drain electrode-N type well connects and can produce exhaustion region near the face and electronics electricity hole is right, and wherein thermoelectron can be via band to band tunnelling (BTBT) mechanism, pass tunnel oxide 128 and injects doped polycrystalline silicon floating grid 122, finishes the action that writes.The maximum difference of present embodiment among Fig. 5 and last embodiment is source voltage V
SOURCEFor+V
BE, V wherein
BEBe one greater than the positive voltage of 0V or the positive voltage pulse of short time, 0.7V (actual V for example
BEVoltage need connect face on PN to be decided).V
BEIts size needs foot to make the P of P channel floating grid transistor 101
+ Source electrode 124, P
+Drain electrode 126 produces parasitic two-carrier transistor (parasitic bipolar junction transistor) 300 with N type well 120.Wherein, P
+Source electrode 124 is considered as the emitter (Emitter) of parasitic two-carrier transistor 300, and N type well 120 is considered as the base stage (Base) of parasitic two-carrier transistor 300, and P
+Drain electrode 126 is considered as the collector (Collector) of parasitic two-carrier transistor 300.When forming, parasitic two-carrier transistor 300 can produce collector-emitter current I simultaneously
CE, make a large amount of electron streams to P
+126 ends that drain significantly promote and write efficient.
In addition, the present invention also is operable in V
COUPLEUnder the voltage conditions of=Vcc～2Vcc, look closely the thickness of tunnel oxide and the requiring standard of writing rate and decide.Erasing of individual layer compound crystal silicon EPROM of the present invention unit can be adopted the ultraviolet erasing mode for it, but is not limited thereto, and also may adopt electric erase mode for it in other embodiments.Since writing mechanism of the present invention adopt efficient than the machine-processed high band of channel hot electron (CHE) to band tunnelling (BTBT) mechanism, except advantage, also have the characteristic that high speed writes with the low-voltage of being operable in.
Claims (16)
1. the method for a sequencing individual layer compound crystal silicon ROM unit is characterized in that, this individual layer compound crystal silicon EPROM unit pack contains the aboveground P channel floating grid transistor of N type that is formed at a P type substrate, and a N channel couples assembly; This P channel floating grid transistor includes P
+Drain electrode, P
+Source electrode, by this P
+Drain electrode and P
+The defined P channel of source electrode, be located at the tunnel oxide on this P channel, and be located at the doped polycrystalline silicon floating grid on this tunnel oxide; This N channel couples assembly includes the polysilicon electrode of floating, it is electrically connected the doped polycrystalline silicon floating grid of this P channel floating grid transistor, and this polysilicon electrode capacitance of floating is coupled to and is formed at the suprabasil controlled doping of this P type district, and this controlled doping district and this N type well are electrically isolated; This method includes:
Make this P type substrate ground connection;
Make this N type well ground connection;
Provide a negative voltage to give this P of this P channel floating grid transistor
+Drain electrode;
Make this P of this P channel floating grid transistor
+Source ground or float; And
Provide a positive voltage to give this controlled doping district, make this positive voltage be coupled to this doped polycrystalline silicon floating grid, and produce a coupled voltages near this positive voltage thereon, cause the P channel of this P channel floating grid transistor following in off position, this P
+The face that connects of drain electrode and this N type well produces exhaustion region, and because band is right to the machine-processed electronics electricity hole that produces of band tunnelling, wherein electronics quickens to inject this doped polycrystalline silicon floating grid via this exhaustion region electric field, finishes write activity.
2. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that this positive voltage is a Vcc voltage.
3. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 2 is characterized in that, this Vcc voltage is+3.3 volts I/O supply voltage.
4. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that, this positive voltage is Vcc～2Vcc voltage.
5. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that this negative voltage is-Vcc voltage.
6. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 5 is characterized in that, this negative voltage is-3.3 volts an I/O supply voltage.
7. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that, is a field oxide between this controlled doping district and this N type well.
8. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that, is a shallow trench isolation layer between this controlled doping district and this N type well.
9. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that, this polysilicon of this N channel couples assembly electrode of floating is a N type doped polycrystalline silicon floating electrode.
10. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 1 is characterized in that the thickness of this tunnel oxide is about 65 dusts.
11. the method for a sequencing individual layer compound crystal silicon ROM unit is characterized in that, this individual layer compound crystal silicon EPROM unit pack contains the aboveground P channel floating grid transistor of N type that is formed at a P type substrate, and a N channel couples assembly; This P channel floating grid transistor includes P
+Drain electrode, P
+Source electrode, by this P
+Drain electrode and P
+The defined P channel of source electrode, be located at the tunnel oxide on this P channel, and be located at the doped polycrystalline silicon floating grid on this tunnel oxide; This N channel couples assembly includes the polysilicon electrode of floating, it is electrically connected the doped polycrystalline silicon floating grid of this P channel floating grid transistor, and this polysilicon electrode capacitance of floating is coupled to and is formed at the suprabasil controlled doping of this P type district, and this controlled doping district and this N type well are electrically isolated; This method includes:
Make this P type substrate ground connection;
Make this N type well ground connection;
Provide-Vcc voltage gives this P of this P channel floating grid transistor
+Drain electrode;
Provide a positive voltage to give this P of this P channel floating grid transistor
+Source electrode; And
Provide+Vcc voltage gives this controlled doping district, makes this Vcc voltage be coupled to this doped polycrystalline silicon floating grid.
12. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 11 is characterized in that, is connected to this P of this P channel floating grid transistor
+Its size of this positive voltage of source electrode needs foot to make this P of this P channel floating grid transistor
+Source electrode, P
+Drain electrode produces parasitic two-carrier transistor with this N type well.
13. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 12 is characterized in that this P
+Source electrode is considered as the transistorized emitter of this parasitism two-carrier, and this N type well is considered as the transistorized base stage of parasitic two-carrier, and this P
+Drain electrode is considered as the transistorized collector of this parasitism two-carrier, can produce a collection utmost point-emitter current I simultaneously when this parasitism two-carrier transistor forms
CE, make a large amount of electron streams to this P
+Drain electrode end promotes and writes efficient.
14. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 11 is characterized in that, this positive voltage is about+and 0.7 volt.
15. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 11 is characterized in that, this Vcc voltage is+3.3 volts I/O supply voltage.
16. the method for sequencing individual layer compound crystal silicon ROM unit as claimed in claim 11 is characterized in that the thickness of this tunnel oxide is about 65 dusts.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100500954A CN100538898C (en) | 2004-07-02 | 2004-07-02 | The method of sequencing individual layer compound crystal silicon ROM unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100500954A CN100538898C (en) | 2004-07-02 | 2004-07-02 | The method of sequencing individual layer compound crystal silicon ROM unit |
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| CN100538898C CN100538898C (en) | 2009-09-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320452A (en) * | 2023-11-29 | 2023-12-29 | 合肥晶合集成电路股份有限公司 | Multiple programmable device and preparation method thereof |
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2004
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320452A (en) * | 2023-11-29 | 2023-12-29 | 合肥晶合集成电路股份有限公司 | Multiple programmable device and preparation method thereof |
| CN117320452B (en) * | 2023-11-29 | 2024-04-05 | 合肥晶合集成电路股份有限公司 | Multiple programmable device and preparation method thereof |
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|---|---|
| CN100538898C (en) | 2009-09-09 |
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