CN1716353A - Modulated signal producing circuit, image display device and TV apparatus - Google Patents
Modulated signal producing circuit, image display device and TV apparatus Download PDFInfo
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- CN1716353A CN1716353A CN 200510081089 CN200510081089A CN1716353A CN 1716353 A CN1716353 A CN 1716353A CN 200510081089 CN200510081089 CN 200510081089 CN 200510081089 A CN200510081089 A CN 200510081089A CN 1716353 A CN1716353 A CN 1716353A
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Abstract
The present invention provides a modulation signal generating circuit which generates a modulation signal which has the width corresponding to input tone data. The modulation signal generating circuit comprises an output modulation signal output part and a control circuit. The output part is controlled as setting up the height value of the modulation signal as a preset height value during a first cycle period within a period that one modulation signal is output and setting up the height value of the modulation signal as a height value higher than the preset height value during a second cycle period. The control circuit sets up a maximum time width as being usable for the first period. The control circuit sets up the maximum time width according to a signal produced according to the instruction of the user or sets up the maximum time width according to a signal which indicates the characteristic of the tone data.
Description
Technical field
The present invention is relevant with modulated signal producing circuit and image display.
Background technology
Japanese patent gazette No.11-337909 disclosed a kind of can according to the input the characteristic LCD of image switching tone.
Japanese patent gazette No.6-178153 disclosed a kind of can be according to the gamma correction circuit of image switching gamma correction curve of input.
Japanese patent gazette No.2000-029425 has disclosed the structure of a kind of non-homogeneous pixel clock of use (PCLK).
Japanese patent gazette No.2003-173159 has disclosed the structure that a kind of signal waveform rises in proper order.
Japanese patent gazette No.7-181917 disclosed a kind of can be from control device and the method for the sequence of some point search on the tone voltage response curve with the sequence that obtains having brightness.
Summary of the invention
Desirable is to develop a kind of modulated signal producing circuit that can change the tone characteristic.
According to first aspect, the invention provides the modulated signal producing circuit of the corresponding modulation signal of tone data of a kind of suitable generation time width and input.This modulated signal producing circuit comprises efferent and control circuit of an output modulation signal.The height value of modulation signal was set to a predetermined altitude value during efferent was controlled so as to period 1 in the cycle of a modulation signal of an output, and the height value of modulation signal is set to a height value higher than predetermined altitude value during the second round different with the period 1 in the cycle of this output modulation signal.Control circuit is provided as the maximum time width that the period 1 can use, and control circuit is provided with the maximum time width according to a signal that produces according to user's instruction, perhaps according to a signal of pointing out the characteristic of tone data the maximum time width is set.
According to second aspect, the invention provides the modulated signal producing circuit of the corresponding modulation signal of tone data of a kind of suitable generation time width and input.This modulated signal producing circuit comprises the efferent and the control circuit that produce modulation signal.Efferent comprises the first transistor and transistor seconds.A central electrode of the first transistor is received on first power supply that a height value that is used for modulation signal is set to a predetermined altitude value and another central electrode is received on the output terminal of efferent, and a central electrode of transistor seconds is received on the second source that a height value that is used for modulation signal is set to a height value higher than predetermined altitude value and another central electrode is received on the output terminal of efferent.Conducting during the period 1 of the first transistor in the cycle of a modulation signal of a generation, make output terminal receive state on first power supply to set up one by the first transistor, and conducting during the second round different with the period 1 of transistor seconds in this produces cycle of a modulation signal makes output terminal receive state on the second source by transistor seconds to set up one.Control circuit is provided as the maximum time width that the period 1 can use, and control circuit is provided with the maximum time width according to a signal that produces according to user's instruction, perhaps according to a signal of pointing out the feature of tone data the maximum time width is set.
According to the third aspect, the invention provides a kind of image display, this image display comprises above-mentioned modulated signal producing circuit and the display that the response modulation signal drives.
According to fourth aspect, the invention provides a kind of image display, this image display comprises modulated signal producing circuit and display that the response modulation signal drives of the corresponding modulation signal of tone data of a suitable generation time width and input.Modulated signal producing circuit comprises the efferent and the control circuit that produce modulation signal.Efferent be controlled so as to that the height value of modulation signal during period 1 in the cycle of a modulation signal of an output is set to a predetermined altitude value and during the second round different in the cycle of this output modulation signal with the period 1 height value of modulation signal be set to a height value higher than predetermined altitude value.Control circuit is provided as the maximum time width that the period 1 can use, control circuit is provided with the maximum time width according to a signal that produces according to user's instruction, according to a signal of pointing out the characteristic of tone data the maximum time width is set, perhaps the maximum time width is set according to a signal of pointing out the ambient brightness of image display.
According to the 5th aspect, the invention provides a kind of image display, this image display comprises modulated signal producing circuit and display that the response modulation signal drives of the corresponding modulation signal of tone data of a suitable generation time width and input.Modulated signal producing circuit comprises efferent and control circuit of an output modulation signal.Efferent comprises the first transistor and transistor seconds.A central electrode of the first transistor is received on first power supply that a height value that is used for modulation signal is set to a predetermined altitude value and another central electrode is received on the output terminal of efferent, and a central electrode of transistor seconds is received on the second source that a height value that is used for modulation signal is set to a height value higher than predetermined altitude value and another central electrode is received on the output terminal of efferent.Conducting during the period 1 of the first transistor in the cycle of a modulation signal of a generation, make output terminal receive state on first power supply to set up one by the first transistor, and conducting during the second round different with the period 1 of transistor seconds in this produces cycle of a modulation signal makes output terminal receive state on the second source by transistor seconds to set up one.Control circuit is provided as the maximum time width that the period 1 can use, control circuit is provided with the maximum time width according to a signal that produces according to user's instruction, according to a signal of pointing out the characteristic of tone data the maximum time width is set, perhaps the maximum time width is set according to a signal of pointing out the ambient brightness of image display.
This image display can also comprise that a plurality of sweep traces, a plurality of modulation lines and order are added to sweep circuit on these sweep traces with sweep signal.It is corresponding with these modulation lines that a plurality of modulated signal producing circuits can be configured to.A plurality of displays can be connected with modulation lines by these sweep traces that form matrix circuit.
The invention provides a kind of television equipment, this television equipment comprises the tuner and this image display of a television broadcasting signal.Described image display is from the tuner received signal, the signal display image that provides according to tuner.
According to the present invention, can realize to change the modulated signal producing circuit of tone characteristic.
From below in conjunction with accompanying drawing to being clear that other features and advantages of the present invention the explanation of exemplary embodiments.
Description of drawings
Fig. 1 is the functional-block diagram that illustrates according to the driver element in the image display of one embodiment of the present of invention design.
Fig. 2 is the block scheme that the internal configurations of the modulation circuit in the driver element shown in Figure 1 is shown.
Fig. 3 is the block scheme that the internal configurations of the shift register in the modulation circuit shown in Figure 2 is shown.
Fig. 4 is the block scheme that a circuit of the pwm circuit in the modulation circuit shown in Figure 2 is shown.
Fig. 5 is the circuit diagram that the configuration of the output-stage circuit in the modulation circuit shown in Figure 2 is shown.
Fig. 6 illustration the drive waveforms of the output-stage circuit output in the modulation circuit shown in Figure 2.
Fig. 7 is the block scheme that a falling waveform circuit of the pwm circuit in the modulation circuit shown in Figure 2 is shown.
Fig. 8 illustration according to the selector switch of embodiments of the invention designs.
Fig. 9 illustration an example of used drive waveforms in the driver element according to embodiments of the invention designs.
Figure 10 illustration another example of used drive waveforms in the driver element according to embodiments of the invention designs.
Figure 11 is the block scheme that is shown specifically according to the data conversion circuit in the driver element of embodiments of the invention design.
Figure 12 shows the example of PWM drive waveforms used in the driver element that designs according to embodiments of the invention.
Figure 13 illustrates the value of the drive waveforms data in the PWM drive waveforms example shown in Figure 12 and the curve map of the relation between the tone (brightness).
Figure 14 shows the example of another PWM drive waveforms.
Figure 15 illustrates the value of drive waveforms data in the PWM drive waveforms example shown in Figure 14 and the curve map of the relation between the tone (brightness).
Figure 16 illustration some examples of switch instances signal.
Figure 17 shows an example according to the structure of the televisor of one embodiment of the present of invention design.
Embodiment
A kind of for example is LCD, plasma display or an electron beam display according to the designed image display of the present invention.Especially, the present invention is applicable to the electron beam display that shows many bits.
Fig. 1 is the functional-block diagram that illustrates according to the driver element in the image display of one embodiment of the present of invention design.As shown in Figure 1, driver element comprises modulation circuit A2, sweep circuit A3, timing generator A4, data conversion circuit A5, parallel-to-serial translation circuit A6, composite power source circuit A7 and scanning power circuit A8.Timing generator A4 and data conversion circuit A5 form a data output circuit.Driver element drives the electron source A1 of the image-display units A1 ' of formation image display.Sweep circuit A3 has a plurality of output terminals, receives respectively on the respective scan line (horizontal line) in the image-display units.Modulation circuit A2 has a plurality of output terminals, receives respectively on the corresponding modulation lines (perpendicular line) of image-display units.Sweep trace and modulation lines form matrix circuit.A plurality of display A0 are connected by these matrix circuits.Though these displays are configured in the infall of sweep trace and modulation lines, only show the some of them display for clarity among Fig. 1.According to this embodiment, use electronic emitter as these displays A0.Image-display units has a kind of fluorescent material, and is luminous when being subjected to the irradiation of electronic emitter ejected electron.Luminous along with fluorescent material just formed image.According to this embodiment, use the surface conductive electronic emitter as electronic emitter.According to this embodiment, data conversion circuit A5 changes into a control circuit that produces the state of modulation signal under another modulation signal generation condition as the state that produces modulation signal with under a predetermined modulation signal generation condition.
Data conversion circuit A5 is transformed into the drive waveforms data layout that is fit to modulation circuit A2 with brightness and the used brightness-tone data of tone of external control electron source A1.According to this embodiment, use data conversion circuit A5 as control circuit.Control circuit output relates to the data that step number is set, and these data are used for being provided with the maximum cycle of a predetermined altitude value.Control circuit is also exported the brightness-tone data as pulse-height modulation (PHM) data and pulse-length modulation (PWM) data.The configuration of data conversion circuit A5 will be below in conjunction with Figure 11 explanation.
Parallel-to-serial translation circuit A6 becomes PHM serial data and PWM serial data with the drive waveforms data conversion of data conversion circuit A5 output.
Receive the horizontal line that the sweep circuit A3 on the horizontal line of electron source A1 selects each signal of modulation circuit A2 output to be added to.Though the common execution sequence horizontal scanning of sweep circuit A3, order select horizontal line, scan method to be not limited to the order horizontal scanning one by one.Sweep circuit A3 can carry out staggered scanning, can select a plurality of row, perhaps can select a plane.That is to say, sweep circuit A3 plays a part selecting arrangement, one is selected voltage to be added to horizontal line the preceding paragraph schedule time that a plurality of electron source connected that will drive in these electron sources of electron source A1 and adds one in this section schedule time and do not select voltage, select these lines.
Timing generator A4 produces modulation circuit A2, sweep circuit A3, data conversion circuit A5 and the required timing signal of parallel-to-serial translation circuit A6.
Composite power source circuit A7 exports a plurality of supply voltages, control modulation circuit A2.Though composite power source circuit A7 is a voltage source circuit normally, is not limited thereto.
Scanning power circuit A8 exports a plurality of supply voltages, gated sweep circuit A3.Though scanning power circuit A8 is a voltage source circuit normally, is not limited thereto.
Fig. 2 is the block scheme that the internal configurations of modulation circuit A2 is shown.Below in conjunction with Fig. 2 modulation circuit A2 is described.
Modulation circuit A2 comprises shift register A9, pwm circuit A10 and output-stage circuit A11.
Shift register A9 receives and transmits and obtains PHM serial data and PWM serial data through parallel-to-serial translation circuit A6 conversion, and this is and the corresponding modulating data of the perpendicular line of electron source A1.Pwm circuit A10 produces with the output voltage of output-stage circuit A11 and exports accordingly from the PHM parallel data and the PWM parallel data of shift register A9 reception conduct with the corresponding modulating data of perpendicular line of electron source A1.The timing signal that is used for controlling shift register A9 and pwm circuit A10 is provided by timing generator A4.Output-stage circuit A11 is connected with composite power source circuit A7, the modulation signal that output has the drive waveforms that will illustrate below.
Fig. 3 is the block scheme that the internal configurations of shift register A9 is shown.Below in conjunction with Fig. 3 shift register A9 is elaborated.
Shift register A9 comprises a plurality of control circuit A12 and a plurality of writing circuit A13.Though description control circuit A12 and writing circuit A13 are made up of some delays (D) trigger here, circuit is not limited to this configuration.
The first writing circuit A13-1 receives the PHM serial data that obtains through parallel-to-serial translation circuit A6 conversion, transmit as with the PHM parallel data of the corresponding modulating data of perpendicular line of electron source A1.The second writing circuit A13-1 receives the PWM serial data that obtains through parallel-to-serial translation circuit A6 conversion, transmit as with the PWM parallel data of the corresponding modulating data of perpendicular line of electron source A1.Each control circuit A12 receives the displacement trigger pulse and the shift clock of the timing signal that produces as timing generator A4, produce the record controls signal, be used for as with the perpendicular line (modulation lines) of electron source A1 the PHM serial data and the PWM serial data typing first and second writing circuit A13-1 and the A13-2 of modulating data accordingly.The record controls signal that response control circuit A12 produces is with the PHM serial data typing first writing circuit A13-1, simultaneously with the PWM serial data typing second writing circuit A13-2.
Fig. 4 is for the block scheme as an example of the circuit arrangement that provides for every perpendicular line of the pwm circuit A10 shown in Fig. 2 is provided.Below in conjunction with Fig. 4 pwm circuit A10 is elaborated.Pwm circuit A10 is not limited to the sort circuit configuration.
Pwm circuit A10 comprises PWM parallel data latch cicuit A14, PHM parallel data latch cicuit A15, counting circuit A16, counter initialization signal generating circuit A17, PHM data decode circuitry A18, primary data signalization decoding circuit A19, V1 begins data-carrier store A20, V2 begins data-carrier store A21, V3 begins data-carrier store A22, V4 begins data-carrier store A23, V1 end data storer A24, V2 end data storer A25, V3 end data storer A26, V4 end data storer A27, the V1 end data is selected circuit A28, the V2 end data is selected circuit A29, the V3 end data is selected circuit A30, the V4 end data is selected circuit A31, V1 begins data comparator A32, V2 begins data comparator A33, V3 begins data comparator A34, V4 begins data comparator A35, V1 end data comparer A36, V2 end data comparer A37, V3 end data comparer A38, V4 end data comparer A39, V4 end data comparer A39, the V1 pulse width produces circuit A40, the V2 pulse width produces circuit A41, the V3 pulse width produces circuit A42 and the V4 pulse width produces circuit A43.Though form counter initialization signal generating circuit A17 with d type flip flop and XOR circuit, counter initialization signal generating circuit A17 is not limited to this configuration.
The latch cicuit A14 of PWM parallel data latchs the PWM parallel data, according to the second writing circuit A13-2 in the timing typing shift register A9 of the load signal of a timing signal that produces as timing generator A4, as with the corresponding modulating data of the perpendicular line of electron source A1.The latch cicuit A15 of PHM parallel data latchs the PHM parallel data, according to the first writing circuit A13-1 in the timing typing shift register A9 of the load signal of a timing signal that produces as timing generator A4, as with the corresponding modulating data of the perpendicular line of electron source A1.
Counter initialization signal generating circuit A17 is according to the load signal of the timing signal that produces as timing generator A4 and the PWM clock generating clear signal to the counter of a regulation internal timing.Counting circuit A16 produces counter initialization signal that circuit A17 produces according to the PWM clock sum counter clear signal of a timing signal that produces as timing generator A4 and the enumeration data of regulation internal timing is offered from V1 begins data comparator A32 to these comparers of V4 end data comparer A39.
The PHM parallel data that PHM data decode circuitry A18 latchs according to PHM parallel data latch cicuit A15 produces the selection signal of selecting circuit A28, V2 end data to select circuit A29, V3 end data to select circuit A30 and V4 end data to select circuit A31 to use for the V1 end data.PHM data decode circuitry A18 produces the selection signal of four 2 bit PHM parallel datas.When the PHM parallel data equaled " 00 ", the V1 end data selected the selection signal of circuit A28 to be set to " 1 ", and all the other select the selection signal of circuit to be set to " 0 "." 00 " means a binary value.When the PHM parallel data equaled " 01 ", the V2 end data selected the selection signal of circuit A29 to be set to " 1 ", and all the other select the selection signal of circuit to be set to " 0 ".When the PHM parallel data equaled " 10 ", the V3 end data selected the selection signal of circuit A30 to be set to " 1 ", and all the other select the selection signal of circuit to be set to " 0 ".When the PHM parallel data equaled " 11 ", the V4 end data selected the selection signal of circuit A31 to be set to " 1 ", and all the other select the selection signal of circuit to be set to " 0 ".
Primary data signalization decoding circuit A19 comes order to produce some write signals according to the primary data signalization of a timing signal that produces as timing generator, the PWM parallel data that is used for latch cicuit A14 is latched (being used for being provided with the data of parameters (the maximum time width that can use as the cycle of each height value control) of the condition that forms drive waveforms as some, by sending with the identical path of PWM data) typing V1 begins data-carrier store A20, V2 begins data-carrier store A21, V3 begins data-carrier store A22, V4 begins data-carrier store A23, V1 end data storer A24, V2 end data storer A25, V3 end data storer A26 and V4 end data storer A27.Primary data signalization decoding circuit A19 produces the write signal of eight 3 bit primary data signalizations.When the primary data signalization was set to " 000 ", the write signal that has only V1 to begin data-carrier store A20 was connected, thereby the PWM parallel data typing V1 that PWM parallel data latch cicuit A14 latchs is begun data-carrier store A20.
When the primary data signalization was set to " 001 ", the write signal that has only V2 to begin data-carrier store A21 was connected, thereby the PWM parallel data typing V2 that PWM parallel data latch cicuit A14 latchs is begun data-carrier store A21.
When the primary data signalization was set to " 010 ", the write signal that has only V3 to begin data-carrier store A22 was connected, thereby the PWM parallel data typing V3 that PWM parallel data latch cicuit A14 latchs is begun data-carrier store A22.
When the primary data signalization was set to " 011 ", the write signal that has only V4 to begin data-carrier store A23 was connected, thereby the PWM parallel data typing V4 that PWM parallel data latch cicuit A14 latchs is begun data-carrier store A23.
When the primary data signalization is set to " 100 ", have only the write signal of V1 end data storer A24 to connect, thus the PWM parallel data typing V1 end data storer A24 that PWM parallel data latch cicuit A14 is latched.
When the primary data signalization is set to " 101 ", have only the write signal of V2 end data storer A25 to connect, thus the PWM parallel data typing V2 end data storer A25 that PWM parallel data latch cicuit A14 is latched.
When the primary data signalization is set to " 110 ", have only the write signal of V3 end data storer A26 to connect, thus the PWM parallel data typing V3 end data storer A26 that PWM parallel data latch cicuit A14 is latched.
When the primary data signalization is set to " 111 ", have only the write signal of V4 end data storer A27 to connect, thus the PWM parallel data typing V4 end data storer A27 that PWM parallel data latch cicuit A14 is latched.
(V1 begins data to be used for forming the parameter of following illustrated drive waveforms, V2 begins data, V3 begins data, V4 begins data, the V1 end data, the V2 end data, V3 end data and V4 end data) in the cycle that comprises the unit starting time of display image not or when the user provides the characteristic changing that will transmit these parameters or tone data, order sends each storer (beginning data-carrier store A20 to V4 end data storer A27 from V1) to as brightness-tone data, so that (V1 begins data with these parameters, V2 begins data, V3 begins data, V4 begins data, the V1 end data, the V2 end data, V3 end data and V4 end data) record in these storeies.
PWM parallel data or the V1 end data of record in V1 end data storer A24 that the V1 end data selects circuit (SEL1E_D) A28 to select signal to select PWM parallel data latch cicuit A14 to latch accordingly according to the PHM data that provide with PHM data decode circuitry A18.
PWM parallel data or the V2 end data of record in V2 end data storer A25 that the V2 end data selects circuit (SEL2E_D) A29 to select signal to select PWM parallel data latch cicuit A14 to latch accordingly according to the PHM data that provide with PHM data decode circuitry A18.
PWM parallel data or the V3 end data of record in V3 end data storer A26 that the V3 end data selects circuit (SEL3E_D) A30 to select signal to select PWM parallel data latch cicuit A14 to latch accordingly according to the PHM data that provide with PHM data decode circuitry A18.
PWM parallel data or the V4 end data of record in V4 end data storer A27 that the V4 end data selects circuit (SEL4E_D) A31 to select signal to select PWM parallel data latch cicuit A14 to latch accordingly according to the PHM data that provide with PHM data decode circuitry A18.
V1 begins data comparator (COMP1S) A32 and begins V1 in the data-carrier store A20 and begin to produce a V1 when data conform to the enumeration data of regulation internal timing in the counting circuit A16 and begin pulse being recorded in V1.
V2 begins data comparator (COMP2S) A33 and begins V2 in the data-carrier store A21 and begin to produce a V2 when data conform to the enumeration data of regulation internal timing in the counting circuit A16 and begin pulse being recorded in V2.
V3 begins data comparator (COMP3S) A34 and begins V3 in the data-carrier store A22 and begin to produce a V3 when data conform to the enumeration data of regulation internal timing in the counting circuit A16 and begin pulse being recorded in V3.
V4 begins data comparator (COMP4S) A35 and begins V4 in the data-carrier store A23 and begin to produce a V4 when data conform to the enumeration data of regulation internal timing in the counting circuit A16 and begin pulse being recorded in V4.
V1 end data comparer (COMP1E) A36 produces a V1 and finishes pulse when the V1 end data selects selected V1 end data of circuit A28 or PWM parallel data to conform to the enumeration data of regulation internal timing in the counting circuit A16.
V2 end data comparer (COMP2E) A37 produces a V2 and finishes pulse when the V2 end data selects selected V2 end data of circuit A29 or PWM parallel data to conform to the enumeration data of regulation internal timing in the counting circuit A16.
V3 end data comparer (COMP3E) A38 produces a V3 and finishes pulse when the V3 end data selects selected V3 end data of circuit A30 or PWM parallel data to conform to the enumeration data of regulation internal timing in the counting circuit A16.
V4 end data comparer (COMP4E) A39 produces a V4 and finishes pulse when the V4 end data selects selected V4 end data of circuit A31 or PWM parallel data to conform to the enumeration data of regulation internal timing in the counting circuit A16.
It is a pwm circuit that the V1 pulse width produces circuit (PWM1) A40, export one and begins the pulse width waveform TV1 that V1 that data comparator A32 produces begins that pulse place is risen and finishes pulse place decline at the V1 that V1 end data comparer A36 produces at V1.
It is a pwm circuit that the V2 pulse width produces circuit (PWM2) A41, export one and begins the pulse width waveform TV2 that V2 that data comparator A33 produces begins that pulse place is risen and finishes pulse place decline at the V2 that V2 end data comparer A37 produces at V2.
It is a pwm circuit that the V3 pulse width produces circuit (PWM3) A42, export one and begins the pulse width waveform TV3 that V3 that data comparator A34 produces begins that pulse place is risen and finishes pulse place decline at the V3 that V3 end data comparer A38 produces at V3.
It is a pwm circuit that the V4 pulse width produces circuit (PWM4) A43, export one and begins the pulse width waveform TV4 that V4 that data comparator A35 produces begins that pulse place is risen and finishes pulse place decline at the V4 that V4 end data comparer A39 produces at V4.
An example of above pwm circuit is to receive the beginning pulse to finish reset-set (RS) trigger of pulse as the input that resets as set input and reception.Yet above pwm circuit is not limited to sort circuit.
Fig. 5 is the circuit diagram of configuration that the output-stage circuit A11 of the output unit of formation shown in Fig. 2 is shown.For each perpendicular line all disposes an output-stage circuit A11.As shown in Figure 5, voltage V4 is greater than voltage V3, and voltage V3 is greater than voltage V2.Voltage V2 is greater than voltage V1, and voltage V1 is greater than zero.The pulse width waveform TV1 to TV4 that voltage V1 to V4 responds respectively as the PWM output waveform exports.Pair transistor Q1 to Q3 and transistor Q4 output voltage V 1 respectively export by output terminal when pair transistor Q1 to Q3 and transistor Q4 conducting to V4.Provide power supply and the annexation between the perpendicular line of voltage V1 to V4 to be subjected to control according to the control signal that PWM output waveform TV1 to TV4 produces.These power supplys can be separated independent current sources.Perhaps, also can be to obtain some other power supply with the some of them power supply, for example produce some voltages by electric resistance partial pressure.Specifically, for example a transistorized central electrode is received on the power supply that voltage V1 is provided and another central electrode is received on the perpendicular line.The control signal that obtains from PWM output waveform TV1 to TV4 is added on the gate as the transistorized control utmost point.Usefulness be field effect transistor (FET) time, central electrode is a source electrode and another central electrode is drain electrode.The responsive control signal turn-on transistor just makes voltage V1 be added on the perpendicular line by transistor.Similarly, control signal is added to is connected on each power supply and the transistorized control between the corresponding perpendicular line and extremely goes up and just controlled being connected between power supply and the corresponding perpendicular line.
Fig. 6 illustration the drive waveforms by the output of the output terminal among Fig. 5.Fig. 6 (a) shows the drive waveforms when the PHM data equal " 11 " and working voltage V1 to V4.The rising edge of voltage V1 begins data and determines by being stored in V1 that V1 begins data-carrier store A20, the rising edge of voltage V2 begins V2 in the data-carrier store A21 and begins data and determine by being stored in V2, the rising edge of voltage V3 begins V3 in the data-carrier store A22 and begins data and determine by being stored in V3, and the rising edge of voltage V4 begins V4 in the data-carrier store A23 and begins data and determine by being stored in V4.The negative edge of voltage V1 is determined by the V1 end data that is stored in the V1 end data storer A24, the negative edge of voltage V2 is determined by the V2 end data that is stored in the V2 end data storer A25, the negative edge of voltage V3 is determined by the V3 end data that is stored in the V3 end data storer A26, and the negative edge of voltage V4 is determined by the PWM data.
Fig. 6 (b) shows the drive waveforms when the PHM data equal " 10 " and working voltage V1 to V3.The rising edge of voltage V1 begins data and determines by being stored in V1 that V1 begins data-carrier store A20, the rising edge of voltage V2 begins V2 in the data-carrier store A21 and begins data and determine by being stored in V2, and the rising edge of voltage V3 begins V3 in the data-carrier store A22 and begins data and determine by being stored in V3.The negative edge of voltage V1 is determined that by the V1 end data that is stored in the V1 end data storer A24 negative edge of voltage V2 is determined by the V2 end data that is stored in the V2 end data storer A25, and the negative edge of voltage V3 is determined by the PWM data.
Fig. 6 (c) shows the drive waveforms when the PHM data equal " 01 " and working voltage V1 to V2.The rising edge of voltage V1 begins V1 in the data-carrier store A20 and begins data and determine by being stored in V1, and the rising edge of voltage V2 begins V2 in the data-carrier store A21 and begins data and determine by being stored in V2.The negative edge of voltage V1 is determined by the V1 end data that is stored in the V1 end data storer A24, and the negative edge of voltage V2 is determined by the PWM data.
Fig. 6 (d) shows the drive waveforms when the PHM data equal " 00 " and working voltage V1.The rising edge of voltage V1 begins V1 in the data-carrier store A20 and begins data and determine by being stored in V1.The negative edge of voltage V1 is determined by the PWM data.
Pwm circuit A10 is according to also comprising falling waveform circuit A50 shown in Figure 7 the circuit of this embodiment in Fig. 4.Can select to be provided with the pattern of the rising edge and the negative edge of drive waveforms, also can select the rising edge of drive waveforms to be set and the pattern of the negative edge of drive waveforms is set with the circuit among Fig. 7 with the circuit among Fig. 4 with the circuit among Fig. 4.Just be called the PWM drive pattern below a kind of pattern in back.
Fig. 7 is illustrated in the falling waveform circuit A50 that is used for producing falling waveform in the PWM drive pattern.Falling waveform circuit A50 comprises PWM parallel data latch cicuit A51, PHM parallel data latch cicuit A52, decline step number storer A53, PHM parallel data storer A54, PWM parallel data comparator circuit A55, step number comparator circuit A56, data minus musical instruments used in a Buddhist or Taoist mass A57, PHM counting circuit A58 and pwm pulse width circuit A59.
PWM parallel data latch cicuit A51 latchs the PWM parallel data, according to the timing of the load signal of a timing signal that produces as timing generator A4 with the second writing circuit A13-2 in its typing shift register A9, as with the corresponding modulating data of the perpendicular line of electron source A1.
PHM parallel data latch cicuit A52 latchs the PHM parallel data, according to the timing of the load signal of a timing signal that produces as timing generator A4 with the first writing circuit A13-1 in its typing shift register A9, as with the corresponding modulating data of the perpendicular line of electron source A1.
Decline step number storer A53 response relates to the data of step number as MODE (pattern) signal record of a timing signal of timing generator A4 generation.Relate to of the bus transmission of the data of step number by the PWM parallel data.
PHM parallel data storer A54 record PHM parallel data.
PWM parallel data comparator circuit A55 produces a pulse when the PWM data conform to the enumeration data of regulation internal timing in the counting circuit A16.
Step number comparator circuit A56 is being used for producing a pulse when the enumeration data of the regulation internal timing of each voltage in data that relate to step number that the falling edge of waveform is provided with the output cycle and counting circuit A16 conforms to.
Data minus musical instruments used in a Buddhist or Taoist mass A57 will record the PHM data minus 1 in PHM parallel data storer A54, will store through subtracting 1 value.
PHM counting circuit A58 is to the step-by-step counting of step number comparator circuit A56 output, and as count pulse, signal of output is used for making step number comparator circuit A56 to quit work when count pulse conforms to the value of data minus musical instruments used in a Buddhist or Taoist mass A57 output.
Pwm pulse width circuit A59 exports the value of each voltage from the decline timing and the data minus musical instruments used in a Buddhist or Taoist mass A57 output of the pulse of step number comparator circuit A56 output.
Working condition to these circuit (being shown in Fig. 4 and Fig. 7) describes below.
At display image not and comprise in the cycle of unit starting time, be used for forming the parameter of drive waveforms, V1 to V4 begins data, V1 to V4 end data and relates to the data of step number, and order transmits as brightness-tone data, makes these parameters and data storage in each respective memory.Adjusting step number can make the relative tone data of light characteristic change in following illustrated mode.Though above explanation be make be provided as by cycle of each height value control can with maximum time width data by sending and be stored in circuit arrangement in the pwm circuit with the identical path of brightness-tone data, be not limited to use the sort circuit configuration.Such data can send by a path different with the path of brightness-tone data.
When response MODE signal was selected first drive pattern (the following PWM that also abbreviates as drives), PWM parallel data comparator circuit A55 compared the PWM data with Counter Value.If the PWM data conform to Counter Value, PWM parallel data comparator circuit A55 just to step number comparator circuit A56 and below the selector switch A60 that will illustrate a pulse is provided, start them and carry out work.
Step number comparator circuit A56 will be used for the enumeration data that falling edge at waveform is provided with the regulation internal timing in the data that relate to step number and the counting circuit A16 in output cycle of each voltage and compare.If step count data conforms to enumeration data, step number comparator circuit A56 just provides a pulse to PHM counting circuit A58 and pwm pulse width circuit A59.
PHM counting circuit A58 compares the value of data minus musical instruments used in a Buddhist or Taoist mass A57 output with the umber of pulse of step number comparator circuit A56 output.If this value conforms to umber of pulse, PHM counting circuit A58 just makes step number comparator circuit A56 quit work.If this value does not conform to umber of pulse, PHM counting circuit A58 resets with regard to the Counter Value that makes step number comparator circuit A56, begins to compare with step count data again.
Pwm pulse width circuit A59 receives the pulse of PWM parallel data comparator circuit A55 output.
(1) if equal for example voltage V3 with the value correspondent voltage of PHM data in the data minus musical instruments used in a Buddhist or Taoist mass A57, pwm pulse width circuit A59 is less than or equal to the pulse width waveform TV1 to TV3 of negative edge of the waveform of voltage V3 with regard to output voltage.
(2) if equal for example voltage V2 with the value correspondent voltage of PHM data in the data minus musical instruments used in a Buddhist or Taoist mass A57, pwm pulse width circuit A59 is less than or equal to the pulse width waveform TV1 to TV2 of negative edge of the waveform of voltage V2 with regard to output voltage.
(3) if equal for example voltage V1 with the value correspondent voltage of PHM data in the data minus musical instruments used in a Buddhist or Taoist mass A57, pwm pulse width circuit A59 is with regard to the pulse width waveform TV1 of the negative edge of the waveform of output voltage V 1.
Detect the pulse of step number comparator circuit A56 output, pwm pulse width circuit A59 just operates, and exports a subsequent voltage (lower voltage) at every turn.Repeat this operation, up to drive waveforms arrival point (GND) level, thus the negative edge of the waveform that formation PWM drives.
As shown in Figure 8, the pulse width waveform TV1 to TV3 of falling waveform circuit A50 output is provided for selector switch A60.The PWM output waveform TV1 to TV4 of circuit shown in Figure 4 also offers on the selector switch A60.
In second drive pattern (following also abbreviate as common driving), the PWM output waveform TV1 to TV4 that selector switch A60 provides circuit shown in Figure 4 passes through, thereby PWM output waveform TV1 to TV4 is sent to output stage A11 among Fig. 5.
The situation of selecting PWM to drive to response MODE signal describes below.
The output signal PWM_on that selector switch A60 response PWM parallel data comparator circuit A55 provides carries out work.The concrete working condition of selector switch A60 is as follows:
(1) selector switch A60 is usually in output signal PWM_on input front wheel driving.That is to say that selector switch A60 passes through " the PWM output waveform TV1 to TV4 that circuit shown in Figure 4 provides ".
(2) selector switch A60 selects " the pulse width waveform TV1 to TV3 that falling waveform circuit A50 provides " after receiving output signal PWM_on, exports selected pulse width waveform TV1 to TV3.
Fig. 9 illustration the drive waveforms when response MODE signal selects PWM to drive.Figure 10 illustration with Fig. 6 (a) in identical drive waveforms (common waveform).
In PWM drives, the preceding appearance that (is equipped with hatched among Fig. 9) in the specified position of PWM data be the drive waveforms identical with common waveform.Yet, after the specified position of PWM data (being equipped with hatched among Fig. 9), export the voltage V3 that hangs down one-level than voltage V4 with step number (being 2) in the corresponding time in Fig. 9 at one section.Then, one section with step number (being 2 in Fig. 9) output voltage V 2 in the corresponding time.Repeat same operation and arrive the GND level, thereby form the waveform that PWM drives up to drive waveforms.
Figure 11 is the block scheme that is illustrated in detail in the data conversion circuit A5 shown in Fig. 1 and 2.
In the following description, when operating position signal 1, the place ahead step number that rises up to drive waveforms is set to 4,4 and 4, and when operating position signal 2, the place ahead step number that rises up to drive waveforms is set to 4,64 and 64.That is to say that V1 to V4 begins data and is arranged so that step number is set to above value in the circuit of Fig. 4.Particularly, V2 begins data and is arranged so that height value rises to the value that V1 begins data, and rises to the value that V2 begins data behind four clocks.This setting make as the cycle can with time width be set to the front end of drive waveforms that V1 begins the value of data at height value and be set to four clock period.This is applicable to that equally also V2 to V4 begins the time width of data.The rear step number is set to 4.The rear step number is recorded in the decline step number storer A53 among Fig. 7.
Step number is provided with data 1 A111 and has value 4,4,4,4,4 and 4.
These six values are represented the place ahead step number, the place ahead step number from voltage V2 to voltage V3, the place ahead step number from voltage V3 to voltage V4, the rear step number from voltage V4 to voltage V3, the rear step number from voltage V3 to voltage V2 and the rear step number from voltage V2 to voltage V1 from voltage V1 to voltage V2 respectively.Selector switch A113 selects these values when operating position signal 1.Selector switch A117 regularly selects and exports these values at first of a frame.Step number is provided with the data record in pwm circuit A10.Subsequently according to parameter and brightness data (PWM data or PHM data) output drive waveforms, so that show.Specifically, determine in the step number of each height value appearance before the rising edge of the maximum height value of the drive waveforms of stipulating by the PHM data according to these parameters.Need begin to determine according to the PWM data, and the step number before negative edge appears in each height value lower than the maximum height value of drive waveforms is provided with data according to step number and determines from the timing that the maximum height value of drive waveforms descends.
The optimized map table of above step number is stored in map table 1 A114.When operating position signal 1, the drive waveforms data (PHM data or PWM data) that selector switch A116 selects brightness data to be transformed into by map table 1 A114.Because first the part selector switch A117 outside regularly at this frame selects these values, therefore export with the drive waveforms data (PHM data or PWM data) and the parameter of recording in advance in the storer of pwm circuit A10 with brightness corresponding driving waveform when the operating position signal 1.
It is 4,64,64,4,4 and 4 value that step number is provided with that data 2 A112 have.The data that V1 to V4 begins in data and the decline step number storer A53 are arranged to satisfy this condition.
Because selector switch A113 selects these values when operating position signal 2, so these values are in the first regularly output of frame.The optimized map table of above step number is stored in the map table 2A115.When operating position signal 2, the drive waveforms data that selector switch A116 selects brightness data to be transformed into by map table 2A115.Because the part selector switch A117 outside first timing of frame selects these values, the brightness corresponding driving waveform when therefore output is with operating position signal 2.
Optimized map table 1 A114 and map table 2 A115 will import tone data and be transformed into the drive waveforms data.Value in map table 1 A114 and map table 2 A115 is specified to brightness and the tone data coupling that makes in showing.Therefore, in map table 1 A114 and map table 2 A115, not only consider drive waveforms, and considered for example display characteristic of the fluorescent material of display.According to an alternative embodiment of the invention, can dispose one separately and make the display characteristic of display and the table of tone data coupling, and a plurality of map tables of this embodiment can only be used for switching drive waveforms.
As mentioned above, change and tone number when increasing, for each drive waveforms provides a map table and no matter how display mode changes can keep a predetermined tone characteristic according to drive waveforms switching map table in drive waveforms.
Figure 12 shows PWM drive waveforms example 1.
As shown in figure 12, the rising step number is set to " 4,4 and 4 ", and the decline step number is set to " 4,4 and 4 ".
The position of mobile as shown in Figure 12 PWM data (being equipped with hatched) can form the waveform that PWM drives.
Figure 13 is the curve map that the value of drive waveforms data in the PWM drive waveforms example 1 is shown and shows the relation between the tone (brightness).Brightness is given by the integration to the value of the brightness in the cycle of selecting a line at one.
Owing to the increase along with the value of drive waveforms data of the cycle of height value V1 when the drive waveforms data have 1 to 8 value prolongs, so brightness increases along with the value of drive waveforms data is linear basically.When the drive waveforms data had 9 to 16 value, the cycle of height value V1 accounted for 8 steps (for the upper limit), and the cycle of height value V2 prolongs along with the increase of the value of drive waveforms data.Therefore, brightness increases along with the increase of the value of drive waveforms data is linear basically.Yet, owing to the height value in the part that increases along with the increase of the value of drive waveforms data at time width greater than the height value when the drive waveforms data have 1 to 8 value, therefore represent the drive waveforms data and Z-axis represents that the slope of coordinate system internal characteristic curve of brightness is just steeper at transverse axis.When the drive waveforms data had 17 to 24 value, the cycle of height value V1 accounted for 8 steps (for the upper limit), and the cycle of height value V2 accounts for 8 steps (for the upper limit), and the cycle of height value V3 prolongs along with the increase of the value of drive waveforms data.Therefore, brightness increases along with the increase of the value of drive waveforms data is linear basically.Yet, owing to the height value in the part that increases along with the increase of the value of drive waveforms data at time width greater than the height value when the drive waveforms data have 1 to 8 value and greater than the height value when the drive waveforms data have 9 to 16 value, therefore represent the drive waveforms data and Z-axis represents that the slope of coordinate system internal characteristic curve of brightness is just also steep at transverse axis.Have 25 or during bigger value, the cycle of height value V4 prolongs along with the increase of the value of drive waveforms data in the drive waveforms data.Characteristic line has part also steep of 1 to 24 value in the drive waveforms data in the slope ratio of this part.For fear of providing a unsharp curve, the part that the hypothesis characteristic line has a value of 1 to 24 in the drive waveforms data in Figure 13 has constant slope, although characteristic slope is actually and changes in mode discussed above.
In PWM drive waveforms example 1, the cycle of height value V4 accounts for nearly 999 steps in whole tones (1023).
Figure 14 shows PWM drive waveforms example 2.
As shown in figure 14, the rising step number is set to " 4,64 and 64 ", and the decline step number is set to " 4,4 and 4 ".Therefore, as by cycle of height value V1 control can with the maximum time width be 8 (=4+4).As by cycle of height value V2 control can with the maximum time width be 68 (=64+4).As by cycle of height value V3 control can with the maximum time width be 68 (=64+4).
The position of mobile as shown in Figure 14 PWM data (being equipped with hatched) can form the waveform that PWM drives.
Figure 15 is the curve map that is illustrated in the value of drive waveforms data in the PWM drive waveforms example 2 and shows the relation between the tone (brightness).
Owing in PWM drive waveforms example 2, support many tones at the lower voltage that comprises voltage V2 and voltage V3 before the working voltage V4, therefore can reach outstanding tone rendering in the dark space.
As mentioned above, can be created in the waveform that the dark space has outstanding tone rendering owing to when operating position signal 1, can produce waveform during at operating position signal 2, so situation signal 1 and 2 can use selectively on demand with higher maximum brightness value.
Figure 16 illustration some examples of switch instances signal.
In routine A161, each situation signal switches according to the instruction from the user.For example, situation 1 is preferential corresponding to brightness, and this is called dynamic mode in commercial tv, and situation 2 is soft preferential corresponding to the dark space tone, is called cinema's pattern.The user can select situation 1 or situation 2.The situation number is not limited to two, can be with any a plurality of situations.
In routine A162, the situation signal is identified as film according to video source and is switched.
Be transformed into the 60Hz interlace mode owing to be identified as the video source of a film from the 24Hz progressive scan mode, the personnel that therefore are familiar with this technical field can be from the regularity between the frame with known interlacing-(IP) transform method is discerned film line by line.For example, situation 2 is identified as the situation of a film corresponding to video source by the film recognition device, and situation 1 is corresponding to the situation outside the situation 2.In routine A162, can show the distinctive scotopia of film with outstanding tone rendering does not need the user to operate frequently.
In routine A163, the user is provided with any step number.In a commercial tv, with so-called user adjust 1 and the user adjust 2 assignments and give the situation 1 and 2 that respectively is provided with any step number.The situation number is not limited to two, and any a plurality of situation can be set.
In routine A164, the situation signal switches according to average picture level (APL).For example, the APL value in from 0.3 to 0.6 scope provides and has the well-lit image.Under these circumstances, situation 1 is used for improving brightness.
Since for 0.3 or smaller APL value a dark image is provided, so situation 2 is used for showing this image to darker tone weighting.
Since be 0.6 or bigger APL value owing to automatic brightness limiter (ABL) has suppressed to have the demonstration in the zone of higher brightness, need be, so operating position 2 in the higher zone of the brightness under the situation 1.Make display can realize its function all the time according to APL value switch instances signal.
In routine A165, the situation signal is switched according to ambient brightness.
In routine A165, the illumination in place, surveillance television machine place.Operating position 1 when illumination is higher than predetermined value, and when illumination is lower than predetermined value operating position 2.Though when display brightness changes according to ambient brightness, in relevant technologies, do not consider tone, can change display brightness according to this embodiment of the present invention and do not influence the performance of display
Figure 17 shows the structure of the televisor 804 that uses image display shown in Figure 1.As shown in figure 17, televisor 804 comprises television broadcasting signal tuner 802 and image display as shown in Figure 1 803.Television broadcasting signal 801 is added on the tuner 802.Tuner 802 extracts a desired signal from received signal 801, the signal that is extracted is offered image display 803.The signal display of television programmes that image display 803 provides according to tuner 802.
Though the present invention describes in conjunction with typical embodiment, is understandable that these embodiment that the present invention is not limited to be disclosed.On the contrary, the present invention should be encompassed in various modification and the equivalent in the given the spirit and scope of the present invention of appended claims.The given scope of patent protection of following claims is understood to include the 26S Proteasome Structure and Function of all such modification and equivalence.
Claims (7)
1. modulated signal producing circuit that is suitable for the corresponding modulation signal of tone data of generation time width and input, described modulated signal producing circuit comprises:
The efferent of an output modulation signal, the height value of modulation signal is set to a predetermined altitude value during being controlled so as to the period 1 in the cycle of a modulation signal of an output, and the height value of modulation signal is set to a height value higher than predetermined altitude value during the second round different with the period 1 in the cycle of a modulation signal of this output; And
One be provided as that the period 1 can use maximum time width control circuit, described control circuit is provided with this width according to a signal that produces according to user's instruction maximum time, perhaps according to the signal of the characteristic of an indication tone data this width is set maximum time.
2. modulated signal producing circuit that is suitable for the corresponding modulation signal of tone data of generation time width and input, described modulated signal producing circuit comprises:
The efferent of an output modulation signal; And
A control circuit,
Wherein said efferent comprises the first transistor and transistor seconds,
A central electrode of wherein said the first transistor receive towards a height value that is used for modulation signal be set to a predetermined altitude value first power supply a side and another central electrode is received the side towards the output terminal of efferent,
A central electrode of wherein said transistor seconds receive towards a height value that is used for modulation signal be set to a height value higher than predetermined altitude value second source a side and another central electrode is received the side towards the output terminal of efferent,
Conducting during the period 1 of wherein said the first transistor in the cycle of a modulation signal of a generation, make output terminal receive state on first power supply to set up one by the first transistor, and conducting during the second round different with the period 1 of transistor seconds in this produces cycle of a modulation signal, make output terminal receive state on the second source to set up one by transistor seconds, and
Wherein said control circuit is provided as the maximum time width that the period 1 can use, described control circuit is provided with this width according to a signal that produces according to user's instruction maximum time, perhaps according to the signal of the feature of an indication tone data this width is set maximum time.
3. image display, described image display comprises:
One according to the described modulated signal producing circuit of claim 1; And
The display that the response modulation signal drives.
4. image display, described image display comprises:
A modulated signal producing circuit that is suitable for the corresponding modulation signal of tone data of generation time width and input; And
The display that the response modulation signal drives,
Wherein said modulated signal producing circuit comprises:
The efferent of an output modulation signal, be controlled so as to that the height value of modulation signal during the period 1 in the cycle of a modulation signal of output is set to a predetermined altitude value and during the second round different in the cycle of a modulation signal of this output with the period 1 height value of modulation signal be set to a height value higher than predetermined altitude value; And
One be provided as that the period 1 can use maximum time width control circuit, described control circuit is provided with this width according to a signal that produces according to user's instruction maximum time, according to the signal of characteristic of an indication tone data this width is set maximum time, perhaps this width is set maximum time according to the signal of the ambient brightness of an indicating image display device.
5. image display, described image display comprises:
A modulated signal producing circuit that is suitable for the corresponding modulation signal of tone data of generation time width and input; And
The display that the response modulation signal drives,
Wherein said modulated signal producing circuit comprises:
The efferent of an output modulation signal; And
A control circuit,
Wherein said efferent comprises the first transistor and transistor seconds,
A central electrode of wherein said the first transistor receive towards a height value that is used for modulation signal be set to a predetermined altitude value first power supply a side and another central electrode is received the side towards the output terminal of efferent,
A central electrode of wherein said transistor seconds receive towards a height value that is used for modulation signal be set to a height value higher than predetermined altitude value second source a side and another central electrode is received the side towards the output terminal of efferent,
Conducting during the period 1 of wherein said the first transistor in the cycle of a modulation signal of a generation, make output terminal receive state on first power supply to set up one by the first transistor, and conducting during the second round different with the period 1 of transistor seconds in this produces cycle of a modulation signal, make output terminal receive state on the second source to set up one by transistor seconds, and
Wherein said control circuit is provided as the maximum time width that the period 1 can use, described control circuit is provided with this width according to a signal that produces according to user's instruction maximum time, according to the signal of characteristic of an indication tone data this width is set maximum time, perhaps this width is set maximum time according to the signal of the ambient brightness of an indicating image display device.
6. according to each described image display in the claim 3 to 5, described image display also comprises:
A plurality of sweep traces;
A plurality of modulation lines; And
Order is added to sweep circuit on a plurality of sweep traces with sweep signal,
Wherein a plurality of modulated signal producing circuits are configured to corresponding with a plurality of modulation lines, and
Wherein a plurality of displays are connected with modulation lines by the described a plurality of sweep traces that form matrix circuit.
7. television equipment, described television equipment comprises:
A television broadcasting signal tuner; And
According to each described image display in the claim 3 to 5,
Wherein said image display is from the tuner received signal, with the signal display image that provides according to tuner.
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| JP2004193474 | 2004-06-30 | ||
| JP2004193474 | 2004-06-30 | ||
| JP2005183270 | 2005-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510081089 Pending CN1716353A (en) | 2004-06-30 | 2005-06-29 | Modulated signal producing circuit, image display device and TV apparatus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102892236A (en) * | 2012-10-16 | 2013-01-23 | 深圳市天微电子有限公司 | Driving method and driving circuit of LED (Light-Emitting Diode) |
| CN104347047A (en) * | 2014-11-11 | 2015-02-11 | 深圳市华星光电技术有限公司 | Array substrate, display equipment and driving method thereof |
| CN107919097A (en) * | 2016-10-06 | 2018-04-17 | 佳能株式会社 | Display device and its control method |
| CN109257034A (en) * | 2018-08-30 | 2019-01-22 | 广州金升阳科技有限公司 | A kind of PWM modulation circuit based on data control |
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2005
- 2005-06-29 CN CN 200510081089 patent/CN1716353A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102892236A (en) * | 2012-10-16 | 2013-01-23 | 深圳市天微电子有限公司 | Driving method and driving circuit of LED (Light-Emitting Diode) |
| CN102892236B (en) * | 2012-10-16 | 2015-01-07 | 深圳市天微电子有限公司 | Driving method and driving circuit of LED (Light-Emitting Diode) |
| CN104347047A (en) * | 2014-11-11 | 2015-02-11 | 深圳市华星光电技术有限公司 | Array substrate, display equipment and driving method thereof |
| CN104347047B (en) * | 2014-11-11 | 2016-09-07 | 深圳市华星光电技术有限公司 | Array base palte, display device and driving method thereof |
| CN107919097A (en) * | 2016-10-06 | 2018-04-17 | 佳能株式会社 | Display device and its control method |
| CN107919097B (en) * | 2016-10-06 | 2021-08-10 | 佳能株式会社 | Display device and control method thereof |
| CN109257034A (en) * | 2018-08-30 | 2019-01-22 | 广州金升阳科技有限公司 | A kind of PWM modulation circuit based on data control |
| CN109257034B (en) * | 2018-08-30 | 2022-03-15 | 广州金升阳科技有限公司 | PWM modulation circuit based on data control |
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