CN1713165A - Data communicating circuit of VME bus and DSP processor - Google Patents
Data communicating circuit of VME bus and DSP processor Download PDFInfo
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- CN1713165A CN1713165A CN 200510083982 CN200510083982A CN1713165A CN 1713165 A CN1713165 A CN 1713165A CN 200510083982 CN200510083982 CN 200510083982 CN 200510083982 A CN200510083982 A CN 200510083982A CN 1713165 A CN1713165 A CN 1713165A
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Abstract
A data communication circuit is prepared by connecting VME bus address line to left end address line of double port RAM storage (DPRAMS), its data line to left end data line of DPRAMS, via driver and its control line to left end control line of DPRAMS via bus end logic control chip; connecting DSP processor address line to right end address line of DPRAMS, its data line to right end data line of DPRAMS and its control line to right end control line of DPRAMS via processor end logic control chip; and providing 5V voltage to DPRAMS .
Description
Technical field
The present invention relates to a kind of datel circuit, more particularly be meant, a kind of at the data communication between VME bus and the 16 bit DSP processors, be the innovation datel circuit between a kind of processor and the bus.
Background technology
The VME bus all is used widely at a lot of industrial circles.Its control is very complicated, and cost is very high.Along with the propelling of the electronic technology and the modernization of industry, traditional many cpu datas telecommunication circuit will be by with simple, and datel circuit with low cost replaces.
At present, wherein just utilized VME bus controller characteristic at a high speed, made it to finish the control algolithm of the high-performance complexity of threephase asynchronous for the control of high-power high-performance unsteady flow device system; And because the integrated peripheral hardware that much is suitable for Electric Machine Control on the dsp processor (as the PWM passage etc.); therefore, the control function such as data acquisition, control signal output, system protection and man-machine interaction of high-power high-performance unsteady flow device system are finished by dsp processor.
Dual port RAM is a storer with 2 groups of separate address wires, data line and control lines, and the steering logic that comprises in the sheet can guarantee correctly the carrying out of data, signal communication between the two-shipper (referring to have the equipment of two processors).
Summary of the invention
The datel circuit that the purpose of this invention is to provide a kind of VME bus and dsp processor, described datel circuit can be realized the data communication between the different control system, and solution realizes data communication between VME bus control system and the digital signal processor for the mode by shared storage.
The datel circuit of a kind of VME bus of the present invention and dsp processor, by the VME bus chip, dsp processor, the dual port RAM storer, processor end logic control chip, bus end logic control chip, address driver and data driver constitute, the address wire of VME bus chip connects with the left end address wire of dual port RAM storer behind address driver, the data line of VME bus chip connects with dual port RAM storer left end data line behind data driver, and the control line of VME bus chip connects with dual port RAM storer left end control line behind bus end logic control chip; The address wire of dsp processor connects with the right-hand member address wire of dual port RAM storer, the data line of dsp processor connects with the right-hand member data line of dual port RAM storer, connects with the right-hand member control line of dual port RAM storer behind the treated device end of the control line of the dsp processor logic control chip; Address driver is made up of first address driver and second address driver, and data driver is made up of first data driver and second data driver; System power supply provides the voltage of 5V to the dual port RAM storer.
Described datel circuit, its dual port RAM storer address in the VME bus chip is OOOOH-OFFFH, the address of dual port RAM storer in the DSP storer is COOOH-CFFFH.
The advantage of datel circuit of the present invention: (1) adopts the medium of dual port RAM chip as data communication, replaces original VME bus communication mechanism, has simplified the management of data communication, has reduced the hardware control system cost; (2) communication and the exchange of data can be realized fast, and the transmission quantity of data can be changed.
Description of drawings
Fig. 1 is the structured flowchart of datel circuit of the present invention.
Fig. 2 is the circuit theory diagrams of dsp processor, dual port RAM storer and the processor end logic control chip of datel circuit of the present invention.
Fig. 3 is the circuit theory diagrams of VME bus, address driver, data driver and the bus end logic control chip of datel circuit of the present invention.
Among the figure: 1.VME bus chip 2. dual port RAM storer 3.DSP processors
4. first data driver, 5. second data drivers, 6. first address drivers, 7. second address drivers
8. bus end logic control chip 9. processor end logic control chips
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
See also shown in Figure 1, the present invention is the datel circuit of a kind of VME bus and dsp processor, and described datel circuit is made of VME bus chip 1, dsp processor 3, dual port RAM storer 2, processor end end logic control chip 9, bus end logic control chip 8, address driver and data driver.System power supply provides the voltage of 5V to dual port RAM storer 2.
The address wire of VME bus chip 1 connects with the left end address wire of dual port RAM storer 2 behind address driver, the data line of VME bus chip 1 connects with dual port RAM storer 2 left end data lines behind data driver, and the control line of VME bus chip 1 connects with dual port RAM storer 2 left end control lines behind bus end logic control chip 8.
The address wire of dsp processor 3 connects with the right-hand member address wire of dual port RAM storer 2, the data line of dsp processor 3 connects with the right-hand member data line of dual port RAM storer 2, and the treated device end of the control line of dsp processor 3 logic control chip 9 backs connect with the right-hand member control line of dual port RAM storer 2.
Datel circuit of the present invention has been realized data communication between VME bus chip 1 control system and the dsp processor 3 by the mode of sharing dual port RAM storer 2, and described data transmission is accurately quick, and is with low cost.
In the present invention, address driver is made up of two 8 bi-directional address chip for driving, i.e. first address driver 6 and second address driver 7; Data driver is made up of two 8 bi-directional data chip for driving, i.e. first data driver 4 and second data driver 5.
Among the present invention, first address driver 6 and second address driver 7 are chosen the MC74F245 chip respectively, first data driver 4 and second data driver 5 are chosen the SN74LS245 chip respectively, bus end logic control chip 8 is chosen the GAL20V8B chip, processor end logic control chip 9 is chosen the GAL20V8B chip, dsp processor 3 is chosen the TMS320LF240 chip, and dual port RAM storer 2 is chosen the IDT7024 chip.According to the chip of choosing, below the realization of datel circuit of the present invention will be described by the connection of each terminal.
The data A1 of VME bus chip 1～A8 end connects with data 2～9 ends of first data driver 4, and data 18～11 ends of first data driver 4 connect with left end data 3～11 ends of dual port RAM storer 2;
The data C1 of VME bus chip 1～C8 end connects with data 2～9 ends of second data driver 5, and data 18～11 ends of second data driver 5 connect with left end data 12～20 ends of dual port RAM storer 2.
The connection of above-mentioned terminal has realized that 16 bit data I/O of VME bus chip 1 realize data transmission by first data driver 4 and second data driver, 5 backs with dual port RAM storer 2.
Address output A30～A24, the C30 end of VME bus chip 1 connects with address input 2～9 ends of first address driver 6, and address output 18～11 ends of first address driver 6 connect with left end address input 67～74 ends of dual port RAM storer 2;
The address output C29～C26 end of VME bus chip 1 connects with address input 2～5 ends of second address driver 7, and address output 18～15 ends of second address driver 7 connect with left end address input 75～78 ends of dual port RAM storer 2.
The connection of above-mentioned terminal has realized that the 12 bit address output of VME bus chip 1 realizes that with dual port RAM storer 2 address is connected with second address driver 7 by first address driver 6.
The control of VME bus chip 1 output C14, B20～B16, C23～C27, C28 ,/the AS end connects with control input 1,2～6,7～11,13,14 ends of bus end logic control chip 8 respectively, and control output 23,21,20 ends and the left end of dual port RAM storer 2 of bus end logic control chip 8 controlled and imported 84,80～82,83 ends and connect.
The flow direction of proprietorial selection and data read-write control and data on the address strobe of 1 pair of dual port RAM storer 2 of connection realization VME bus chip of above-mentioned terminal, the sheet.
16 data 2,4,6,8,10,12,14,16,18,20,22,24,26,28,30 of dsp processor 3 and right-hand member data 23～40 ends of 32 ends and dual port RAM storer 2 so connect the data transmission that realizes between dsp processor 3 and the dual port RAM storer 2.
12 addresses output, 1,3,5,7,9,11,13,15,17,19,21 and 23 ends of dsp processor 3 and right-hand member address input 60～49 ends of dual port RAM storer 2 so connect realization dsp processor 3 and connect with address between the dual port RAM storer 2.
Control output 48,40,46 ends of dsp processor 3 connect with control input 4～6 ends of processor end logic control chip 9, and control output 18～14 ends of processor end logic control chip 9 connect with control input 47～45,44,41,42,62 ends of dual port RAM storer 2.The flow direction of proprietorial selection and data read-write control and data on the address strobe of 3 pairs of dual port RAM storeies 2 of connection realization dsp processor like this, the sheet.
In the present invention, having set the address of dual port RAM storer 2 in VME bus chip 1 is OOOOH-OFFFH, and the address of dual port RAM storer 2 in DSP storer 3 is COOOH-CFFFH.Guaranteed can not produce shared conflict that data write between VME bus chip 1 and the DSP storer 3.
In the data communication process of two CPU processors is arranged, exist the storage space contention problem, common solution has following several: (1) hardware plan all has the RDY pin, and inserts corresponding latent period on two CPU; (2) interrupt scheme is supported when needing hardware and software.Promptly the external interrupt input pin at the left and right sides of storer look-at-me output pin and CPU links to each other, and writes corresponding interruption subroutine; (3) semaphore scheme is supported when needing hardware and software equally, also is referred to as " software arbitration ".Its step is for applying for exclusive area, judge whether application is successful, discharging exclusive area.Because two CPU do not use same address simultaneously, so can avoid the generation of contention yet." software arbitration " is meant and specifies a memory block in the storer that uses, and only the CPU for an end uses, and is used for avoiding address arbitration problem.Its step is for applying for exclusive area, judge whether application is successful, discharging exclusive area.Because same address is not used on both sides simultaneously, so can avoid the generation of contention yet.
Adopt semaphore (SEMAPHARE) scheme in the present invention, the reading and writing data that is VME bus chip 1 and 3 pairs of dual port RAM storeies 2 of dsp processor adopts " software arbitration ", when VME bus chip 1 used dual port RAM storer 2, dsp processor 3 was not exercised writing of dual port RAM storer 2 data; When dsp processor 3 used dual port RAM storer 2, VME bus chip 1 was not exercised writing of dual port RAM storer 2 data." software arbitration " mode of employing is controlled to be the use-pattern of sharing dual port RAM storer 2 between VME bus chip 1 and the dsp processor 3: VME bus chip 1 is at first to dual port RAM storer 2 application SEMAPHARE (semaphore), read Shaking_Hands (shaking hands) signal, discharge SEMAPHARE (semaphore), judge whether Shaking_Hands (shaking hands) signal is successful, if read the success of Shaking_Hands (shaking hands) signal, this moment, dual port RAM storer 2 was only for 1 use of VME bus chip.If Shaking_Hands (shaking hands) signal is unsuccessful, VME bus chip 1 withdraws from the application SEMAPHARE (semaphore) that reads and writes data to twoport RM storer 2, does not promptly use dual port RAM storer 2.Putting Shaking_Hands (shaking hands) signal is FFH, discharges SEMAPHARE (semaphore), withdraws from interrupt routine.In software scale value (entering interruption once), realized like this every data of the individual some read-write of n (n 〉=1) every 200us, be after VME bus chip 1 every interruption n time, just read and write the data in the dual port RAM storer 2 one time, and upgrade Shaking_Hands (shaking hands) signal.Thereby dsp processor also is that n 200us writes a secondary data, just reads and writes the data in the dual port RAM storer 2 one time, has guaranteed that VME bus chip 1 and dsp processor 3 read and write data can not conflict.
Datel circuit of the present invention is shared dual port RAM storer 2 by VME bus chip 1 and dsp processor 3 and is replaced original VME bus chip 1 communication mechanism, has simplified the management of data communication, has reduced the hardware control system cost; And can realize the communication and the exchange of data fast, and can change the transmission quantity of data.
Claims (3)
1, the datel circuit of a kind of VME bus and dsp processor, it is characterized in that: constitute by VME bus chip (1), dsp processor (3), dual port RAM storer (2), processor end logic control chip (9), bus end logic control chip (8), address driver and data driver
The address wire of VME bus chip (1) connects with the left end address wire of dual port RAM storer (2) behind address driver, the data line of VME bus chip (1) connects with dual port RAM storer (2) left end data line behind data driver, and the control line of VME bus chip (1) connects with dual port RAM storer (2) left end control line behind bus end logic control chip (8);
The address wire of dsp processor (3) connects with the right-hand member address wire of dual port RAM storer (2), the data line of dsp processor (3) connects with the right-hand member data line of dual port RAM storer (2), and the treated device end of control line logic control chip (9) back of dsp processor (3) connects with the right-hand member control line of dual port RAM storer (2);
Address driver is made up of first address driver (6) and second address driver (7), and data driver is made up of first data driver (4) and second data driver (5);
System power supply provides the voltage of 5V to dual port RAM storer (2).
2, datel circuit according to claim 1, it is characterized in that: first data driver (4) and second data driver (5) are chosen the MC74F245 chip respectively, first address driver (6) and second address driver (7) are chosen the SN74LS245 chip respectively, bus end logic control chip (8) is chosen the GAL20V8B chip, processor end logic control chip (9) is chosen the GAL20V8B chip, dsp processor (3) is chosen the TMS320LF240 chip, dual port RAM storer (2) is chosen the IDT7024 chip, and VME bus chip (1) is chosen 96 pin Harding socket CNVME96.
3, datel circuit according to claim 1 is characterized in that: the address of dual port RAM storer (2) in VME bus chip (1) is 0000H-0FFFH, and the address of dual port RAM storer (2) in DSP storer (3) is C000H-CFFFH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510083982 CN1713165A (en) | 2005-07-18 | 2005-07-18 | Data communicating circuit of VME bus and DSP processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510083982 CN1713165A (en) | 2005-07-18 | 2005-07-18 | Data communicating circuit of VME bus and DSP processor |
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| CN1713165A true CN1713165A (en) | 2005-12-28 |
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| CN 200510083982 Pending CN1713165A (en) | 2005-07-18 | 2005-07-18 | Data communicating circuit of VME bus and DSP processor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420325C (en) * | 2006-01-20 | 2008-09-17 | ***电信传输研究所 | Charge loading method for cdma2000 1xEV-DO system covering test |
| CN100587639C (en) * | 2006-12-30 | 2010-02-03 | 中国科学院电工研究所 | Real time multiple task distributive control system based on VME bus |
| CN102866646A (en) * | 2012-09-20 | 2013-01-09 | 重庆望江工业有限公司 | Real-time control system and method |
-
2005
- 2005-07-18 CN CN 200510083982 patent/CN1713165A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420325C (en) * | 2006-01-20 | 2008-09-17 | ***电信传输研究所 | Charge loading method for cdma2000 1xEV-DO system covering test |
| CN100587639C (en) * | 2006-12-30 | 2010-02-03 | 中国科学院电工研究所 | Real time multiple task distributive control system based on VME bus |
| CN102866646A (en) * | 2012-09-20 | 2013-01-09 | 重庆望江工业有限公司 | Real-time control system and method |
| CN102866646B (en) * | 2012-09-20 | 2014-09-03 | 重庆望江工业有限公司 | Real-time control system and method |
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