CN1700478A

CN1700478A - Semiconductor device and method for manufacturing same

Info

Publication number: CN1700478A
Application number: CN 200410082007
Authority: CN
Inventors: 川村和郎
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2004-05-17
Filing date: 2004-12-29
Publication date: 2005-11-23
Also published as: CN1938825A; CN1938825B

Abstract

The method for fabricating a semiconductor device comprises the step of forming an Ni film 66 on a source/drain diffused layers 64 , the first thermal processing step of reacting a part of the Ni film 66 on the lower side and a part of the source/drain diffused layers 64 on the upper side with each other by thermal processing to form Ni<SUB>2</SUB>Si films 70 b on the source/drain diffused layers 64 , and the step of etching off the part of the Ni film 66 , which has not reacted, and the second thermal processing of reacting by thermal processing the Ni<SUB>2</SUB>Si films 70 b and parts of the source/drain diffused layers 64 on the upper side with each other.

Description

Semiconductor device and manufacture method thereof

Technical field

The present invention relates to a kind of semiconductor device and manufacture method thereof, relate more specifically to a kind of nickel that wherein utilizes and carry out semiconductor device and manufacture method thereof that silicide forms (silicidation).

Background technology

So-called silicide (self-aligned silicide) technology has less ohmic technology as a kind of grid and source of making knownly, and this technology is used for being formed self-aligned metal silicide film on the surface of grid and source.As a kind of metal material that reacts with silicon in this silicide process, cobalt (Co) is widely used (for example referring to Japanese publication examine number of patent application Hei 09-251967 (1997)).

On the other hand, the microminiaturization of semiconductor device structure develops by leaps and bounds.Particularly, the knot of source/drain diffusion layer (junction) degree of depth is little (does not contain 80nm) to 80nm.The film thickness that is formed at the metal silicide film on the source is little (not to contain 20nm) to 20nm.Grid length is little (not to contain 50nm) to 50nm.

In this microminiaturization day by day of semiconductor device structure, when the grid length of semiconductor device (does not contain 40nm) below 40nm, and utilize the Co film on this grid, to form CoSi ₂During film, affirmation has the phenomenon of the resistance dispersion sharp increase of grid.

With this CoSi ₂On the contrary, nickel silicide (nickel silicide) has such advantage, even when grid length (does not contain 40nm) below 40nm, the resistance of grid is still stable, and this is worth receiving publicity.

Yet when utilizing the Ni film to carry out silicide formation simply, the rough interface degree is so big between silicon layer and the silicide film, to such an extent as to the sheet resistance of source/drain diffusion layer disperses increase to some extent, and junction leakage often increases to some extent.

Summary of the invention

The purpose of this invention is to provide a kind of semiconductor device and manufacture method thereof, the sheet resistance that this semiconductor device can suppress source disperses and junction leakage.

According to a scheme of the present invention, a kind of semiconductor device is provided, comprising: grid is formed on the Semiconductor substrate; Source/drain diffusion layer is formed in the Semiconductor substrate on these grid both sides; And silicide film, being formed on this source/drain diffusion layer, this silicide film is formed by single nickle silicide, and the film thickness of this silicide film is 20nm or below the 20nm.

According to another program of the present invention, a kind of method that is used for producing the semiconductor devices is provided, comprising: the step that on Semiconductor substrate, forms grid; The step of formation source/drain diffusion layer in the Semiconductor substrate on these grid both sides; On this source/drain diffusion layer, form the step of nickel film; First heat treatment step by the part of heat treatment nickel film downside and the part of source/drain diffusion layer upside, reacts to each other it, to form nickel silicide film on this source/drain diffusion layer; Selective etch falls the step of still unreacted a part of nickel film; And second heat treatment step, the part on this nickel silicide film and source/drain diffusion layer upside is reacted to each other.

According to the present invention, by this first heat treatment step, the part on the thick relatively nickel film downside and the part on the silicon substrate upside react to each other, and in this first heat treatment, can form Ni thus ₂The Si film suppresses NiSi simultaneously ₂The formation of crystal.Then, in the present invention, do not etched away by selectivity as yet with a part of nickel film of Si reaction, then by second heat treatment, Ni ₂Part on Si film and the silicon substrate upside reacts to each other, and to form the NiSi film, prevents that thus the big thickness of NiSi film ether from forming.And, according to the present invention, suitably set the first and second heat treated conditions, can control the film thickness of NiSi film thus.Thus, according to the present invention, suppressed high-resistance NiSi ₂The formation of film can form high-quality and low-resistance NiSi film simultaneously on silicon substrate.Thus, when the surface of the surface of grid and source/drain diffusion layer being carried out silicide when forming, can suppress the dispersion of sheet resistance.Can also suppress junction leakage.

Description of drawings

Figure 1A-1E is the schematic section (part 1) that the silicide that is used for nickel silicide forms the reaction model of technology.

Fig. 2 A-2D is the schematic section (part 2) that the silicide that is used for nickel silicide forms the reaction model of technology.

Fig. 3 is the schematic section of MOS transistor, utilizes the Ni film of relative thin that this transistor is carried out salicide processes, and this figure illustrates the structure of MOS transistor.

Fig. 4 is the figure of experimental result of the sheet resistance of source/drain diffusion layer, in this experiment, utilizes the Ni film of different film thicknesses, source/drain diffusion layer is carried out silicide form.

Fig. 5 A-5D is the schematic section of the explanation principle of the invention.

Fig. 6 is-Tu, and it has schematically shown the relation between the film thickness of system's Gibbs free energy of silicon substrate and nickel silicide film and Ni film.

Fig. 7 is the sectional view according to the semiconductor device of first embodiment of the invention, and it has illustrated the structure of this semiconductor device.

Fig. 8 A-8C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 1).

Fig. 9 A-9C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 2).

Figure 10 A-10C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 3).

Figure 11 A-11C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 4).

Figure 12 A-12C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 5).

Figure 13 A-13C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 6).

Figure 14 A-14C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 7).

Figure 15 A-15C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 8).

Figure 16 A-16C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 9).

Figure 17 A-17C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 10).

Figure 18 A-18C is the sectional view of semiconductor device in its step of manufacturing according to first embodiment of the invention, and these figure illustrate this method (part 11).

Figure 19 A-19D is the transmission electron micrograph that the method evaluation result is shown, and this method is used to make the semiconductor device according to first embodiment of the invention.

Figure 20 is the sectional view of semiconductor device used during method is estimated, and this method is used to make the semiconductor device according to first embodiment, and this figure illustrates the structure of this semiconductor device.

Figure 21 is the figure of method evaluation result, and this method is used to make the semiconductor device (part 1) according to first embodiment of the invention.

Figure 22 is the figure of method evaluation result, and this method is used to make the semiconductor device (part 2) according to first embodiment of the invention.

Figure 23 A-23C is the sectional view of semiconductor device in its step of manufacturing according to second embodiment of the invention, and these figure illustrate this method.

Embodiment

[principle of the present invention]

At first, with reference to Figure 1A-1E, 2A-2D, 3,4,5A-5D and 6, principle of the present invention is described.Figure 1A-1E and 2A-2D are schematic sections, and the silicide that these figure explanations are used for nickel silicide forms the reaction model of technology.Fig. 3 is the schematic section of MOS transistor, utilizes the Ni film of relative thin that this transistor is carried out salicide processes, and this figure illustrates the structure of MOS transistor.Fig. 4 is the figure of experimental result of the sheet resistance of source/drain diffusion layer, in this experiment, utilizes the Ni film of different film thicknesses, source/drain diffusion layer is carried out silicide form.Fig. 5 A to 5D is the schematic section of the explanation principle of the invention.Fig. 6 is such figure, and this figure schematically shows the relation between the film thickness of system's Gibbs free energy of silicon substrate and nickel silicide film and Ni film.

So far, reported the reaction model of silicide formation technology, this technology is used for forming nickel silicide with silicon substrate and Ni film, and these models change along with the film thickness of Ni film.In the application's specification, " nickel silicide " broadly is meant the compound of nickel and silicon, when clearly expressing the composition of nickel silicide, uses " silication two nickel (Ni respectively ₂Si) ", " single nickle silicide (NiSi) " or " nickel disilicide (NiSi ₂) ".

At first, the silicide that is carried out on the abundant thick Ni film for the about 200nm thickness that forms on the silicon substrate forms technology, and the reaction model below having reported is (referring to people such as F.d ' Heurle, J.Appl.Phys., vol.55, pp.4208-4218 (1984)).

When nickel (Ni) film 12 of the about 200nm thickness that forms on utilizing (111) or (100) silicon substrate 10 is heat-treated, silication two nickel (Ni ₂Si) film 14 is formed in the interface between silicon substrate 10 and the Ni film 12, shown in Figure 1B.That is to say Ni ₂The nickel silicide film 14 of Si phase is formed in the interface between silicon substrate 10 and the Ni film 12.Form the Ni of nickel silicide film 14 ₂The crystal of Si phase has orthohormbic structure, and in this structure, the atom ratio of components of Ni: Si is 2: 1, lattice constant is a=0.499nm, and b=0.372nm and c=0.703nm are (referring to people such as F.d ' Heurle, J.Appl.Phys., vol.55, pp.4208-4218 (1984)).Because Ni film 12 is very thick, and Ni's is in large supply in the supply of Si, so form Ni ₂Si film 14.

Then, along with continuing heat treatment, shown in Fig. 1 C, Ni ₂14 continued growths of Si film, and all Ni become Ni ₂Si.That is to say, on silicon substrate 10, form Ni ₂The nickel silicide film 14 of Si phase.

Then, along with further continuation heat treatment, shown in Fig. 1 D, single nickle silicide (NiSi) film 16 is formed at silicon substrate 10 and Ni ₂In the interface between the Si film 14.That is to say that the nickel silicide film 16 of NiSi phase is formed at silicon substrate 10 and Ni ₂In the interface between the Si film 14.The crystal that forms the NiSi phase of nickel silicide film 16 is an orthohormbic structure, in this structure, the atom ratio of components of Ni: Si is 1: 1, lattice constant is a=0.5233nm, b=0.3258nm and c=0.5659nm are (referring to people such as F.d ' Heurle, J.Appl.Phys., vol.55, pp.4208-4218 (1984)).

Then, along with further continuation heat treatment, shown in Fig. 1 E, NiSi film 16 continues further growth, Ni even ₂Si film 14 becomes the NiSi film.That is to say, on silicon substrate 10, form the only nickel silicide film 16 of the nickel silicide of NiSi phase.

As mentioned above, in the silicide formation technology of the abundant thick Ni film that utilizes about 200nm thickness, this reacts with Ni ₂The order of Si and NiSi continues.

The cross-sectional view result (referring to people such as V.Teodorescu, J.Appl.Phys., vol.90, pp.167-174 (2001)) of transmission electron microscope has been reported in the heat treatment of being carried out on the thin Ni film for the 12nm thickness that forms on the silicon substrate.The cross-sectional view of transmission electron microscope knows that the reaction model of expression is as described below.

When the Ni film 12 of formed 12nm thickness is heat-treated on for (001) silicon substrate 10 (seeing Fig. 2 A), shown in Fig. 2 B, nickel disilicide (NiSi ₂) crystal 18 is formed in the interface between silicon substrate 10 and the Ni film 12 unevenly.NiSi ₂The crystal of phase has cube structure, and in this structure, the atom ratio of components of Ni: Si is 1: 2, and lattice constant is a=b=c=0.543nm (referring to people such as F.d ' Heurle, J.Appl.Phys., vol.55, pp.4208-4218 (1984)).NiSi ₂Crystal 18 is formed in the early stage technology of this reaction, and it can not form very thickly along with Ni film 12, because Ni film 12 is very thin, and the supply of Ni is less than the supply of Si.

Along with further continuation heat treatment, shown in Fig. 2 C, NiSi ₂Ni film 12 on the crystal becomes NiSi film 16.At this moment, NiSi ₂Also growth in silicon substrate 10 of crystal 18.That is to say that on silicon substrate 10, having formed wherein, mixing has NiSi ₂The nickel silicide film of phase and NiSi phase.

Then, along with further continuation heat treatment, shown in Fig. 2 D, 16 continued growths of NiSi film.At this moment, inhomogeneous formation NiSi under NiSi film 16 ₂Crystal.

As mentioned above, in the silicide process of the relative thin Ni film that utilizes about 12nm thickness, this reacts with NiSi ₂Continue with the order of NiSi, and NiSi ₂Crystal is inhomogeneous to be formed under the NiSi film.

As mentioned above, silicide formation reaction process changes according to the film thickness of the Ni film that forms on the silicon substrate.

In the silicide of the thick relatively Ni film that utilizes about 200nm thickness formed, as mentioned above, this reacted with Ni ₂The order of Si and NiSi continues, and the NiSi film can evenly be formed.The rough interface degree can diminish between silicon substrate and the NiSi film.Yet along with semiconductor device is microminiaturized day by day at present, the height of grid (contains 100nm) below 100nm, and the junction depth of source/drain diffusion layer is littler.When utilizing thick Ni film to carry out silicide formation on the source/drain diffusion layer of so little junction depth, for junction depth, the NiSi film usually forms too thickly on source/drain diffusion layer.For junction depth, the NiSi film that forms too thickly on source/drain diffusion layer has increased junction leakage.

Yet, as mentioned above, when the Ni of the relative thin of utilizing about 12nm thickness film carries out silicide formation, formed the NiSi film, and NiSi ₂The crystal adequate relief is formed under the NiSi film.The resistivity of NiSi is 14 μ Ω cm, and NiSi ₂Resistivity be 34 μ Ω cm, its be NiSi resistivity twice or more than.

The high resistance NiSi of inhomogeneous like this formation ₂Crystal is the reason that interface roughness increases between silicon substrate and the NiSi film, also is the reason that sheet resistance disperses increase.This still is the reason that junction leakage increases.

Fig. 3 is the summary sectional view that the MOS transistor of its structure is shown, and utilizes the Ni film of the relative thin of about 12nm thickness, and this MOS transistor is carried out salicide processes.As shown in the figure, grid 24 is formed on the silicon substrate 20, is formed with gate insulating film 22 therebetween.Side wall insulating film 26 is formed on the sidewall of grid 24.In the silicon substrate 20 on grid 24 both sides, formed the source/drain diffusion layer 28 of extension source/drain electrode structure.On grid 24 and source/drain diffusion layer 28, utilize the Ni film of relative thin, form NiSi film 30 by salicide processes.Because utilize the salicide processes of the Ni film of relative thin, so NiSi ₂Crystal is formed in the NiSi film 30 or under the NiSi film 30 unevenly.That is to say, in nickel silicide film, mixed NiSi phase and NiSi ₂Phase.

The junction depth of source/drain diffusion layer 28 is littler at its part place near side wall insulating film 26 ends.Thus, as shown in Figure 3, near the end of side wall insulating film 26, NiSi ₂Crystal 32 usually arrives near the knot of source/drain diffusion layer 28.Such NiSi ₂Crystal 32 is the reasons that produce junction leakage.

In the semiconductor device of 90nm node technology, the junction depth of source/drain diffusion layer (contains 80nm) below 80nm.Thus, will must below 20nm, (contain 20nm) at the film thickness that forms on source/drain diffusion layer as the metal silicide film of source/drain electrode, thereby fully suppress the generation of junction leakage.Thereby the film thickness of used Ni film preferably (contained 13nm) during the silicide of source/drain diffusion layer formed below 13nm.On the other hand, form the Ni film very thin, can form NiSi unevenly ₂Crystal, this is the reason of sheet resistance dispersion and junction leakage.As mentioned above, utilizing the Ni film to carry out silicide when being formed for microminiaturized MOS transistor, common process can't be avoided forming the Ni film very thin, and this will make and be difficult to be avoided NiSi ₂The formation of crystal, these NiSi ₂Crystal causes the reduction of transistor characteristic.

The present inventor has carried out the experiment of the sheet resistance of measurement source/drain diffusion layer (this source/drain diffusion layer has utilized the Ni film of different-thickness to carry out salicide processes), film thickness with clear and definite Ni film, this thickness allows to carry out silicide and forms, and this has suppressed NiSi ₂The generation of crystal.In experiment, utilize the Ni film of 10nm thickness, 12nm thickness, 15nm thickness, 17nm thickness and 20nm thickness, salicide processes has been carried out on the surface of the source/drain diffusion layer of 0.14 μ m width boron-doping.For each film thickness, a plurality of samples have been measured sheet resistance, and drawn the cumulative probability of these samples.Fig. 4 is the figure of experimental result.The sheet resistance of expression source/drain diffusion layer on trunnion axis is represented cumulative probability on vertical axis.The ■ mark is drawn and is represented the measurement result of 10nm thickness Ni film, ● mark is drawn and is represented the measurement result of 12nm thickness Ni film, the △ mark is drawn and is represented the measurement result of 15nm thickness Ni film, the  mark is drawn and is represented the measurement result of 17nm thickness Ni film, the measurement result of ◇ mark drawing expression 20nm thickness Ni film.

From experimental result shown in Figure 4 obviously as can be known, sheet resistance in the silicide that utilizes 17nm thickness Ni film and 20nm thickness Ni film forms disperses, and disperses much smaller than the sheet resistance in the silicide that utilizes 10nm thickness Ni film, 12nm thickness Ni film and 15nm thickness Ni film forms.Based on this result, we can say that the film thickness when the Ni film (contains 17nm) more than 17nm, suppressed NiSi ₂The formation of crystal.That is to say, can think that in this case the silicide that has produced reaction model shown in Fig. 1 forms.In addition, when the film thickness of Ni film (contains 17nm) more than 17nm, also suppressed the gathering of silicide.

On the other hand, when the film thickness of Ni film (contained 17nm) below 17nm, the sheet resistance dispersion of carrying out the source/drain diffusion layer of salicide processes was significant.Based on this result, when the film thickness of Ni film (contains 17nm) below 17nm, we can say to have formed NiSi ₂Crystal.That is to say, can think that in this case the silicide that reaction model shown in Fig. 2 has taken place forms.

Here, utilize the Ni film of above (the containing 20nm) film thickness of 20nm and the film thickness of the NiSi film that forms (contains 30nm) more than 30nm.Thus, when the Ni film that utilizes the film thickness that (contains 20nm) more than the 20nm, when the surface of the surface of grid and source/drain diffusion layer is formed silicide simply, can suppress NiSi ₂The formation of crystal, but risk is possible increase junction leakage.

The present inventor has done conscientious research and has drawn such viewpoint, as follows, can suppress high resistance NiSi ₂The formation of crystal can form the NiSi film of required film thickness degree simultaneously.With reference to Fig. 5 A to 5D, illustrate that silicide of the present invention forms technology.

At first, shown in Fig. 5 A, for example the Ni film 12 of 20nm thickness is formed on the silicon substrate 10.The film thickness of Ni film 12 for example (contains 17nm) more than 17nm.Yet, preferably the film thickness maximum of Ni film 12 is set in below the 200nm and (contains 200nm), because as described later, after silicide forms, must inerrably remove as yet not part with the Ni film 12 of Si reaction.

Then, with first heat treatment phase with, for example under 270 ℃, carry out 30 seconds RTA (rapid thermal annealing), shown in Fig. 5 B, the Si of the part in the Ni of the part in the Ni film 12 on downside and the silicon substrate 10 on upside reacts to each other thus, forms Ni ₂Si film 14.That is to say, only by Ni ₂The nickel silicide film 14 that the nickel silicide of Si phase forms is formed in the interface between silicon substrate 10 and the Ni film 12.The film thickness of this part Ni film 12 on downside (with the Si reaction) for example is 10nm.The first heat treated heat treatment temperature for example is 200 to 400 ℃.Heat treatment time for example is 10 seconds to 60 minutes.

Then, shown in Fig. 5 C, do not etched away by selectivity as yet with a part of Ni film 12 of Si reaction.Etching solvent for example is with 3: 1 the mixed thiosulfonic acid and the thiosulfonic acid/hydrogen peroxide mixture of hydrogen peroxide.Etching period is not set according to waiting with the film thickness of this part Ni film 12 of Si reaction as yet.For example, etching period is 1 to 3 minute.

Then, for example under 500 ℃, carry out 30 seconds second heat treatment by RTA.Thus, shown in Fig. 5 D, Ni ₂Ni in the Si film 14 ₂A part of Si in Si and the silicon substrate 10 on the upside reacts to each other, and forms NiSi film 16.That is to say that only the nickel silicide film 16 that is formed by the nickel silicide of NiSi phase is formed on the silicon substrate 10.The second heat treated heat treatment temperature is equal to or higher than the first heat treated temperature substantially.Particularly, this heat treatment temperature for example is 350 ℃ to 650 ℃.Heat treatment time for example is 10 seconds to 60 seconds.

As mentioned above, in silicide of the present invention formed, the part on upside reacted to each other by first heat treatment thick relatively Ni film 12 in the part on the downside and silicon substrate 10.Because Ni film 12 is thicker relatively, in first heat treatment, NiSi can suppressed ₂The formation of crystal forms Ni simultaneously ₂Si film 14.Then, not etched as yet with this part Ni film 12 of Si reaction, Ni then ₂A Si film 14 and the part on silicon substrate 10 upsides react to each other by second heat treatment, form NiSi film 16, prevent that thus NiSi film 16 from forming too thickly.The film thickness of NiSi film 16 can be controlled by suitably imposing a condition, such as the first and second heat treated heat treatment temperatures and heat treatment time etc.

Thus, high-quality and low-resistance NiSi film 16 can be formed required film thickness on silicon substrate 10, suppress high resistance NiSi simultaneously ₂The formation of film, the rough interface degree can diminish between silicon substrate 10 and the NiSi film 16 thus.Thus, when salicide processes is carried out on the surface of the surface of grid and source/drain diffusion layer, can suppress the dispersion of sheet resistance.Can suppress junction leakage.

Preferably the film thickness of Ni film is set at more than the 17nm and (contains 17nm), thereby form Ni by first heat treatment ₂The Si film suppresses NiSi simultaneously ₂The formation of film.Its reason is as described below.

Fig. 6 be schematically shown system's Gibbs free energy of silicon substrate and nickel silicide film and silicide form in graph of a relation between the film thickness of used Ni film.In the drawings, imaginary curve is represented silicon substrate and NiSi ₂Relation during system's Gibbs free energy of film and silicide form between the film thickness of used Ni film.In the drawings, solid-line curve is represented silicon substrate and Ni ₂Relation during system's Gibbs free energy of Si film and silicide form between the film thickness of used Ni film.

As shown in Figure 6, with the 17nm film thickness of Ni film as the border, when the film thickness of Ni film during less than boundary film thickness, silicon substrate and NiSi ₂The system of film will be than silicon substrate and Ni ₂The system of Si film has lower Gibbs free energy.Thus, in this case, can think stably to have formed NiSi ₂Film.

On the other hand, with the 17nm film thickness of Ni film as the border, when the film thickness of Ni film during greater than boundary film thickness, silicon substrate and Ni ₂The system of Si will be than silicon substrate and NiSi ₂The system of film has higher Gibbs free energy.Thus, in this case, can think stably to have formed Ni ₂The Si film.That is to say that the film thickness of Ni film is set at 17nm above (containing 17nm), can suppress NiSi fully thus ₂The formation of film.

As mentioned above, the film thickness of Ni film is set at 17nm above (containing 17nm), more preferably (contains 20nm) more than 20nm, is suppressing NiSi thus ₂The formation of film can form Ni simultaneously ₂The Si film.This has obtained the support of the sheet resistance measurement result of source/drain diffusion layer shown in Figure 4.

[first embodiment]

With reference to Fig. 7 to 22, semiconductor device and manufacture method thereof according to first embodiment of the invention are described.Fig. 7 is the sectional view according to the semiconductor device of present embodiment.Fig. 8 A-8C to 18A-18C is that it has illustrated this method according to the semiconductor device of the present embodiment sectional view at the method step that is used for making this semiconductor device.Figure 19 A-19D is a transmission electron micrograph, shows the evaluation result that is used to make according to the method for the semiconductor device of present embodiment.Figure 20 is used for making the used semiconductor device sectional view of method according to the semiconductor device of present embodiment in evaluation, shows its structure.Figure 21 and 22 is the evaluation result figure that are used to make according to the method for the semiconductor device of present embodiment.

At first, with reference to Fig. 7, the structure according to the semiconductor device of present embodiment is described.

In silicon substrate 34, be formed for limiting the device isolation regions 46 of device area.Be formed with therein and form the trap (not shown) in the silicon substrate 34 of device isolation regions 46.

Be formed with therein on the silicon substrate 34 of trap, form the grid 54 of polysilicon film, be formed with the gate insulating film 52 of silicon dioxide film therebetween.On grid 54, form the only nickel silicide film 72a of NiSi.That is to say that nickel silicide film 72a is only formed by the nickel silicide of NiSi phase.The film thickness of nickel silicide 72a for example (contains 20nm) below 20nm.

Side wall insulating film 60 is formed on the sidewall of the grid 54 that is formed with nickel silicide film 72a thereon.

Channel doping layer 50 is formed in the silicon substrate 34 under the grid 54.In the silicon substrate 34 on grid 54 both sides, form the source/drain diffusion layer 64 that contains shallow diffusion of impurities zone 58 (having formed the elongated area of extension source/drain electrode structure) and dark diffusion of impurities zone 62.Only the nickel silicide film 72b of NiSi is formed on source/drain diffusion layer 64.That is to say that nickel silicide film 72b is only formed by the nickel silicide of NiSi phase.The thickness of nickel silicide (nickel silicide) film 72b for example (contains 20nm) below 20nm.

Thus, the MOS transistor that comprises grid 54 and source/drain diffusion layer 62 is formed on the silicon substrate 34.

Silicon nitride film 74 is formed on the silicon substrate 34 that is formed with MOS transistor thereon.Silicon dioxide film 76 is formed on the silicon nitride film 74.

Contact hole 78a is formed in silicon dioxide film 76 and the silicon nitride film 74, downwards the nickel silicide film 72a on grid 54.Contact hole 78b is formed in silicon dioxide film 76 and the silicon nitride film 74, downwards the nickel silicide film 72b on source/drain diffusion layer 64.

Contact plug 84a, the 84b of barrier metal 80 and tungsten film 82 is buried in respectively among contact hole 78a, the 78b.

Interlayer dielectric 86 is formed on the silicon dioxide film 76 of wherein burying

contact plug

84a, 84b.

Thus, constituted semiconductor device according to present embodiment.

Principal character according to the semiconductor device of present embodiment is that the nickel silicide film 72a, the 72b that are formed at respectively on the grid 54 and on source/drain diffusion layer 64 are only formed by the nickel silicide of NiSi phase.

That is to say, in semiconductor device according to present embodiment, no NiSi ₂Crystal is formed among nickel silicide film 72a, the 72b.NiSi ₂Crystal neither is formed in the interface between nickel silicide film 72a and the grid 54, also is not formed in the interface between nickel silicide 72b and the silicon substrate 34.

As mentioned above, because

nickel silicide film

72a, 72b are only formed by the nickel silicide of NiSi phase, rough interface degree between interface between NiSi film 72a and the grid 54, NiSi film 72b and the source/drain diffusion layer 64 can diminish, thus can suppressor grid 54 and the sheet resistance on the surface of source/drain diffusion layer 64 disperse.

The film thickness of nickel silicide film 72b for example is as thin as 20nm following (containing 20nm), and does not form NiSi ₂Crystal (these NiSi ₂Crystal arrives near the knot (junction) of source/drain diffusion layer 64, causes junction leakage), even thus when the junction depth of source/drain diffusion layer 64 is very little, still can suppress junction leakage.

Then, with reference to Fig. 8 A-8C to Figure 18 A-18C, the manufacture method according to the semiconductor device of present embodiment is described.

At first, for example with ammonia/hydrogen peroxide mixture, clean the surface of silicon substrate 34.Silicon substrate 34 for example is p type (a 100) silicon substrate.

Then, for example by thermal oxidation, on silicon substrate 34, form for example silicon dioxide film 36 of 50nm thickness (seeing Fig. 8 A).

Then, for example by spin coated, form photoresist film 38.Then, by photoetching with photoresist film 38 patternings.Thus, be formed for the photoresist mask 38 (seeing Fig. 8 B) of patterned silicon dioxide film 36.

Then, with photoresist film 38 as mask, etch silicon dioxide film 36 (seeing Fig. 8 C).

Then, as mask, for example inject, impurity is injected in the silicon substrate 34 by ion with photoresist film 38 and silicon dioxide film 36.Thus, form the trap 40 (seeing Fig. 9 A) of required conduction type.When forming p type trap when (being used for forming therein nmos pass transistor), for example use boron as p type impurity, and the condition that ion injects is 120keV accelerating voltage and 1 * 10 ¹³Cm ^-2Dosage.When forming n type trap when (being used for forming therein the PMOS transistor), for example use phosphorus as n type impurity, and the condition that ion injects for example is 300keV acceleration energy and 1 * 10 ¹³Cm ^-2Dosage.

After forming trap 40, remove photoresist film 38 (Fig. 9 B).Then, etch away silicon dioxide film 36 (seeing Fig. 9 C).

Then, for example as follows, be formed for limiting the device isolation regions of device area by STI (shallow trench isolation).

At first, for example, on silicon substrate 34, form for example silicon nitride film 42 of 50nm thickness (seeing Figure 10 A) by CVD (chemical vapour deposition (CVD)).

Then, by photoetching and dry ecthing, patterning silicon nitride film 42.Thus, be formed for forming the hard mask 42 of raceway groove, these raceway grooves will be used for buried silicon dioxide film (seeing Figure 10 B) therein.

Then, with silicon nitride film 42 as mask, etched silicon substrate 34.Thus, raceway groove 44 is formed in the silicon substrate 34 and (sees Figure 10 C).

After forming raceway groove 44,, remove silicon nitride film 42 (seeing Figure 11 A) as mask by wet etching.

Then, be formed with therein on the silicon substrate 34 of raceway groove 44, for example, form for example silicon dioxide film of 300nm thickness by CVD.

Then, for example, till the surface of exposing silicon substrate 34, remove the silicon dioxide film on the silicon substrate 34 thus by CMP (chemico-mechanical polishing) polishing silicon dioxide film.

Thus, formed the device isolation regions 46 (seeing Figure 11 B) that is buried in the silicon dioxide film in the raceway groove 44.Device isolation regions 46 limits device area.

Then, for example by spin coated, form photoresist film 48.Then, by photoetching, patterning photoresist film 48.Thus, be formed for forming the photoresist mask 48 (seeing Figure 11 C) of channel doping layer.In the accompanying drawing after accompanying drawing 11C, amplified the device area that is used for forming therein MOS transistor.

Then, as mask, for example inject, impurity is injected in the silicon substrate 34 by ion with photoresist film 48.Thus, channel doping layer 50 is formed in the silicon substrate 34 and (sees Figure 12 A).When forming nmos pass transistor, for example use boron as p type impurity, and to be used for the condition that ion injects for example be 15keV acceleration energy and 1 * 10 ¹³Cm ^-2Dosage.When forming the PMOS transistor, for example use arsenic as n type impurity, and to be used for the condition that ion injects for example be 80keV acceleration energy and 1 * 10 ¹³Cm ^-2Dosage.

After forming channel doping layer 50, remove photoresist film 48 as mask.

Then, for example heat treatment by 950 ℃ and 10 seconds, the impurity in the activation channel doping layer 50.

Then, for example by thermal oxidation, on silicon substrate 34, form for example gate insulating film 52 of the silicon dioxide film of 2nm thickness (Figure 12 B).Gate insulating film 52 is formed by silicon dioxide film, but and is nonessentially formed by silicon dioxide film.Can suitably use any other dielectric film.

Then, for example on whole surface, form for example polysilicon film 54 of 100nm thickness by CVD.

Then, for example inject, impurity is injected into (referring to Figure 12 C) in the polysilicon film 54 by ion.When forming nmos pass transistor, for example use phosphorus as n type impurity, and to be used for the condition that ion injects for example be 10keV acceleration energy and 1 * 10 ¹⁶Cm ^-2Dosage.When forming the PMOS transistor, for example use boron as p type impurity, and to be used for the condition that ion injects for example be 5keV and 5 * 10 ¹⁵Cm ^-2

Then, for example by spin coated, form photoresist film 56.Then, by photoetching, patterning photoresist film 56.Thus, be formed for the photoresist mask 56 (seeing Figure 13 A) of patterned polysilicon film 54.

Then, with photoresist film 56 as mask, dry ecthing polysilicon film 54.Thus, grid 54 forms (seeing Figure 13 B) by polysilicon film.

After forming grid 54, remove photoresist film 56 as mask.

Then, as mask, for example inject, impurity is injected in the silicon substrate 34 on grid 54 both sides by ion with grid 54.When forming nmos pass transistor, for example use arsenic as n type impurity, and to be used for the condition that ion injects for example be lkeV acceleration energy and 1 * 10 ¹⁵Cm ^-3Dosage.When forming the PMOS transistor, for example use boron as p type impurity, and to be used for the condition that ion injects for example be 0.5keV acceleration energy and 1 * 10 ¹⁵Cm ^-2Dosage.Thus, form shallow diffusion of impurities zone 58, these diffusion zones have formed the elongated area (seeing Figure 13 C) of extension source/drain electrode structure.

Then, for example, on whole surface, form for example silicon dioxide film 60 of 100nm thickness (Figure 14 A) by CVD.

Then, for example by RIE (active-ion-etch), anisotropically the etch silicon dioxide film 60.Thus, side wall insulating film 60 forms (Figure 14 B) by the silicon dioxide film on the sidewall of grid 54.Side wall insulating film 60 is here formed by silicon dioxide film, but and is nonessentially formed by silicon dioxide film.Can suitably use any other dielectric film.

Then,, impurity is injected in the silicon substrate 34 on the both sides of grid 54 and side wall insulating film 60 as mask with grid 54 and side wall insulating film 60.When forming nmos pass transistor, for example use phosphorus as n type impurity, and to be used for the condition that ion injects for example be 8keV acceleration energy and 1 * 10 ¹⁶Cm ^-2Dosage.When forming the PMOS transistor, for example use boron as p type impurity, and to be used for the condition that ion injects for example be 5keV acceleration energy and 5 * 10 ¹⁵Cm ^-2Dosage.Thus, form diffusion of impurities zone 62, the dark zone of these regional formation source/drain diffusion layer (seeing Figure 14 C).

Then, by the heat treatment of appointment, the impurity that injects in the activator

impurity diffusion zone

58,62.

Thus, be that shallow diffusion of impurities zone 58 and the dark diffusion of impurities zone 62 source/drain diffusion layer that form 64 are formed in the silicon substrate 34 on the both sides of grid 54 by the elongated area.

Then, by for example handling, remove on the surface of grid 54 and the primary oxide film that forms on the surface of source/drain diffusion layer 64 with hydrofluoric acid.

Then, by for example carrying out splash, on whole surface, form for example Ni film 66 of 20nm thickness with the Ni target.The film thickness of Ni film 66 for example (contains 17nm) more than 17nm.As describing subsequently, preferably, the film thickness of Ni film 66 (contains 200nm) below 200nm, because after first heat treatment, must remove as yet not the part with the Ni film 66 of Si reaction.

Then, for example by PVD (physical vapour deposition (PVD)), on Ni film 66, form for example diaphragm 68 (seeing Figure 15 C) of the titanium nitride of 5 to 50nm thickness (TiN) film.Diaphragm 68 is also nonessentially formed by titanium nitride.Diaphragm 68 for example can be titanium (Ti) film of 5 to 30nm thickness.

Diaphragm 68 can prevent nickel film 66 and subsequently that the nickel silicide film that forms is oxidized.

Be formed with the substrate of Ni film 66 when being installed on it, this Ni film 66 is exposed to the box that is used for transport substrates or is loaded on the smelting furnace of RTA device or during the chamber of film deposition apparatus, box (cassette), smelting furnace or chamber are polluted by Ni, and the Ni particulate usually adheres to other substrates, these other substrates be installed on the box subsequently or be loaded into the smelting furnace of RTA device or the chamber of film deposition apparatus in.Be formed at diaphragm 68 on the Ni film 66 and can prevent the secondary pollution of Ni.

Then, for example, carry out first heat treatment and be used for silicide formation by at 270 ℃ of following RTA of 30 seconds.Thus, the Si of the part in the Ni of the part in the Ni film 66 on downside and the grid 54 on upside reacts to each other, and the Si of the part in the Ni of the part in the Ni film 66 on downside and the source/drain diffusion layer 64 on upside reacts to each other.Thus, Ni ₂Si film 70a is formed on the grid 54, Ni ₂Si film 70b is formed on source/drain diffusion layer 64 and (sees Figure 16 A).That is to say, only Ni ₂Nickel silicide 70a, the 70b of the nickel silicide of Si phase is formed in the interface between grid 54 and the Ni film 66 and in the interface between source/drain diffusion layer 64 and the Ni film 66.

Then, by wet etching, optionally remove respectively as yet not diaphragm 68 and a part of Ni film 66 (seeing Figure 16 B) with the Si reaction.For example, this etching solvent is with 3: 1 the mixed thiosulfonic acid and the thiosulfonic acid/hydrogen peroxide mixture of hydrogen peroxide.This etching period for example is 20 minutes.

Then, the same with second heat treatment that is used for silicide formation, for example, heat-treat by at 500 ℃ of following RTA of 30 seconds.Thus, Ni ₂Ni among the Si film 70a ₂A part of Si in Si and the grid 54 on the upside reacts to each other Ni ₂Ni among the Si film 70b ₂A part of Si in Si and the source/drain diffusion layer 64 on the upside reacts to each other.Thus, NiSi film 72a is formed on the grid 54, and NiSi film 72b is formed on source/drain diffusion layer 64 and (sees Figure 16 C).That is to say that only nickel silicide film 72a, the 72b of the nickel silicide of NiSi phase are formed on grid 54 and the source/drain diffusion layer 64.

Thus, by salicide processes, NiSi film 72a is formed on the grid 54, and NiSi film 72b is formed on source/drain diffusion layer 64.By being film thickness and the condition that Ni film 66 is suitably set in first and second heat treatments, can form

NiSi film

72a, 72b with required film thickness.For example,

NiSi film

72a, 72b can form the 20nm film thickness of following (containing 20nm).

As mentioned above, the principal character that is used to make according to the method for the semiconductor device of present embodiment is, Ni film 66 is formed thick relatively after, by first heat treatment, part on grid 54 upsides and the Si in source/drain diffusion layer 64 and the Ni of the part on the downside in Ni film 66 react, thus the Ni that forms on gate electrode 54 and the source/drain diffusion layer 64 ₂Si film 70a, 70b then, are not selectively removed with a part of Ni film 66 of Si reaction as yet, then by second heat treatment, and Si and Ni in a part of grid 54 and the source/drain diffusion layer 64 ₂Ni among Si film 70a, the 70b ₂The Si reaction forms

NiSi film

72a, 72b on the grid 54 and on source/drain diffusion layer 64 thus.

By first heat treatment, the Ni reaction in relative with the part on the downside respectively thick Ni film 66 with Si in source/drain diffusion layer 64 of the part on its gate electrode 54 upsides in first heat treatment, can form Ni thus ₂Si film 70a, 70b suppress NiSi simultaneously ₂The formation of crystal.Then selective removal as yet not with a part of Ni film 66 of Si reaction after, by second heat treatment, thereon a part of grid 54 on the side and the Si in source/drain diffusion layer 64 respectively with Ni ₂Ni among Si film 70a, the 70b ₂The Si reaction forms NiSi film 70a, 70b thus.Thus, prevent that

NiSi film

72a, 72b from forming too thickly.The film thickness of

NiSi film

72a, 72b can by suitably impose a condition (such as, the first and second heat treated heat treatment temperatures, heat treatment time etc.) control.

Thus, can on grid 54 and source/drain diffusion layer 64, form NiSi film 72a, the 72b of high-quality, suppress high resistance NiSi simultaneously with required film thickness ₂The formation of crystal, the rough interface degree between interface between NiSi film 72a and the grid 54 and NiSi film 72b and the source/drain diffusion layer 64 can diminish thus.The sheet resistance on the surface that can suppressor grid 54 and the surface of source/drain diffusion layer 64 disperses.Can also suppress junction leakage.

Then, for example, on whole surface, form for example silicon nitride film 74 of 50nm thickness by plasma CVD.The depositing temperature of silicon nitride film 74 for example is 500 ℃.Step after the salicide processes is for example carried out in the temperature that (contains 500 ℃) below 500 ℃, to suppress the gathering of

NiSi film

72a, 72b.

Then, for example, on silicon nitride film 74, form for example silicon dioxide film 76 of 600nm thickness (seeing Figure 17 A) by plasma CVD.

Then, for example by CMP, planarization silicon dioxide film 76 (seeing Figure 17 B).

Then, by photoetching and dry ecthing, contact hole 78a and contact hole 78b are formed in silicon dioxide film 76 and the silicon nitride film 74, respectively downwards until NiSi film 72a and NiSi film 72b (seeing Figure 17 C).

Then, for example by splash on the silicon dioxide film 76 that is formed with

contact hole

78a, 78b therein, form for example barrier metal 80 of the titanium nitride film of 50nm thickness.

Then, for example, on barrier metal 80, form for example tungsten film 82 of 400nm thickness (seeing Figure 18 A) by CVD.

Then, for example by CMP, with tungsten film 82 and barrier metal 80 polishings, until the surface of exposing silicon dioxide film 76.Thus,

contact plug

84a, 84b form (seeing Figure 18 B) by barrier metal among contact hole 78a, the 78b 80 and tungsten film 82 respectively.

Then, interlayer dielectric 86 is formed on the whole surface and (sees Figure 18 C).

After forming interlayer dielectric 86, suitably form the interconnection layer (not shown).

Thus, produce according to semiconductor device embodiment illustrated in fig. 7.

Then, with reference to Figure 19 A-19D to Figure 22, the evaluation result that is used to make according to the method for the semiconductor device of present embodiment is described.

(evaluation result (part 1))

By transmission electron microscope, observe by the cross section that is used to make according to the MOS transistor of the method manufacturing of the semiconductor device of present embodiment, and estimate interface roughness between silicon substrate and the nickel silicide film.This cross-section is to carry out at the source/drain diffusion layer of MOS transistor and the interface that is formed between the nickel silicide film on its source/drain diffusion layer.

Figure 19 A is the transmission electron micrograph in the observation cross section of example 1 (promptly being used to make the MOS transistor according to the method manufacturing of the semiconductor device of present embodiment).In example 1, the TiN film is formed on the Ni film of 20nm thickness, and first heat treatment was carried out 30 seconds at 260 ℃.Then, remove as yet not TiN film and a part of Ni film with the Si reaction, and second heat treatment was carried out 30 seconds at 450 ℃.

Figure 19 B is the transmission electron micrograph in the observation cross section of control 1.In control 1, the TiN film is formed on the Ni film of 10nm thickness, and carries out the heat treatment of 400 ℃ and 30 seconds.

Figure 19 C is the transmission electron micrograph in the observation cross section of control 2.In control 2, the TiN film is formed on the Ni film of 10nm thickness, and first heat treatment was carried out 30 seconds at 280 ℃.Then, selective removal as yet not with TiN film and a part of Ni film of Si reaction, and second heat treatment was carried out 30 seconds at 450 ℃ then.

Figure 19 D is the transmission electron micrograph in the observation cross section of control 3.In control 3, the TiN film is formed on the Ni film of 10nm thickness, and first heat treatment was carried out 30 seconds at 260 ℃.Then, selective removal as yet not with TiN film and a part of Ni film of Si reaction, and second heat treatment was carried out 30 seconds at 450 ℃ then.

In the control shown in Figure 19 B to 19D 1 to 3, can be observed high resistance NiSi ₂Crystal 92 is formed at the near interface between source/drain diffusion layer 88 and the NiSi film 90 unevenly.That is to say, in control 1 to 3, NiSi phase and NiSi ₂Phase is mixed on source/drain diffusion layer in the formed nickel silicide film.Only low annealing (low annealing) and do not make and to suppress NiSi by Ni film thickening ₂Pulse (spike).

In contrast, in the example shown in Figure 19 A 1, do not observe these NiSi ₂Crystal.That is to say that in example 1, the nickel silicide film that is formed on source/drain diffusion layer is formed by the nickel silicide of NiSi phase only.

Can find obviously the comparison between the electron microscope picture that the interface roughness ratio in example 1 between source/drain diffusion layer 88 and the NiSi film 90 is much smaller in control 1 to 3.

Based on the above-mentioned cross-section result of transmission electron microscope, be used to make the NiSi film that can form high-quality according to the method for the semiconductor device of present embodiment, suppress NiSi simultaneously ₂The formation of film, and confirmed to reduce interface roughness between silicon substrate and the NiSi film.

(evaluation result (part 2))

Measure the junction leakage of the source/drain diffusion layer of MOS transistor, this MOS transistor is to be produced by the method that is used to make according to the semiconductor device of present embodiment.On the transistorized p type of the PMOS that is injected with boron ion source/drain diffusion layer, measure junction leakage.

In this was measured, as shown in figure 20, via contact plug 84b and electronic pads 94a, negative voltage was applied in the source/drain diffusion layer 64 on grid 54 1 sides.Via contact plug 84b and electronic pads 94b, positive voltage is applied in n type trap 40, does not have source/drain diffusion layer to be formed on the opposite side of grid 54 at n type trap 40.Then, measure junction leakage, this electric current flows through when reverse biased acts between source/drain diffusion layer 64 and the trap 40 (grid 54 is between between the two).In example of describing subsequently 2 and control 4 to 6, on a plurality of samples, measure junction leakage, and draw the cumulative probability of these samples respectively.Figure 21 is the figure of measurement result.On trunnion axis, near the junction leakage component of the source/drain diffusion layer the expression grid, on vertical axis, the expression cumulative probability.

In Figure 21, the  mark is drawn and is represented the measurement result of example 2 (promptly being used to make the method according to the semiconductor device of present embodiment).In example 2, the TiN film is formed on the Ni film of 20m thickness, and first heat treatment was carried out 30 seconds at 270 ℃.Then, by cleaning with ammonia/hydrogen peroxide mixture and thiosulfonic acid/hydrogen peroxide mixture, selective removal as yet not with TiN film and a part of Ni film of Si reaction, second heat treatment was carried out 30 seconds at 500 ℃ then.

In Figure 21, ● mark is drawn and is represented the measurement result of control 4, forms the Ni film of relative thin and carry out a heat treatment in this control 4.In control 4, the TiN film is formed on the Ni film of 10nm thickness, and 400 ℃ of heat treatments of carrying out one time 30 seconds.Then, clean by ammonia/hydrogen peroxide mixture and thiosulfonic acid/hydrogen peroxide mixture, selective removal as yet not with TiN film and a part of Ni film of Si reaction.

In Figure 21, the △ mark is drawn and is represented the measurement result of control 5, forms the Ni film of relative thin and carry out twice heat treatment in this control 5.In control 5, the TiN film is formed on the Ni film of 10nm thickness, and first heat treatment was carried out 30 seconds at 300 ℃.Then, by utilizing ammonia/hydrogen peroxide mixture and thiosulfonic acid/hydrogen peroxide mixture to clean, after selective removal TiN film and a part of Ni film, second heat treatment was carried out 30 seconds at 500 ℃.

In Figure 21, the ■ mark is drawn and is represented the measurement result of control 6, forms cobalt disilicide (CoSi in this control 6 ₂) film, the replacement nickel silicide film.In control 6, as being used for the metal film that silicide forms, substitute the Co film that the Ni film forms 4nm thickness, and form CoSi by heat treatment ₂Film.

Obviously find out the comparison between the drawing of example 2 and each control, at example 2 (wherein, relatively large thickness with 20nm forms the Ni film, and first heat treatment is carried out under 270 ℃ relatively lower temp) in, it is very little that junction leakage is compared with control 4 and 5 (wherein, the less thickness with 10nm forms the Ni film).The junction leakage of example 2 (wherein, forms CoSi with control 6 ₂Film) compares and decrease.

Based on control 4 and 5 result, can find, when the Ni film form during relative thin, no matter how high the first heat treated temperature have, and can't fully reduce junction leakage.

(evaluation result (part 3))

And, on MOS transistor, measure the sheet resistance of grid, this MOS transistor is to be produced by the method that is used to make according to the semiconductor device of present embodiment.This MOS transistor is the PMOS transistor.The impurity ion that injects in the grid is a boron.The grid length of grid is 40nm.In example 2 and control 4 to 6, on a plurality of samples, measure sheet resistance, and draw the cumulative probability of these samples respectively.Figure 22 is the figure of measurement result.On trunnion axis, the sheet resistance of expression grid, on vertical axis, the expression cumulative probability.In Figure 22, the  mark is drawn and is represented the measurement result of example 2, ● mark is drawn and is represented to control 4 measurement result, and the △ mark is drawn and represented the measurement result of control 5, and the measurement result of control 6 is represented in the drawing of ■ mark.

Find out obviously the comparison between each is drawn that in example 2, comparing of sheet resistance and control 5 (wherein, Ni film form relative thin) is much smaller.The sheet resistance of example 2 is reduced to and is equal to or less than control 6 (wherein, formation CoSi substantially ₂Film) sheet resistance.

Based on the above-mentioned measurement result of junction leakage and sheet resistance, can confirm to be used to make the sheet resistance that method according to the semiconductor device of present embodiment can reduce the junction leakage of source/drain diffusion layer and be formed with the grid upside of silicide film on it.

As mentioned above, according to present embodiment, Ni film 66 is formed thick relatively appointed thickness, and by first heat treatment, a part of Ni film 66 on the downside and Si reaction are to form Ni ₂Si film 70a, 70b remove as yet not a part of Ni film 66 with the Si reaction, then by second heat treatment, and Ni ₂Si film 70a, 70b and Si reaction can form NiSi film 72a, the 72b of high-quality with required film thickness thus, suppress high-resistance NiSi simultaneously ₂The formation of film.Therefore, the rough interface degree between the interface between grid 54 and the NiSi film 72a, source/drain diffusion layer 64 and the NiSi film 72b can diminish, and the sheet resistance on the surface of surface that can suppressor grid 54 and source/drain diffusion layer 64 disperses.Can also suppress junction leakage.

(remodeling)

The method that explanation is used to make the semiconductor device of retrofiting according to present embodiment.

The method that is used to make according to the semiconductor device of this remodeling is characterised in that, in the method that is used for making according to the semiconductor device of the foregoing description, carried out constantly to carrying out the first heat treated step from the step that forms Ni film 66, and be not exposed in the atmospheric air.

Until the step till the step of formation source/drain diffusion layer 64 is identical with the method that is used to make according to the semiconductor device of the foregoing description as shown in Fig. 8 A to 15A, will omit their explanation here.

Then, for example by handle formed primary oxide film on the surface of removal grid 54 and the surface of source/drain diffusion layer 64 with hydrofluoric acid.

Then, on whole surface, form for example Ni film 66 of 20nm thickness.The film thickness of Ni film 66 (contains 17nm) more than 17nm.Preferably, the film thickness of Ni film 66 (is containing 200nm) below the 200nm because must remove as yet not the part of the Ni film 66 that reacts with Si after silicide forms.

Here, Ni film 66 is formed in the membrane formation device, and this device can form and the multiple metal film of heat treatment in same chamber constantly, and can not be exposed in the atmospheric air.In such membrane formation device,, form metal film for example by sputter deposited etc.Therefore, the formation of Ni film 66, the formation, first heat treatment that are formed at the diaphragm 68 etc. of the TiN film on the Ni film 66 are carried out constantly, and can not be exposed in the atmospheric air.

Then, in this chamber,, form for example diaphragm 68 of the TiN film of 5 to 50nm thickness constantly forming Ni film 66 parts.Diaphragm 68 is also nonessentially formed by the TiN film.Diaphragm 68 for example can be formed by the Ti film of 5 to 30nm thickness.

In this remodeling, after forming Ni film 66, the substrate that exposes Ni film 66 neither is transferred also without undergoing the processing in another device, but diaphragm 68 is formed in the combustion chamber that has formed Ni film 66 constantly.Therefore, can prevent the secondary pollution of Ni effectively.

Then, in the chamber that forms Ni film 66 and diaphragm 68, for example the RTA by carrying out 30 seconds at 270 ℃ is used for first heat treatment that silicide forms constantly.Thus, a part of Ni in Ni film 66 on the downside and a part of Si on the upside in grid 64 react to each other, and Ni in a part of Ni film 66 on downside and a part of Si on the upside in source/drain diffusion layer 64 react to each other.Thus, Ni ₂Si film 70a, 70b are formed on the gate electrode 54 and on source/drain diffusion layer 64.

It is identical with the method step that is used to make according to the semiconductor device of the foregoing description to follow the first heat treated step, and will omit their explanation.

As mentioned above, in the method that is used for making according to the semiconductor device of this remodeling, same device, carried out constantly to carrying out the first heat treated step from the step that forms Ni film 66, and be not exposed in the atmospheric air.Therefore, the formation that can carry out Ni film 66 is until first heat treatment, and the surface of Ni film 66 can be exposed to atmospheric air.Thus, can suppress the surface oxidation of Ni film 66, and silicide film can have good quality.Another annealing device then is unwanted for first heat treatment, and this can improve the output of manufacturing step.

Diaphragm 68 is formed in the chamber that forms Ni film 66 constantly, and this can prevent the secondary pollution of Ni effectively.

[second embodiment]

With reference to Figure 23 A to 23C, semiconductor device and the method that is used to make this semiconductor device according to second embodiment of the invention are described.Figure 23 A to 23C is that these figure have illustrated this method according to the semiconductor device of the present embodiment sectional view at the method step that is used for making this semiconductor device.Present embodiment is to be represented by identical label with semiconductor device and manufacture method components identical thereof according to first embodiment shown in Fig. 7 to 18A-18C, in order to avoid repeat or in order to simplify their explanation.

According to the semiconductor device of present embodiment structurally with basic identical according to the semiconductor device of first embodiment, but with the latter's different methods that are to make this semiconductor device.

That is to say, the method that is used to make according to the semiconductor device of present embodiment is characterised in that, in the method that is used for making according to the semiconductor device of first embodiment, before being used for first heat treatment that silicide forms, by injecting the Ni ion, make Ni film 66 amorphous states.

At first, until the step till the step of formation source/drain diffusion layer 64 is identical with the method step that is used to make the semiconductor device of first embodiment shown in Fig. 8 A to 15A, and will omit their explanation.

Then, carry out splash, on whole surface, form for example Ni film 66 of 20nm thickness (seeing Figure 23 A) by utilizing the Ni target.The film thickness of Ni film 66 (contains 17nm) more than 17nm.The film thickness of Ni film 66 preferably (contains 200nm) below 200nm, because after silicide forms, must inerrably remove as yet not a part of Ni film 66 with the Si reaction.

Then, before first heat treatment that is used for silicide formation, the Ni ion is injected in the Ni film 66 (sees Figure 23 B).Thus, according to the film thickness of Ni film 66, suitably set the condition that the Ni ion injects.When the film thickness of Ni film 66 for example was 20nm, as the condition that ion injects, acceleration energy for example was 5keV.When the film thickness of Ni film 66 for example was 200nm, as the condition that ion injects, acceleration energy for example was 500keV.This dosage can be to make Ni film 66 amorphous amounts, for example 1 * 10 ¹⁴To 1 * 10 ¹⁵Cm ^-2

Then, for example by PVD, on amorphous state Ni film 66, form for example diaphragm 68 of the TiN film of 5 to 50nm thickness (seeing Figure 23 C).Diaphragm 68 is used to prevent Ni film 66 and the nickel silicide film generation oxidation that forms on it.Diaphragm 68 is also nonessentially formed by the TiN film.Diaphragm 68 can be formed by for example Ti film of 5 to 30nm thickness.

It is identical with the method step that is used to make according to the semiconductor device of first embodiment shown in Figure 16 A to 18C to follow step that diaphragm 68 forms, and will omit their explanation.

As mentioned above, in the method that is used for making according to the semiconductor device of present embodiment, before first heat treatment that is used for silicide formation, the Ni ion is injected in the Ni film 66 by ion, makes Ni film 66 amorphous states thus.Therefore, be used for first heat treatment that silicide forms, Ni in the Ni film 66 and Si react, and it is with than being not that the higher speed of Ni in amorphous Ni film spreads.Therefore, in first heat treatment, can be effectively and stably form Ni ₂Si film 70a, 70b.Thus, can form high-

quality NiSi film

72a, 72b, further effectively suppress NiSi simultaneously ₂The formation of film.

In the present embodiment, inject, make Ni film 66 amorphous states by the Ni ion.Yet, being used to make Ni film 66 amorphous methods to be not limited to ion injects, and can be by for example very high splash deposited at rates Ni of 1 nm/sec above (containing 1 nm/sec), make Ni film 66 amorphous states, perhaps, make Ni film 66 amorphous states by under high argon (Ar) pressure that for example (contains 5 millitorrs) more than 5 millitorrs (mTorr), carrying out splash.Even when by such processing, when making the minimum micronize of Ni film 66, also can obtain and the identical effect of effect that Ni film 66 amorphous states are obtained.It is that mean particle dia with forming the particulate of metal film is reduced to nanoscale that minimum micronize is here looked like.

The unexamined patent application Hei 09-251967 (1997) of Japanese publication discloses: in the salicide processes of utilizing the Co film, its purpose is to suppress CoSi _XThe generation (this is the reason that produces junction leakage) of supernormal growth (pulse), before the Co film is formed on the silicon substrate, make the silicon substrate amorphous state.Yet, disclosed method (wherein among the unexamined patent application Hei 09-251967 (1997) of Japanese publication, make the silicon substrate amorphous state) with the method irrelevant (wherein, in the salicide processes of utilizing the Ni film, making Ni film amorphous state) that is used to make according to the semiconductor device of present embodiment.

[remodeling embodiment]

The invention is not restricted to the foregoing description, and can cover other various remodeling.

For example, in the above-described embodiments, carry out salicide processes, on grid 54 and source/drain diffusion layer 64, to form NiSi film 72a, 72b.Yet, in the present invention,

NiSi film

72a, 72b and nonessential being formed on grid 54 and the source/drain diffusion layer 64, and the NiSi film can be formed at grid 54 and source/drain diffusion layer 64 the two one of on.

In the above-described embodiments, carry out first and second heat treatments by RTA.Yet first and second heat treatments also nonessentially are limited to RTA heat treatment.For example, first and second heat treatments can be annealed by smelting furnace, pulse annealing waits and carries out.Can suitably make up the heat treatment of RTA, smelting furnace annealing and pulse annealing.

Be used for the condition that the first heat treated condition is not limited to the foregoing description.In first heat treatment, heat treatment temperature for example can be 200 to 400 ℃.Processing time for example can 10 seconds to 60 minutes.

Be used for the condition that the second heat treated condition is not limited to the foregoing description.In second heat treatment, heat treatment temperature can be equal to or higher than the first heat treated temperature substantially, particularly, and for example 350 to 650 ℃.Heat treatment time for example can be 10 seconds to 60 minutes.In addition, second heat treatment can be undertaken by 450 to 650 ℃ pulse annealing.

In the above-described embodiments, Ni film 66 forms by splash.Yet Ni film 66 also nonessentially forms by splash.Ni film 66 for example can wait by the vapour deposition outside the splash, electron-beam vapor deposition and form.

In the above-described embodiments, diaphragm 68 is formed on the Ni film 66, but can not form.Be formed with the substrate of Ni film when being installed on it, this Ni film is exposed on the box that is used for transport substrates or is loaded into the smelting furnace of RTA device or during the chamber of film deposition apparatus, box, smelting furnace or chamber are polluted by Ni, and the particulate of Ni usually adheres to other substrates, these other substrates be installed on the box subsequently or be loaded on the smelting furnace of RTA device or the chamber of film deposition apparatus in.Be formed at diaphragm 68 on the Ni film 66 and can prevent the secondary pollution of Ni.

Claims

1. semiconductor device comprises:

Grid is formed on the Semiconductor substrate;

Source/drain diffusion layer is formed in the Semiconductor substrate on these grid both sides; And

Silicide film is formed on this source/drain diffusion layer,

This silicide film is formed by single nickle silicide, and

The film thickness of this silicide film is 20nm or below the 20nm.

2. semiconductor device as claimed in claim 1 also comprises:

Another silicide film is formed on this grid;

Described another silicide film is formed by single nickle silicide, and

The film thickness of described another silicide film is 20nm or below the 20nm.

3. method that is used for producing the semiconductor devices comprises:

On Semiconductor substrate, form the step of grid;

The step of formation source/drain diffusion layer in the Semiconductor substrate on these grid both sides;

On this source/drain diffusion layer, form the step of nickel film;

First heat treatment step by the part of heat treatment nickel film downside and the part of source/drain diffusion layer upside, reacts to each other it, to form nickel silicide film on this source/drain diffusion layer;

Selective etch falls the step of still unreacted a part of nickel film; And

Second heat treatment step further makes the part of this nickel silicide film and source/drain diffusion layer upside react to each other.

4. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

In the step that forms this nickel film, this nickel film is formed 17nm or the above thickness of 17nm.

5. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

In the step that forms this nickel film, this nickel film further is formed on this grid,

In this first heat treatment step, the part of nickel film downside and the part of grid upside react to each other, with the further nickel silicide film that forms on this grid,

Fall in the step of still unreacted this part of nickel film at selective etch, still unreacted a part of nickel film is etched away by selectivity on this grid, and

In this second heat treatment step, the part of nickel silicide film on this grid and grid upside further reacts to each other.

6. the method that is used for producing the semiconductor devices as claimed in claim 4, wherein:

In this second heat treatment step, this nickel silicide film on this grid and the part of grid upside further react to each other.

7. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

Heat treatment temperature in this second heat treatment step is higher than the heat treatment temperature in this first heat treatment step.

8. the method that is used for producing the semiconductor devices as claimed in claim 4, wherein:

9. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

Heat treatment temperature in this first heat treatment step is 200 to 400 ℃, and

Heat treatment temperature in this second heat treatment step is 350 to 650 ℃.

10. the method that is used for producing the semiconductor devices as claimed in claim 4, wherein:

11. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

In this second heat treatment step, carry out this heat treatment by 450 to 650 ℃ pulse annealing.

12. the method that is used for producing the semiconductor devices as claimed in claim 4, wherein:

13. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

In the step that forms this nickel film, form this nickel film by splash.

14. the method that is used for producing the semiconductor devices as claimed in claim 4, wherein:

In the step that forms this nickel film, form this nickel film by splash.

15. the method that is used for producing the semiconductor devices as claimed in claim 3 after the step that forms this nickel film and before this first heat treatment step, also comprises:

Make the amorphous step of this nickel film.

16. the method that is used for producing the semiconductor devices as claimed in claim 4 after the step that forms this nickel film and before this first heat treatment step, also comprises:

Make the amorphous step of this nickel film.

17. the method that is used for producing the semiconductor devices as claimed in claim 15, wherein:

In making the amorphous step of this nickel film, inject nickel ion to this nickel film by ion, make this nickel film amorphous state.

18. the method that is used for producing the semiconductor devices as claimed in claim 17, wherein:

In making the amorphous step of this nickel film, with 5 to 500keV acceleration energies and 1 * 10 ¹⁴To 1 * 10 ¹⁵Cm ^-2Dosage, ion inject described nickel ion to this nickel film.

19. the method that is used for producing the semiconductor devices as claimed in claim 3 after the step that forms this nickel film and before this first heat treatment step, also comprises:

On this nickel film, be formed for preventing the step of the diaphragm of this nickel film oxidation.

20. the method that is used for producing the semiconductor devices as claimed in claim 3, wherein:

Carried out constantly to this first heat treatment step from the step that forms this nickel film, and be not exposed in the atmospheric air.