CN1687912A - Method and apparatus for fast reading and writing memory data - Google Patents
Method and apparatus for fast reading and writing memory data Download PDFInfo
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- CN1687912A CN1687912A CN 200510073316 CN200510073316A CN1687912A CN 1687912 A CN1687912 A CN 1687912A CN 200510073316 CN200510073316 CN 200510073316 CN 200510073316 A CN200510073316 A CN 200510073316A CN 1687912 A CN1687912 A CN 1687912A
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Abstract
The invention is a device for fast reading and writing memory data, comprising a memory module and a north bridge chip set, used to make power-on self-test after the computer starts up, and the memory module is provided with many memory cells and the north bridge chip set comprises a programmable buffer module and a memory module controller, where the programmable buffer module stores at least a preset data and the memory module controller carries out burst read or write for all the memory cells according to the preset data.
Description
Technical field
The present invention relates to a kind of method and device of fast reading and writing memory data, particularly a kind of method and device that does not need the fast reading and writing memory data controlled by CPU.
Background technology
With development of computer application technology, CPU (central processing unit) (CPU) was by 8086 o'clock processor development processors of 64 so far on behalf of 16 (bit), its processing speed has the progress of highly significant, add the system that two CPU are also arranged on the market and exist, also improve processing speed and usefulness many.
Though the processing speed of CPU has significant lifting, but general employed dynamic RAM (DRAM) in computing machine, its speed lags far behind present CPU processing speed, and before using DRAM, execution earlier refreshes (refresh) operation just can be used, and has more reduced its execution speed.For avoiding storer to become the bottleneck of CPU speed, present CPU has designed high-speed cache (cache), is used for the temporary data of needs at present, and cooperation is directly write (write through) or write-back (write back) technology improves the access speed of data again.
Yet processing speed is fast more, just easy more generation data access mistake to memory data access the time.When storage access mistake (RAM accesserror) takes place during at executive routine in computing machine, just can the initiator fault, when serious then again activation system can recover; This moment is if it is important data and not deposit then can cause user's heavy losses that couple user is arranged, if break down and need start again at the huge server of data volume, its loss will be more considerable.Therefore, the technician develops a kind of error checking and correction (ECC) (error checking andcorrecting, ECC) function is to avoid taking place above-mentioned condition.
In system, need when activating earlier memory refress just can be used for one time in system with ECC function.Suppose in one 64 systems (64 equal 8 bytes and equal 1QW (quadword)) that the read-write length of storer (burst length) is 8, the length of high-speed cache is that 8QW and CPU once refresh 4 bytes.Under situation without high-speed cache (cache off), if the data of 8QW (64 byte) are arranged, need carry out read-modify-write (ReadModify Write because have the storer of ECC function, RMW) operation, this operation is the data of earlier data read of 8QW being revised CPU again to north bridge chips and being write, last again with the data write-back DRAM of 8QW, and CPU whenever refreshes 4 bytes and just needs to carry out a read operation and a write operation, so need 16 times read and 16 times write altogether.If the use direct writing technology then needs earlier the data of 8QW to be read to the high speed buffer memory, carry out 16 read operations and 16 write operations again, therefore need 17 read operations and 16 write operations altogether.If under the situation of using high-speed cache (cache on), use the write-back technology, then need the data of 8QW are read earlier to the high speed buffer memory, be ready to the data that will write by CPU, again data are written back to storer, therefore need 1 read operation and 1 write operation.
Above-mentioned way obviously will be wasted many times if be applied in the present system that has easily above the 1GB storer when activation system.Therefore, how to accelerate the time of reading and writing memory data to reduce system's activationary time, real one of the current important topic that belongs to.
Summary of the invention
In view of above-mentioned problem, the purpose of this invention is to provide a kind of method and device thereof of fast reading and writing memory data.
Therefore, for reaching above-mentioned purpose, include a memory module and a north bridge chipset according to the device of fast reading and writing memory data of the present invention, its be used to carry out behind the computer booting Power-On Self-Test (power on self test, POST).Memory module has a plurality of storage unit (memory cell), and north bridge chipset comprises a buffer module able to programme and a memory module controller, buffer module wherein able to programme is stored at least one presupposed information, the memory module controller is then according to being stored in presupposed information in the buffer module able to programme, and carries out at all storage unit that burst type reads (burst read) or burst type writes (burst write).
In addition, the present invention also discloses a kind of method of fast reading and writing memory data, the method is used in the computer system, this computer system has a north bridge chipset and a memory module, wherein be provided with a memory module controller and a buffer module able to programme in the north bridge chipset at least, buffer module able to programme stores at least one presupposed information, and memory module has a plurality of storage unit, and the method for this fast reading and writing memory data comprises following steps:
At first, by one substantially output/input system module transmit initialize signal to a north bridge chipset;
Then, transmit enabling signal to a memory module controller by north bridge chipset;
At last, according to being stored at least one presupposed information of a buffer module able to programme, and carry out at storage unit that burst type reads or burst type writes by the memory module controller.
In sum, because of method and device thereof according to fast reading and writing memory data of the present invention pass through to increase buffer module able to programme in north bridge chipset, transmit signal by basic output/input system module again and give north bridge chipset, so the memory module controller is able to according to the presupposed information in the buffer module able to programme, and directly memory module is read and write, thereby need not control by CPU.
Description of drawings
Fig. 1 is the synoptic diagram of demonstration according to the device of the quick reading memory data of preferred embodiment of the present invention;
Fig. 2 is demonstration another synoptic diagram according to the device of the quick reading memory data of preferred embodiment of the present invention;
Fig. 3 is the process flow diagram of demonstration according to the method for the quick reading memory data of preferred embodiment of the present invention.
The element numbers complete list
| Reference numeral | Assembly | Reference numeral | Assembly |
| ??11 | Basic output/input system module | ????S 1 | Initialize signal |
| ??12 | Memory module | ????S 2 | Enabling signal |
| ??121 | Storage unit | ????S 3 | Address signal |
| ??13 | North bridge chipset | ????I 1 | Presupposed information |
| ??131 | The memory module controller | ????D1 | Programmable data |
| ??132 | Buffer module able to programme | ????R 1 | Address Register |
| ??14 | Memory bus | ????R 2 | Data buffer |
| ????P 1～P 3 | The process step of the method for quick reading memory data |
Embodiment
Hereinafter with reference to relevant drawings, method and device thereof according to the fast reading and writing memory data of preferred embodiment of the present invention are described, wherein identical assembly will be illustrated with identical Reference numeral.
Please refer to shown in Figure 1, the device of the fast reading and writing memory material of preferred embodiment of the present invention comprise one substantially output/input system ((BIOS) module 11, a memory module 12, a north bridge chipset 13 are used to carry out the Power-On Self-Test (POST) behind the computer booting.
Basic output/input system module 11 produces initialize signal S
1, this signal is sent to north bridge chipset 13.
Memory module 12 has a plurality of storage unit (memory cell) 121, and in the present embodiment, memory module 12 can be a dynamic RAM (DRAM) module.
North bridge chipset 13 comprises a memory module controller 131 and a buffer module 132 able to programme, and in the present embodiment, buffer module 132 able to programme stores at least one presupposed information I
1, memory module controller 131 is then according to presupposed information I
1,, carry out at storage unit 121 that burst type reads (burst read) or burst type writes (burstwrite) by a memory bus 14.
Please refer to shown in Figure 2ly again, in the present embodiment, buffer module 132 able to programme also can comprise an Address Register R
1An and data buffer R
2At Address Register R
1In store at least one address date, convert address date to address signal S by buffer module 132 able to programme again
3And be sent to memory module controller 131.In the present embodiment, address date can comprise an initial address date and end address data again, and buffer module able to programme 132 can be converted to an initial address signal and an end address signal with start address data and end address data.In the present embodiment, address date is represented the address of the storage unit 121 of memory module 12.And at data buffer R
2In, store at least one programmable data D
1, its content then is the data that will write in the storage unit 121 of memory module 12.
Referring now to Fig. 3 and cooperate shown in Figure 2, method according to the fast reading and writing memory data of preferred embodiment of the present invention is described, the method is used in one to be had in the computer system of north bridge chipset 13 and memory module 12, wherein north bridge chipset 13 is provided with a memory module controller 131 and a buffer module 132 able to programme at least, and stores at least one presupposed information I in buffer module 132 able to programme
1, in addition, memory module 12 has a plurality of storage unit 121, and in the present embodiment, memory module 12 can be a dynamic RAM (DRAM) module, and the method for this fast reading and writing memory data comprises following process step:
At first, process step P
1Be by one substantially output/input system module 11 transmit an initialize signal S
1To north bridge chipset, in the present embodiment, initialize signal S
1Be to produce in Power-On Self-Test stage behind computer booting.
Then, process step P
2Be by north bridge chipset 13, receiving initialize signal S
1Promptly produce an enabling signal S afterwards
2, and this signal is sent to memory module controller 131.
At last, process step P
3Be by memory module controller 131, according to the presupposed information I that is stored in the buffer module 132 able to programme
1And carry out at storage unit 121 that burst type reads or burst type writes, in the present embodiment, burst type reads or burst type is write fashionable when memory module controller 131 is carried out, do not need to control, that is CPU (central processing unit) need not waited for after memory module controller 131 executes the operation of reading or writing and carries out all the other programs again by CPU (central processing unit).
For making the technician can further understand the present invention, below will lift an example so that the method and apparatus of fast reading and writing memory data of the present invention to be described.
With performed error checking and correction (ECC) of Power-On Self-Test stage behind the computer booting (Error checkingand correcting, ECC) be example, memory module with ECC function must just can be used its content refresh for one time before use, hypothesis has the memory module of 1GB now again, and will be zero with its content refresh.
At this moment, basic output/input system module 11 can produce an initialize signal S
1And be sent to north bridge chipset 13.North bridge chipset then can produce an enabling signal S
2And be sent to memory module controller 131, then memory module controller 131 can be by extracting presupposed information I in the buffer module 132 able to programme
1Presupposed information I
1Can pre-deposit, or at initialize signal S
1Being set up on their own by the user during generation, in the present embodiment, is at Address Register R
1In to preestablish the start address data be 0 and the end address data are 1G, then at data buffer R
2In preestablish programmable data D
1Be 0 (that is, being 0 with 0 to 1G address flush in the memory module), last, memory module controller 131 can be according to presupposed information I
1, via memory bus 14 memory module 12 is carried out burst type and write, among 0 write once memory module, and do not need to write by CPU.
Said method also can be used for doing memory bus signal integration test usefulness, and for example data strobe signal input (DQSI) or data strobe signal output (DQSO) all is Power-On Self-Test stage execution behind computer booting.
In sum, because of according to the method for fast reading and writing memory data of the present invention and device by means of in north bridge chipset, increasing buffer module able to programme, make that the memory module controller in the north bridge chipset can be according to the presupposed information in the buffer module able to programme, and directly memory module is read and write, and need not control by CPU, and can once read or the operation of write-once according to the direct execution of memory address range that sets, need to write the time of being wasted while reading thereby saved prior art.
More than explanation only is exemplary, but not determinate.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the scope of claims its equivalent modifications of carrying out or change.
Claims (13)
1, a kind of device of fast reading and writing memory data is used to carry out the Power-On Self-Test behind the computer booting, and the device of this fast reading and writing memory data comprises:
One memory module, it has a plurality of storage unit; And
One north bridge chipset, it comprises a buffer module able to programme and a memory module controller, wherein this buffer module able to programme stores at least one presupposed information, this memory module controller is then according to being stored in this presupposed information in this buffer module able to programme, and carries out at all described storage unit that burst type reads or burst type writes.
2, the device of fast reading and writing memory data as claimed in claim 1, wherein this presupposed information comprises at least one address signal, and wherein this address signal further comprises an initial address signal and an end address signal.
3, the device of fast reading and writing memory data as claimed in claim 2, wherein this buffer module able to programme further comprises:
One Address Register, it stores at least one address date, and this buffer module able to programme is converted to this address signal with this address date, and wherein this address date further comprises an initial address date and end address data.
4, the device of fast reading and writing memory data as claimed in claim 1, wherein this presupposed information comprises at least one programmable data.
5, the device of fast reading and writing memory data as claimed in claim 4, wherein this buffer module able to programme further comprises:
One data buffer, it stores these programmable datas.
6, the device of fast reading and writing memory data as claimed in claim 1, wherein this memory module is a dynamic RAM module.
7, the device of fast reading and writing memory data as claimed in claim 1 further comprises:
One output/input system module substantially, its generation is sent to an initialize signal of this north bridge chipset, to activate this memory module controller, carries out at all described storage unit according to this presupposed information that burst type reads or burst type writes.
8, the device of fast reading and writing memory data as claimed in claim 7, wherein this initialize signal is to produce in Power-On Self-Test stage behind computer booting.
9, the device of fast reading and writing memory data as claimed in claim 8, wherein this Power-On Self-Test stage also comprises execution one error checking and correction (ECC) or carries out data strobe signal output test or carry out a data strobe signal input test.
10, a kind of method of fast reading and writing memory data, be used to have the computer system of a north bridge chipset and a memory module, wherein be provided with a memory module controller and a buffer module able to programme in this north bridge chipset at least, this buffer module able to programme stores at least one presupposed information, and this memory module has a plurality of storage unit, and the method for this fast reading and writing memory data comprises following steps:
By one substantially output/input system module transmit an initialize signal to this north bridge chipset;
Transmit an enabling signal to this memory module controller by this north bridge chipset; And
This memory module controller is according to this presupposed information that is stored in this buffer module able to programme, and carries out at all described storage unit that burst type reads or burst type writes.
11, the method for fast reading and writing memory data as claimed in claim 10 wherein carries out that burst type reads or burst type is write fashionablely when this memory module controller, does not need by central processing unit controls.
12, the method for fast reading and writing memory data as claimed in claim 10, wherein this initialize signal is to produce in Power-On Self-Test stage behind computer booting.
13, the method for fast reading and writing memory data as claimed in claim 12, wherein this Power-On Self-Test stage also comprises execution one error checking and correction (ECC) or carries out data strobe signal output test or carry out a data strobe signal input test.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073316 CN100342361C (en) | 2005-05-31 | 2005-05-31 | Method and apparatus for fast reading and writing memory data |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073316 CN100342361C (en) | 2005-05-31 | 2005-05-31 | Method and apparatus for fast reading and writing memory data |
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| CN100342361C CN100342361C (en) | 2007-10-10 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436135B (en) * | 2007-11-15 | 2012-04-04 | 英业达股份有限公司 | Initialized setting system and method of options read only memory |
| CN103744744A (en) * | 2014-02-08 | 2014-04-23 | 威盛电子股份有限公司 | Data storage device and data checking method of volatile storage |
| US8749353B2 (en) | 2010-03-01 | 2014-06-10 | Abb Research Ltd. | Wireless communication between two temporarily connected devices |
| CN105373501A (en) * | 2015-07-31 | 2016-03-02 | 福州瑞芯微电子股份有限公司 | Clock cycle control method and device for bus module and loop filter module |
-
2005
- 2005-05-31 CN CN 200510073316 patent/CN100342361C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436135B (en) * | 2007-11-15 | 2012-04-04 | 英业达股份有限公司 | Initialized setting system and method of options read only memory |
| US8749353B2 (en) | 2010-03-01 | 2014-06-10 | Abb Research Ltd. | Wireless communication between two temporarily connected devices |
| CN103744744A (en) * | 2014-02-08 | 2014-04-23 | 威盛电子股份有限公司 | Data storage device and data checking method of volatile storage |
| CN105373501A (en) * | 2015-07-31 | 2016-03-02 | 福州瑞芯微电子股份有限公司 | Clock cycle control method and device for bus module and loop filter module |
| CN105373501B (en) * | 2015-07-31 | 2018-08-31 | 福州瑞芯微电子股份有限公司 | A kind of the clock rotation control method and device of bus module and loop filtering module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100342361C (en) | 2007-10-10 |
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