CN1685620A - Circuit for recursively calculating data - Google Patents
Circuit for recursively calculating data Download PDFInfo
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- CN1685620A CN1685620A CNA038227371A CN03822737A CN1685620A CN 1685620 A CN1685620 A CN 1685620A CN A038227371 A CNA038227371 A CN A038227371A CN 03822737 A CN03822737 A CN 03822737A CN 1685620 A CN1685620 A CN 1685620A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
- H03M13/2714—Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/276—Interleaving address generation
- H03M13/2764—Circuits therefore
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3884—Pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
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Abstract
The invention relates to a circuit for calculating a second data set based on a first data set calculated by at least a calculation device ( 31 ) that is capable of calculating a data in a predefined number of clock cycles. The calculation device has an input ( 311 ) and an output ( 312 ). The circuit comprises transport means ( 32 ) for routing a data of the first data set from the output to the input of said calculation device, in a number of clock cycles depending on the number of data of the first data set and on the predefined number of cycles necessary for the calculation of one data. A data advances through said transport means with each clock cycle.
Description
Technical field
The present invention relates to a circuit, this circuit is based on the first data set computing, second data set, obtain first data set by at least one arithmetic facility computing, this arithmetic facility can be in the predefined clock cycle data of computing, above-mentioned arithmetic facility has an input and an output.
The invention still further relates to a system, be used for the interior substitutional element of row of an interleaver of computing (interleaver), a decoding circuit that comprises this system, an electronic equipment and a communication network that comprises this decoding circuit.
The present invention generates an application, for example, and in a satellite communication system or a system that adopts UMTS (UMTS=Universal Mobile Telecommunications System) standard, such as a third generation mobile.
Background technology
Some data handling system is carried out the recursive operation of data, and data set of its computing need be based on the another one data set.For example can carry out a data b
jThe computing of [i], wherein i and j are coefficient, and i changes to n from 0, and j changes to m from 0, and m and n are nonzero integer.This is typical computing in the computing of power matrix.
Fig. 1 is the example that such treatment system is wanted the data of computing.In the present example, integer m is 9, and Integer n is 4.Want 5 data sets of computing, b
0[0] to b
9[0], b
0[1] to b
9[1], b
0[2] to b
9[2], b
0[3] to b
9[3], b
0[4] to b
9[4].Treatment system is computing b respectively
0[0] to b
9[0], is b then
0[1] to b
9[1], the rest may be inferred.A data set is based on data set the preceding.For example, b
0[1] be about b
0[0] a function f:
b
0[1]＝f(b
0[0])
Similarly, b
1[1]=f (b
1[0]), b
2[1]=f (b
2[0]), the rest may be inferred.Usually:
b
i[i+1]＝f(b
j[i])
Fig. 2 shows a circuit carrying out above-mentioned computing.This circuit comprises 21, one controllers 22 of a memory and an arithmetic facility 23.Following example has been narrated based on the first data set b
0[1] to b
9[1] the computing second data set b
0[2] to b
9[2].In the present example, adopt data of arithmetic facility 23 computings to need a clock cycle.The first data set b
0[1] to b
9[1] storage is in memory 21.In a clock cycle, with b
0[1] send to arithmetic facility 23, this equipment is computing b then
0[2].Then with this storage in memory 21.In the next clock cycle, with b
1[1] send to arithmetic facility 23, this equipment is computing b then
1[2].Then with this storage in memory 21.Circuit is handled similarly from b
2[2] to b
9[2] computing.
Therefore this circuit needs a random access memory and a controller.This memory and this controller occupy a large amount of silicon faces and adopt a large amount of electric currents.This is its shortcoming, particularly in the portable electric appts such as mobile phone etc.In fact, in portable electric appts, effectively silicon face is limited.And this kind equipment is battery-powered, and to battery charge, low-power consumption is necessary for fear of frequent.
Summary of the invention
An object of the present invention is to provide a kind of circuit based on the first data set computing, second data set, foregoing circuit takies less silicon plane, and lower current drain is arranged.
According to the present invention and the circuit of in beginning section, being narrated following feature is arranged, it was included in several clock cycle, first data set is transferred to the transmission equipment of input from the output of above-mentioned arithmetic facility, this clock cycle quantity depends on data bulk and necessary amount of cycles of data of predefined computing of first data set, in each clock cycle, there are data to transmit by above-mentioned transmission equipment.
When data of arithmetic facility computing first data set and when utilizing these data to carry out the data of computing second data set after several clock cycle, the data of this first data set are transferred to the input of arithmetic facility by transmission equipment, and this is operated only by above-mentioned clock control.Transmitting device is that these data arrive the input of above-mentioned arithmetic facility when arithmetic facility will be used the data of this first data set.Therefore, circuit does not need random access memory and controller, has so just reduced the power consumption of sort circuit and shared silicon face.
Advantageously, transmitting device comprises and is used to regulate the adjusting device that data is transferred to the necessary periodicity of input from the output of above-mentioned arithmetic facility.Therefore this circuit has very big flexibility.In fact, the data volume of the handled data centralization of this circuit changes.Data are transferred to the data volume that the necessary periodicity of input also depends on data set from the output of arithmetic facility.Because this adjusting device, just can be according to a function of the data volume of data set to be processed, adjusting is transferred to the necessary periodicity of input with data from the output of arithmetic facility.Therefore, this circuit can be used for handling and has different pieces of information quantity data collection.
In a preferred embodiment, transmitting device comprises at least one clock trigger register, and above-mentioned register can new data of each clock cycle storage.According to present embodiment, transmitting device only comprises the register that can store data.The silicon face that this register takies is few and current drain is little.This circuit is design easily also, and the quantity of such register is corresponding to data are transferred to the necessary periodicity of input from the output of above-mentioned arithmetic facility.
Description of drawings
With reference to following examples,, these and other aspects of the present invention can be described clearly by there not being circumscribed example.
In the drawings:
Fig. 1 shows an example of the data of wanting computing;
Fig. 2 is a block diagram, shows the circuit of prior art of the data of arithmograph 1;
Fig. 3 is a block diagram, shows according to a circuit of the present invention;
Fig. 4 is a block diagram, shows circuit according to a preferred embodiment of the present invention;
Fig. 5 shows a circuit that is used for the phase multiply accumulating according to of the present invention;
Fig. 6 shows a communication network that comprises in a circuit according to the invention;
Fig. 7 shows alternate matrix and a computing block interleaved;
Fig. 8 shows according to a circuit of the present invention, and this circuit is used for substitutional element between the row of an interleaver of computing.
Embodiment
Fig. 3 shows according to a circuit of the present invention.This circuit comprises an arithmetic facility 31 and a transmitting device 32 with an input 311 and an output 312.In this example, transmitting device comprises 9 register 321-329.Arithmetic facility 31 also receives additional data 34, for example coefficient.
It is how based on the first data set computing, second data set that the example of the following stated shows equipment by circuit among Fig. 3.This example is applied to the second data set b among Fig. 1
0[2] to b
9[2] and the first data set b
0[1] to b
9[1].
At first, based on corresponding to the data set b among Fig. 1
0[0] to b
9The data of primary data computing first data set [0].These data send to arithmetic facility 31 with the form of additional data 34.In first clock cycle, send data b
0[0] to arithmetic facility 31.Arithmetic facility 31 operational data b then
0And be stored in the register 321 [1].It should be noted data b
0[1] can walk abreast and be stored in the memory device, it does not illustrate in Fig. 1.In second clock cycle, send data b
1[0] to arithmetic facility 31.Arithmetic facility 31 operational data b then
1[1], and with it replaces b
0[1] stores in the register 321, b
0[1] sends in the register 322.In fact, register 321 to 329 is triggered by clock, and in other words, in each clock cycle, the data in a register are left this register.
Data b
2[1] to b
9[1] same operation has been adopted in computing.The tenth clock cycle, be stored in the data b in the register 329
1[0] be sent to the input 311 of arithmetic facility 31, however data b
9[1] by arithmetic facility 31 computing and be sent in the register 321.
The 11 clock cycle, arithmetic facility 31 is based on data b
0[1] data b of computing second data set
0[2].Then with this data b
0[2] be stored in the register 321.The 11 clock cycle, with the data b that is stored in the register 329
1[1] sends to the input 311 of arithmetic facility 31.The 12 clock cycle, arithmetic facility 31 operational data b
1[2] and with it be stored in the register 321.Carry out identical operations and be used for operational data b
2[2] to b
9[2].
In this example, suppose that data of arithmetic facility 31 computings need a clock cycle.Also can need a plurality of clock cycle for this computing.For example, suppose that this computing needs three clock cycle.
In first clock cycle, with data b
0[0] sends to arithmetic facility 31.Second clock cycle, with data b
1[0] sends to arithmetic facility 31.The 3rd clock cycle, with data b
2[0] sends to arithmetic facility 31.Because an operation of data needs three clock cycle, therefore at the 3rd clock cycle operational data b
0[1].Then with this storage in register 321.The tenth clock cycle, with data b
9[0] sends to arithmetic facility 31.Then, data b
0[1] be to be arranged in register 327, and be sent to arithmetic facility 31, thus the data b of initialization second data set
0[2] computing.Therefore, transmitting device 32 only needs seven registers 321 to 327.
Therefore, data are transferred to data bulk and the necessary clock cycle quantity of data of computing that the needed clock periodicity of input depends on data set from the output of arithmetic facility 31.Usually, if if data set comprises that k data and necessary clock periodicity of data of computing are 1, then data are transferred to the needed clock periodicity of input from the output of arithmetic facility 31 and are (k-1).In the example of Fig. 3, this just means the individual register that is triggered by clock of transmitting device needs (k-1).
In above-mentioned example, supposed that also computing is a pipeline-type, that is to say, in each clock cycle, send data to arithmetic facility 31.Obviously, having comprised various arithmetic facilities in a circuit according to the invention, may not be all to send data each clock cycle to arithmetic facility 31 yet.If in this case, data are transferred to data bulk and the necessary clock cycle quantity of data of computing that the needed clock periodicity of input still depends on data set from the output of an arithmetic facility, be described in detail as Fig. 5.
Fig. 4 shows a circuit according to a preferred embodiment of the present invention.Except the described element of Fig. 3, this circuit also comprises adjusting device, is used for regulating with the form of multiplexer 35 data are transferred to the necessary periodicity of input from the output of above-mentioned arithmetic facility.Control circuit control that multiplexer 35 is not illustrated among Fig. 4 can send to the input 311 of arithmetic facility 31 with being stored in data in register 323 or register 327 or the register 329.Therefore, can regulate data are transferred to the needed periodicity of input from the output of arithmetic facility 31.In fact, if be stored in the selected input that sends to arithmetic facility 31 of data in the register 323, then data being transferred to the needed periodicity of input from the output of arithmetic facility 31 is 3.If be stored in the selected input that sends to arithmetic facility 31 of data in the register 327, then data being transferred to the needed periodicity of input from the output of arithmetic facility 31 is 7.
Therefore, this circuit can be used to handle the data set with data volume variation.For example, be that pipeline-type and arithmetic facility 31 are handled a data requirement during clock cycle in the supposition computing, handle the data set that comprises four data, then be stored in the selected input 311 that sends to arithmetic facility 31 of data in the register 323.Handle the data set that comprises nine data, then select to be stored in the data in the register 327.Handle the data set that comprises ten data, then select to be stored in the data in the register 329.
Obviously, adjusting device is designed to and can selects data from each memory of register 321 to 329.Therefore, when arithmetic facility 31 is handled data and required a clock cycle, can handle and comprise that quantity is the data set of the data between 2 to 10.
Fig. 5 shows a circuit that is used for the product accumulation computing according to the present invention.This circuit comprises four arithmetic facilities 41 to 44.These arithmetic facilities all are adders.In four arithmetic facilities 41 to 44 each all is connected to 440 with a multiplier 410 respectively.Each arithmetic facility all is connected with three registers respectively, is respectively 411 to 413,421 to 423,431 to 433 and 441 to 443.
Circuit among Fig. 5 is based on 16 data d
1To d
16With 16 coefficient c
1To c
16, calculate four results of phase multiply accumulating MAC1 to MAC4.
MAC1＝c
1*d
1+c
5*d
5+c
9*d
9+c
13*d
13
MAC2＝c
2*d
2+c
6*d
6+c
10*d
10+c
14*d
14
MAC3＝c
3*d
3+c
7*d
7+c
11*d
11+c
15*d
15
MAC4＝c
4*d
4+c
8*d
8+c
12*d
12+c
16*d
16
For example using this circuit to be used in the decoding filter with MP3 format transmission data.With the form transmission data of data tape, each band is divided into a plurality of subbands.Circuit among Fig. 5 is by clock control.There are data to arrive circuit and are sent in the multiplier 410 to 440 one in each clock cycle.Data d
1Send to multiplier 410, data d
2Send to multiplier 420, data d
3Send to multiplier 430, data d
4Send to multiplier 440, data d
5Send to multiplier 410, the rest may be inferred.
In first clock cycle, coefficient c
1Send to multiplier 410, calculated data c
1* d
1, by arithmetic facility 41 it is added a value of zero then.Then with data c
1* d
1Send to register 411.At second clock cycle, coefficient c
2Send to multiplier 420, calculated data c
2* d
2, by arithmetic facility 42 it is added a value of zero then.Then with data c
2* d
2Send to register 421.Carry out similar operation and calculate c
3* d
3And c
4* d
4Value, and send it to register 431 and 441 respectively.Data c
1* d
1, c
2* d
2, c
3* d
3And c
4* d
4Form first data set.
At the 5th clock cycle, coefficient c
5Send to multiplier 410, calculated data c
5* d
5, by arithmetic facility 41 it is added data c then
1* d
1In fact, data c
1* d
1The second, three, four clock cycle have been passed through register 411,412 and 413, and the 4th clock cycle, these data are sent to arithmetic facility 41 then.Then, the data c that arithmetic facility 41 is calculated
1* d
1+ c
5* d
5Send to register 411.Carry out similar operation the 6th, seven and eight clock cycle, so that calculated data c
2* d
2+ c
6* d
6, c
3* d
3+ c
7* d
7And c
4* d
4+ c
8* d
8Data c
1* d
1+ c
5* d
5, c
2* d
2+ c
6* d
6, c
3* d
3+ c
7* d
7And c
4* d
4+ c
8* d
8Be based on second data set that first data set calculates.
Fig. 6 shows a communication network that comprises in a circuit according to the invention.This network comprises an encoding device ENC, a transmission channel CHAN and a decoding circuit DEC.At encoding device ENC end, the data vector S1 that 61 pairs of first system's recursive coder will be transmitted encodes, thereby generates first odd even vector P1.Parallel with it, the data of 62 pairs of data vector S 1 of first interleaver are interlocked, and 63 pairs of vectors that obtain after interlocking of second system's recursive coder are encoded, and generate second odd even vector P2.The staggered order that comprises with element in the predefined order modification vector of a vector data, thus the another one vector obtained.Below, in order to simplify description, the staggered vector in other words conj.or perhaps of the data in the vector that will underdraw is staggered.
Subsequently, data vector S1, first odd even vector P1 and second odd even vector P2 are sent to a receiver (not shown in Figure 6) by transmission channel CHAN.This is undertaken by reflector (not shown in Figure 6).Then data vector S11, first odd even vector P1 and second odd even vector P2 are sent to decoding circuit DEC.
Decoding circuit DEC comprises 65, the three interleavers 67 of 66, the second interleavers of 64, the second decoders of first decoder and deinterlacer (de-interleaver) 68.In the example of Fig. 1, decoder 64 and 66 is soft input-soft output decoder device (SISO).
This decoding circuit DEC moves with iterative manner.In iteration, first decoder 64 calculates first external data output vector based on the data vector S1 that is received, first odd even vector P1 that is received and the extrinsic data vector from second decoder 66.If also, just replace it, for example use a unit vector with a predefined vector not from the extrinsic data vector of second decoder 66.This is possible during iteration in the first time of decoding.
By second interleaver 65 first external data output vector is interlocked, the vector that therefrom obtains is sent to second decoder 66.Then, second decoder 66 is based on second odd even vector P2, from vector S 2 of the 3rd interleaver 67 with from the vector of second interleaver 65, calculate second external data output vector, the 3rd interleaver 67 has data vector S1 for its input.68 pairs of second external data output vectors of deinterlacer carry out release of an interleave then, and the vector that therefrom obtains is sent to first decoder 64.Can carry out a new iteration then.
This decoding circuit can be used in the electronic equipment, for example a third generation mobile.
Substitutional element in the staggered demand calculated column of data is as the description of carrying out with reference to figure 7.Carry out the calculating of substitutional element in these row by a system that comprises in a circuit according to the invention, as the description of carrying out with reference to figure 8.
Fig. 7 shows alternate matrix and a computing block interleaved, and this computing is carried out by an interleaver of communication network shown in Figure 6.The example of the following stated is used to meet an interleaver of " 3GGP TS 25.212V3.9.0 (2002-03) " standard.
A purpose of this interleaver is to change the order be included in the data in the data vector that K bit arranged, and K is an integer between 40 to 5114.The predefined interlace scheme of alternate matrix of interleaver capable by R according to one of C row is transformed to an intercrossed data vector with data vector.
Example among Fig. 7 show this alternate matrix be how to define and how the position of a data vector is interlocked.In this example, a data vector B who comprises 25 bits is interlocked, obtain the intercrossed data vector B '.It should be noted that the purpose of this example is that how explanation obtains the intercrossed data vector B in a simple manner '.In particular, this example does not also meet " 3GGP TS 25.212 V3.9.0 (2002-03) " standard, and in this standard, the length K of data vector is between 40 to 5114.
In this example, each of data vector B is all identified by an identifier 0 to 24.Identifier writes in first matrix M 1 line by line.Then,, in matrix M 1, carry out displacement in the row, obtain a matrix M 2 according to replacement scenario in the row.Then,, in matrix M 2, carry out displacement between row, obtain a matrix M 3 according to replacement scenario between row.Matrix M 3 is an alternate matrix.
Then, can obtain the intercrossed data vector B by reading the identifier of this alternate matrix by row ' the identifier of position.In this example, the position by identifier " 0 " sign that first position in data vector B is found, it is in the intercrossed data vector B ' in be positioned at the 24 position.By the position of identifier " 5 " sign, it is in the intercrossed data vector B in data vector B ' in be positioned at the second place, and the like.
For each value of K, all define an interlace scheme.In order to realize this purpose, defined in the row replacement scenario between replacement scenario and row.Above-mentioned standard code replacement scenario between four row, as form 1 definition.For example, replacement scenario replaces first row of matrix M 2 between the row of numeral 1 sign, and this line identifier is " 0 ", and the 20 line identifier of matrix M 2 is " 19 ", corresponding the tenth row of second row, and the like.
| The scheme sequence number | Replacement scenario between row |
| ????1 | [19?9?14?4?0?2?5?7?12?18?10?8?13?17?3?1?16?6?15?11] |
| ????2 | [19?9?14?4?0?2?5?7?12?18?16?13?17?15?3?1?6?11?8?10] |
| ????3 | [9?8?7?6?5?4?3?2?1?0] |
| ????4 | [4?3?2?1?0] |
Table 1: replacement scenario between row
Replacement scenario depends on the length K of data vector between the line number of alternate matrix and row, as shown in Table 2.This form stores is in memory and known length K, and interleaver is determined replacement scenario between the line number R of the alternate matrix that will adopt and row.Therefore, owing to pre-determined these parameters, the data vector of a given length K is interlocked, the line number that interleaver does not need to calculate alternate matrix does not need replacement scenario between row yet.
On the contrary, to replacement scenario between the impossible memory row of each possible columns C.In fact, columns C can get any integer value between 2 to 256.Therefore, the storage capacity that replacement scenario between each possible columns C memory row is needed very large amount.Therefore, when the data vector that a new length K is arranged being interlocked at every turn, replacement scenario in the calculated column.
| ?K | Scheme quantity | ????R |
| ?40≤K≤159 | ????4 | ????5 |
| ?160≤K≤200 | ????3 | ????10 |
| ?201≤K≤480 | ????1 | ????20 |
| ?481≤K≤530 | ????3 | ????10 |
| ?531≤K≤2280 | ????1 | ????20 |
| ?2281≤K≤2480 | ????2 | ????20 |
| ?2481≤K≤3160 | ????1 | ????20 |
| ?3161≤K≤3210 | ????2 | ????20 |
| ?3211≤K≤5114 | ????1 | ????20 |
Table 2: replacement scenario and about the function R of K in the row
For replacement scenario between the row that calculate given length K, determine following parameter.
In first position, determine a prime number p.Numeral p is for making the least prime of (p-1)-K/R 〉=0.
Then, determine line number C.Line number C is the smallest positive integral that makes K≤R*C in set of integers { (p-1), p, (p+1) }.
Then, determine primitive root v (primitive root), it is a function about prime number p, and is as shown in table 3.
| P | ?v | ?p | ?V | ?p | ?v | ?p | ? |
| 7 | ?3 | ?59 | ?2 | ?113 | ?3 | ?191 | ?19 |
| 11 | ?2 | ?61 | ?2 | ?127 | ?3 | ?193 | ?5 |
| 13 | ?2 | ?67 | ?2 | ?131 | ?2 | ?197 | ?2 |
| 17 | ?3 | ?71 | ?7 | ?137 | ?3 | ?199 | ?3 |
| 19 | ?2 | ?73 | ?5 | ?139 | ?2 | ?211 | ?2 |
| 23 | ?5 | ?79 | ?3 | ?149 | ?2 | ?223 | ?3 |
| 29 | ?2 | ?83 | ?2 | ?151 | ?6 | ?227 | ?2 |
| 31 | ?3 | ?89 | ?3 | ?157 | ?5 | ?229 | ?6 |
| 37 | ?2 | ?97 | ?5 | ?163 | ?2 | ?233 | ?3 |
| 41 | ?6 | ?101 | ?2 | ?167 | ?5 | ?239 | ?7 |
| 43 | ?3 | ?103 | ?5 | ?173 | ?2 | ?241 | ?7 |
| 47 | ??5 | ??107 | ??2 | ??179 | ??2 | ??251 | ??6 |
| 53 | ??2 | ??109 | ??6 | ??181 | ??2 | ??257 | ??3 |
Table 2: primitive root v is a function about prime number p
Then, calculate a sequence of least prime
qThis sequence is made up of the value of R, is configured by following:
q[0]＝1
For j＞0, q[j] for satisfying the least prime of following condition:
Q[j] and (p-1) between greatest common divisor be 1
q[j]＞6
q[j]＞q[j-1]
Then, use replacement scenario T:r[T[j between row]]=q[j], calculate least prime constant series
r
Then, calculate basic sequence
sThis sequence comprises p-1 value, is configured by following:
s[0]＝1
S[i]=(v*s[i-1]) mod p, " mod p " refers to carry out mould p multiplication here.
At last, calculate replacement scenario in the row for every row j.For a given row j, corresponding following computation model when C=p, calculates substitutional element U in the C row
j:
U
j[i]＝s[(i*r[j])mod(p-1)]i＝0，1，.......，p-2
U
j[p-1]＝0
Can prove expression formula U
j[i]=s[(i*r[j]) mod (p-1)] equal:
U
j[i+1]=(v ' [j] * U
j[i]) mod p, v ' [j] is one and equals v here
R[j]A new primitive root.In fact:
Expression formula s[i]=(v*s[i-1]) mod p equals following formula:
s[i]＝(v
i*s[0])mod?p＝v
i?mod?p.
Then, expression formula U
j[i]=s[(i*r[j]) mod (p-1)] equal expression formula:
U
j[i]＝v
(I*r[j])mode(p-1)mod?p.
If a=v and i*r[j are arranged]=b:
a
bMod p=[a
N (p-1)] [a
Bmod (p-1)] mod p, n is here:
b＝n(p-1)+bmod(p-1).
So a
bMod p=[a
N (p-1)Mod p] [a
Bmod (p-1)] mod p
＝[(a
(p-1))
nmod?p][a
bmod(p-1)]mod?p
＝[a
(p-1)mod?p]
n[a
bmod(p-1)]mod?p
If p is a prime number, and if the greatest common divisor between a and the p be 1, a then
(p-1)Mod p=1.In this example, a=v and v this means that from being not equal to p the greatest common divisor between a and the p is 1.Therefore
[a
(p-1)mod?p]
n＝1。Thereby, a
bMod p=a
Bmod (p-1)Mod p
If, in this expression formula, replace a with v, use i*r[j] replace b, obtain:
v
i*r[j]mod?p＝v
(i*r[j])mod(p-1)mod?p＝U
j[i]
This expression formula equals expression formula: U
j[i]=(v ' [j])
iMod p, v ' [j]=v here
R[j]
Use this expression formula with a recursive fashion, obtain:
U
j[i+1]＝(v’[j]*U
j[i])mod?p
Fig. 8 shows the system that comprises according to a circuit of the present invention, and this circuit is used for substitutional element between the above-mentioned row of computing.
This system comprises an arithmetic facility 800 and a transmitting device 801.Arithmetic facility comprises 15 register R1-R15, seven mould p shift unit SMP1-SMP7, eight multiplier MUX1-MUX8, seven mould p adder AMP2-AMP8.Transmitting device 801 comprises 12 register R16-R27.System also is included as the adjusting device of the form of a multiplier MUX9.
x＝x(0)x(1)x(2)x(3)x(4)x(5)x(6)x(7)
y＝y(0)y(1)y(2)y(3)y(4)y(5)y(6)y(7)
In level 81, data x is sent to mould p shift unit SMP1.Owing to multiplier MUX1 is arranged,, then will be worth x and copy register R8 to if the value of position y (0) is 1.If the value of position y (0) is 0, will be worth 0 and copy register R8 to.
Mould p shift unit moves to left data x and data and the p that obtains is compared.The data that obtain are:
x(1)x(2)x(3)x(4)x(5)x(6)x(7)0
If these data that obtain greater than p, are then carried out mould p computing to these data that obtain, and the result of computing is write register R1.If these data that obtain less than p, then copy it to register 1.
In level 82, the data that are stored among the register R1 are sent to mould p shift unit SMP2 and multiplier MUX2.Each step all needs a clock cycle that is used for trigger register.If the value of second y (1) is 1, the data that then will be stored among the register R1 send to mould p adder AMP2.If the value of second y (1) is 0, then will be worth 0 and send to mould p adder AMP2.The data that are stored among the register R8 also send to mould p adder AMP2.Mould p adder AMP2 carries out mould p addition and the result is sent to register R9 two input values.
During level 83 to 88, carry out similar operations, obtain the result of the mould p multiplication between x and y at the output of mould p adder AMP8.
Narrate in the back by the circuit among Fig. 8 substitutional element in being listed as is carried out computing.
If the value of the line number R of alternate matrix is 10 or 20, substitutional element is written into 8 bits in then new primitive root v ' [j] and the row, if the value of R is 5, then is written into five bits.
Suppose that substitutional element is written into 8 bits in new primitive root v ' [j] and the row.In this case, the mould p multiplication between the substitutional element needs 8 clock cycle in a new primitive root v ' [j] and row.
In level 81, substitutional element U in will being listed as
0[0] sends to mould p shift unit SMP1 and multiplier MUX1, with substitutional element U in the calculated column
0[1].After first clock cycle, at second clock cycle execution level 82.Second clock cycle, substitutional element U in will being listed as
1[0] sends to mould p shift unit SMP1 and multiplier MUX1, to carry out at v ' [1] and U
1[0] the first mould p multiplication grade between, otherwise, carry out at v ' [0] and U
0The second level of the mould p multiplication [0].
Fig. 8 shows the computing of carrying out the 8th clock cycle.Execution is at v ' [0] and U
0[0] the 8th grade of the mould p multiplication between, wherein multiplier MUX8 confirms whether the value of the 8th v ' [0] (7) of new primitive root v ' [0] is 1.Execution is at v ' [1] and U
1[0] the 7th grade of the mould p multiplication between, wherein multiplier MUX7 confirms whether the value of the 7th v ' [1] (6) of new primitive root v ' [1] is 1, and the like.Execution is at v ' [7] and U
7The first order of the mould p multiplication [0], wherein multiplier MUX1 confirms whether the value of first v ' [7] (0) of new primitive root v ' [7] is 1.
At the end of the 8th clock cycle, substitutional element U in the calculated column
0[1] and with it is stored among the register R15.Suppose that alternate matrix has 20 row.For each row, all to calculate substitutional element in 20 row.So substitutional element U in the calculated column
0[1] to U
19[1], then based on U
0[1] calculates U
0[2], based on U
1[1] calculates U
1[2], and the like.Thereafter, 12 clock cycle after finishing as calculated, arithmetic facility 800 reuses substitutional element in each row that is calculated by it.Transmitting device 801 comprises 12 register R16 to R27, and it is transferred to input with data from the output of arithmetic facility 800 in 12 clock cycle.
Suppose that alternate matrix has 10 row.For each row j, all to calculate substitutional element in ten row.Thereafter, two clock cycle after finishing as calculated, arithmetic facility 800 reuses substitutional element in each row that is calculated by it.Because multiplier MUX9, can select data at the output of register R17, thereby in two clock cycle, these data are transferred to input from the output of arithmetic facility 800.
Verb " comprises " and its variation speech can make an explanation from the broad sense mode, that is to say, be not precluded within and have other element outside the element cited behind the described verb, also comprise numerous elements that related to behind this verb and the element of being modified by word " ".
Claims (7)
1. circuit, this circuit is based on the first data set computing, second data set that is obtained by at least one arithmetic facility (31) computing, this arithmetic facility can be in predefined a plurality of clock cycle data of computing, described arithmetic facility has an input (311) and an output (312), described circuit is characterised in that, it comprises transmitting device (32), be used in a plurality of clock cycle data of first data set are transferred to input from the output of described arithmetic facility, this clock periodicity amount depends on the data bulk and the necessary clock cycle quantity of data of predefined computing of first data set, has data to transmit by described transmitting device in each clock cycle.
2. the described circuit of claim 1 is characterized in that transmitting device comprises adjusting device (35), is used to regulate data are transferred to the necessary amount of cycles of input from the output of described arithmetic facility.
3. claim 1 or 2 described circuit is characterized in that transmitting device comprises at least one clock trigger register (321), and this register can be in new data of each clock cycle storage.
4. the system of substitutional element in the row that are used to calculate an interleaver, this system comprises a described circuit of claim 1.
5. decoding circuit that comprises a described system of claim 4.
6. electronic equipment that comprises a described decoding circuit of claim 5.
7. a communication network comprises at least one reflector that can send signal, a transmission channel, the receiver and the described decoding circuit of claim 5 that can receive described signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0211839 | 2002-09-25 | ||
| FR02/11839 | 2002-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1685620A true CN1685620A (en) | 2005-10-19 |
Family
ID=32039551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA038227371A Pending CN1685620A (en) | 2002-09-25 | 2003-09-10 | Circuit for recursively calculating data |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20060090111A1 (en) |
| EP (1) | EP1547253A1 (en) |
| JP (1) | JP2006500850A (en) |
| CN (1) | CN1685620A (en) |
| AU (1) | AU2003259480A1 (en) |
| WO (1) | WO2004030225A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5510189B2 (en) * | 2010-08-25 | 2014-06-04 | 三菱電機株式会社 | Interleaving apparatus and interleaving method |
| US20140133483A1 (en) * | 2012-11-14 | 2014-05-15 | Broadcom Corporation | Distributed Switch Architecture Using Permutation Switching |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4894626A (en) * | 1988-09-30 | 1990-01-16 | Advanced Micro Devices, Inc. | Variable length shift register |
| US4931974A (en) * | 1989-01-30 | 1990-06-05 | Integrated Device Technology, Inc. | Sixteen-bit programmable pipelined arithmetic logic unit |
| JPH05197741A (en) * | 1991-06-06 | 1993-08-06 | Lsi Logic Corp | Interlieved multiplier accumulator |
| US5784306A (en) * | 1996-06-28 | 1998-07-21 | Cirrus Logic, Inc. | Parallel multiply accumulate array circuit |
| US6112218A (en) * | 1998-03-30 | 2000-08-29 | Texas Instruments Incorporated | Digital filter with efficient quantization circuitry |
| DK1097516T3 (en) * | 1999-05-19 | 2007-01-29 | Samsung Electronics Co Ltd | Turbo-interleaving apparatus and method |
| US6392572B1 (en) * | 2001-05-11 | 2002-05-21 | Qualcomm Incorporated | Buffer architecture for a turbo decoder |
-
2003
- 2003-09-10 AU AU2003259480A patent/AU2003259480A1/en not_active Abandoned
- 2003-09-10 JP JP2004539290A patent/JP2006500850A/en active Pending
- 2003-09-10 WO PCT/IB2003/003943 patent/WO2004030225A1/en not_active Application Discontinuation
- 2003-09-10 US US10/528,622 patent/US20060090111A1/en not_active Abandoned
- 2003-09-10 CN CNA038227371A patent/CN1685620A/en active Pending
- 2003-09-10 EP EP03798270A patent/EP1547253A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP1547253A1 (en) | 2005-06-29 |
| WO2004030225A1 (en) | 2004-04-08 |
| US20060090111A1 (en) | 2006-04-27 |
| AU2003259480A1 (en) | 2004-04-19 |
| JP2006500850A (en) | 2006-01-05 |
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