CN1677865A - Locking-status judging circuit for digital PLL circuit - Google Patents
Locking-status judging circuit for digital PLL circuit Download PDFInfo
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- CN1677865A CN1677865A CN 200410096357 CN200410096357A CN1677865A CN 1677865 A CN1677865 A CN 1677865A CN 200410096357 CN200410096357 CN 200410096357 CN 200410096357 A CN200410096357 A CN 200410096357A CN 1677865 A CN1677865 A CN 1677865A
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Abstract
The object of the invention is to achieve a locked-state determination circuit capable of surely executing determination of a locked state of a digital PLL to which a signal with a longer inversion interval and a signal with a shorter inversion interval are inputted. An input signal of the PLL is inputted by a discrete value sampled by an output signal from a digital control oscillator 25. A voltage comparison means 311 detects whether or not a signal level of the discrete value obtained by the repetition of an oscillation frequency of the digital control oscillator 25 is in the range of the preset threshold. When detected by the voltage comparison means 311 that the detected voltage is out of the range of the threshold, a first positive number is assigned by a selector 312. When detected that it is in the range of the threshold, a second negative number is assigned by the selector 312. The assigned number is added and accumulated with an accumulation means 321. It is determined by a lock determination means 323 whether or not the PLL2 is in the locked state corresponding to the magnitude of the accumulated number.
Description
Technical field
The present invention relates to use with digital PLL (phase-locked loop) circuit, be used to detect whether PLL has carried out the digital PLL of locking to input signal lock detecting circuit.
Background technology
When the playback CD, will be from the signal input digit PLL of optical disc reproducing, regenerated clock signal, regeneration with the optical disk reproducing apparatus of the information signal of this record clock signal just in practicability.Here, if can promptly detect digital PLL with lock detecting circuit is to be in synchronous regime, still depart from synchronous regime, so just can when released state, increase the loop gain of PLL, the response speed that acceleration is used to lock, perhaps when lock-out state, reduce the loop gain of PLL, obtain the clock signal of frequency, can realize suitable optical disk reproducing apparatus for the noise signal stable components of input.
Fig. 7 shows the structure of the digital PLL circuit of conventional example, with reference to accompanying drawing its action is described.
The digital PLL circuit with lock-in detection function shown in this figure is made of phase-comparison circuit 11, loop filter 12, numerically-controlled oscillator 13, phase difference detecting circuit 14 and locking decision circuitry 15.
At first, the input signal with noise contribution and phase error composition is provided for a phase-comparison circuit 11 and phase difference detecting circuit 14 input terminal separately.The vibration output that is caused vibration by numerically-controlled oscillator 13 is provided for phase-comparison circuit 11 and phase difference detecting circuit 14 another input terminal separately.
The phase difference of the signal of phase-comparison circuit 11 detection inputs and the output of numerically-controlled oscillator, output is about the error signal of phase difference.Error signal is input to loop filter 12, utilizes accumulation process to strengthen the low-frequency component of error signal.The error signal that has strengthened low-frequency component is input to numerically-controlled oscillator 13.Numerically-controlled oscillator 13 vibrates according to the frequency of digital signal of input, utilizes this vibration output generation to be used to drive the clock signal etc. of other not shown digital circuits.
Above-mentioned phase difference detecting circuit 14 detects the phase difference of two signals of input.That is, when the digital PLL circuit has carried out locking (synchronously) to input signal, detect less than phase signal, when the digital PLL circuit locks, and the noise composition that comprises in input signal and phase error composition are for a long time, detect phase signal.
Locking decision circuitry 15 compares the size of the absolute value of phase signal with the voltage that is set at benchmark, when greater than reference set value, judge to be in released state.The for example optical disk reproducing apparatus of digital PLL circuit is installed, and the signal according to the lock-out state of judging makes the work of regenerated signal decoding circuit, obtains decoding output.
As an example, following record is arranged in patent documentation 1.Surpass the set point of regulation by means of detecting at the mean value of specified time limit, realize that the release of PLL detects as the phase error of the output of the phase comparator of PLL.
In addition, in the example of patent documentation 2, only when PLL phase place relative error and locking judge that comparative result with reference set value is lower than reference set value above set point number ground continuously, just be judged to be lock-out state.
But, in the release shown in the example of patent documentation 1 detects, even PLL is in the lock state when the playback CD, when having imported the big signal of the short signal equiphase error of the reversal interval that is subject to the influence that transmission characteristic degenerates, with regard to being difficult to distinguish detected signal is that still the release owing to PLL has detected phase error because of the short input signal of reversal interval produces.Also have, when when the PLL servo-actuated, having improved the gain of PLL, can not judge their difference more.
In addition, the situation of the input signal that is obtained by the playback CD just illustrates the detection of the locking and unlocking shown in the example of patent documentation 2.When the playback CD, when the input signal of reversal interval length,,, also carry out the judgement of lock-out state easily so PLL locks easily because of not being subject to the influence that transmission characteristic degenerates.But, when the short input signal of reversal interval, because the influence that degenerated by transmission characteristic,, detect in the majority above the situation of the phase error of fiducial value so phase error increases.How the short signal of reversal interval is contained in the input signal randomly.Therefore, when the short signal of continuous input reversal interval etc.,, also can judge by accident sometimes and be released state although PLL is locked.That is it is disconnected, also often to comprise erroneous judgement in the lock-out state of patent documentation 2 disclosed PLL is judged.
The spy opens the 2002-358739 communique
Patent documentation 2
Specially permit communique No. 3028955
Summary of the invention
So, the present invention is intended to realize be not subject to the long signal of the reversal interval of the influence that transmission characteristic degenerates and be subject to the digital PLL that influences the short signal of reversal interval that transmission characteristic degenerates mixing input at random, also can carry out the lock detecting circuit of judgement of the lock-out state of PLL rightly.
For solving above-mentioned problem, the present invention is by following 1) or 2) device constitute.
That is,
1) a kind of lock detecting circuit of digital PLL, this digital PLL utilizes phase comparator that the oscillation output signal that obtains from numerically-controlled oscillator is carried out bit comparison mutually with the input signal of importing from the outside, change the frequency of oscillation of above-mentioned numerically-controlled oscillator according to the error signal that obtains by this phase bit comparison, obtain above-mentioned oscillation output signal, the lock detecting circuit of above-mentioned digital PLL is connected with digital PLL, whether detection is synchronous with above-mentioned phase of input signals from the phase place of the oscillation output signal that this digital PLL obtains, it is characterized in that possessing:
Phase difference detection device (22) is obtained phase place poor of above-mentioned phase of input signals and above-mentioned oscillation output signal, the absolute value respective phase difference signal of this phase difference that detects and try to achieve;
Weight assignment device (262), when by the detected above-mentioned phase signal of above-mentioned phase difference detection device during less than the reference level of predetermined regulation, think that above-mentioned digital PLL locks, distribute the 1st number, and when above-mentioned phase signal during greater than the reference level of afore mentioned rules, think that above-mentioned digital PLL locks, during each of regulation, distribute different the 2nd several of the polarity of polarity and above-mentioned the 1st number successively; And
Locking judgment means (27), have and to count the portion that adds up (271) that adds up and try to achieve accumulated value from above-mentioned the 1st number of above-mentioned weight assignment device output with the above-mentioned the 2nd, polarity according to the accumulated value that obtains by the above-mentioned portion of adding up, judge that above-mentioned digital PLL is that above-mentioned input signal is locked, and does not still lock it.
2) as above-mentioned 1) lock detecting circuit of described digital PLL, it is characterized in that: above-mentioned the 1st number that is distributed by above-mentioned weight assignment device is that its absolute value is than the above-mentioned the 2nd several little number of absolute value.
The invention effect
According to the lock detecting circuit of digital PLL of the present invention, can obtain following 1) or 2) effect that illustrates.
That is,
1) owing to the phase difference that the vibration of input signal and numerically-controlled oscillator is exported detects, signal level weights assigned number according to phase difference, the number of weighting is added up, detect lock-out state, so can realize to carry out rightly the lock detecting circuit of digital PLL to the judgement of the lock-out state of the input signal of phase noise mixing existence.
2) can be implemented in and set the absolute value of the 1st number than the absolute value of the 2nd number when big, can carry out the lock detecting circuit of PLL of the detection of the lockout failure of lock-out state after for a long time rapidly.
Description of drawings
Fig. 1 is the figure of schematic configuration that the digital PLL with lock-in detection function of the embodiment of the invention is shown.
Fig. 2 is the key diagram of sampling operation again of the input signal of the embodiment of the invention.
Fig. 3 be the embodiment of the invention carrying out the key diagram of waveform of sampling again.
Fig. 4 be the embodiment of the invention carrying out the key diagram of waveform of sampling again.
Fig. 5 is the figure of structure that the lock detecting circuit of the embodiment of the invention is shown.
Fig. 6 is the figure of structure that the locking decision circuitry of the embodiment of the invention is shown.
Fig. 7 is the figure that the schematic configuration with the digital PLL that locks arbitration functions of conventional example is shown.
Embodiment
Below, utilize most preferred embodiment that the execution mode of the lock detecting circuit of digital PLL of the present invention is described.
Figure 1 illustrates the schematic configuration of digital PLL, its operation is described with reference to accompanying drawing with lock detecting circuit.
Digital PLL 2 shown in this figure is made of zero cross detection circuit 22, phase-comparison circuit 23, loop filter 24, numerically-controlled oscillator 25 and the lock detecting circuit 26 of input from the signal of sampling point interpolation circuit 21.
At first, 21 inputs have input signal reversal interval length and the phase error reversal interval weak point to the sampling point interpolation circuit.To being converted to the digital input signals of digital signal by the sampling clock that does not have a synchronized relation with numerically-controlled oscillator,, become the input signal of digital PLL 2 by taking a sample again from the bit clock of numerically-controlled oscillator output by not shown A/D converter.
Here, operate as follows: when input signal does not contain phase error, and be that PLL is when having carried out the perfect condition of phase locking, utilization is from the bit clock of numerically-controlled oscillator output, the signal data of taking a sample again, at the zero passage sampling point that signal polarity changes, its level must be 0.
Carried out the mistake nought state of the input signal of sampling again with zero cross detection circuit 22 detections.Here, the value of the zero passage sampling point that intersects of the waveform that detects input voltage and zero level.Under desirable state, detect level and be 0 zero passage sampling point, but in actual detected, will change the little side of absolute value in the signal of front and back in signal polarity and be considered as the zero passage sampling point and detect.
Phase-comparison circuit 23 compares the zero-crossing timing position of trying to achieve according to detected zero passage sampling value and time location by the bit clock of numerically-controlled oscillator 25 inputs.Poor corresponding to by the time location of relatively trying to achieve, promptly phase difference generates phase error signal.Phase error signal is offered loop filter 24, here, because the loop characteristics of PLL, the control signal of low frequency signal that generated enhancing that low-frequency component added up.
The phase error signal that has carried out Filtering Processing is transfused to numerically-controlled oscillator 25 as control signal.From numerically-controlled oscillator 25, obtain vibration output, and generate bit clock signal according to vibration output and export to vibrate with the signal correspondent frequency of input.Promptly, in numerically-controlled oscillator 25, phase error signal according to input, generate phase control signal, the oscillation phase of numerically-controlled oscillator 25 can change with the phase control signal that generates, and can obtain phase error signal has been carried out accumulating the frequency control signal of (integration), the frequency of oscillation of control figure control generator.
Value by the centrifugal pump data of above-mentioned zero cross detection circuit 22 detected zero passage sample position is transfused to the lock detecting circuit 26 that below will utilize Fig. 5 to be described in detail.Here, data and the specified reference value input with centrifugal pump compares.According to by the result who relatively obtains, obtain when PLL is in the lock state the weighted results of paying different weight coefficients when not being in the lock state.With this weighted results addition, according to the result who is obtained by addition, the detection digital PLL is in the lock state or is in released state.This detection can correctly detect lock-out state and released state, and is taking place from lock-out state to released state, perhaps from released state when lock-out state changes, can promptly detect the transformation of this state.
The structure and the operation thereof of digital PLL have more than been summarized with lock detecting circuit.
Here, when not shown A/D converter supply bit clock carries out the A/D conversion operations, can save sampling point interpolation circuit 21.The design item is how to constitute digital PLL.
Below so the narration digital PLL operation.
In Fig. 2, input signal and the relevant signal relation of sampling operation have again been illustrated, have illustrated.
In the figure, transverse direction is a time shaft, shows the amplitude of signal at longitudinal direction.
At first, the analog signal of input is converted to digital signal by not shown A/D converter.This A/D converter is to carry out work with the sampling frequency of the bit clock different frequency of exporting from numerically-controlled oscillator 25.Show by the discrete data after the A/D converter sampling with white circle.
Taken a sample again by the bit clock of exporting from numerically-controlled oscillator 25 in sampling point interpolation circuit 21 by the digital input signals after the A/D converter sampling.Show the discrete data of taking a sample and obtaining with black circle by again.
In the figure, show by the bit clock that produces by the PLL that is in the lock state take a sample the again waveform that obtains and the position of discrete data.
Like this, obtained in a plurality of centrifugal pump data after the sampling again, be 0 magnitude of voltage crossing zero position.This has utilized: the time location of the bit clock that is generated by oscillatory signal in the numerically-controlled oscillator 25 of the PLL that is in normal lock state is the position of zero passage.
Figure 3 illustrates the situation that the bit clock that is produced by PLL comprises the zero passage sample position.
Here, show the position of the discrete data that is obtained by sampling again with black circle, the little sampling point of absolute value in 2 before and after the variation that the signal data symbol is changed is considered as the zero passage sampling point.
Fig. 4 shows the situation that the bit clock that is produced by PLL does not comprise the zero passage sample position.
In the figure, be 2 intermediate point before and after the variation that changes of the polarity of data with the point shown in the △ symbol, will be considered as zero crossing with the point shown in this △ symbol, obtain phase error information.During with the method for Fig. 3, only can distinguish just after its value is compared that in 2 that data polarity changes which is zero crossing, contrast therewith is during with the method for Fig. 4, as long as it is just passable to obtain 2 median.Therefore, from the simplicity of signal handler, the method for Fig. 4 is simple.But, when using the method for Fig. 4, obtain intermediate point because of utilizing interpolation method, so comprise interpolation error.
The operation of digital PLL more than has been described and has been carried out the waveform of the signal of sampling again by bit clock.
Fig. 5 shows the structure of lock detecting circuit 26, is elaborated with reference to this figure.
Lock detecting circuit 26 shown in this figure is by comparator 261, and selector 262 and the locking decision circuitry of forming with adder 271, limiter 272 and trigger (FF) 273 27 constitute.
At first, to the centrifugal pump of the input terminal A of comparator 261 input, input terminal B is imported voltage as the regulation of reference level with the detected sampling point near zero crossing of above-mentioned zero cross detection circuit shown in Figure 1 22.Compare with 261 pairs of voltages that input to terminal A and B respectively of comparator, when B end big, output signal " 0 ", when the B end hour, output signal " 1 ".
The output signal of comparator 261 is input to selector 262.When signal " 0 " when being transfused to, the signal of+N (N is a positive number) is output as weighted results; When signal " 1 " when being transfused to, the signal of-M (M is a positive number) is output as weighted results.Here, by means of the value of M and the value of N are set at different values, can improve a side's of lock-out state or released state detection sensitivity.
Under normal conditions, keep the situation of lock-out state in the majority, how from selector 262 output+N.When lockout failure takes place when, output-M.Though it is less that the situation of lockout failure takes place during with low frequency output-M,, know that it is important having carried out locking really, will detect this state early when having the suspection of lockout failure for example in order to constitute optical disk reproducing apparatus.
So by means of establishing N＜M, when having the possibility of lockout failure, the accumulated value of weighted results is negative value at short notice.Add up by means of number, can the state that PLL becomes lockout failure be detected weighted results.
That is, locking decision circuitry 27 is carried out this testing.271 pairs of weighted results additions of adder by selector 262 weighted results that obtains and the past that obtains by trigger 273.Addition output is input to limiter 272, and when lock-out state or released state continued for a long time, the value that addition obtains increased.The value that limiter 272 obtains addition is restricted in the scope of regulation.By setting restriction, when preventing the overflowing of circuit, can also to from released state to lock-out state, or carry out servo-actuated from lock-out state early to the variation of released state and detect.
Trigger 273 is the circuit that are used for obtaining with the sequential enforcement that detects zero cross signal the sequential of release output.When to EN terminal feeding enabling signal, the signal of input D terminal is input to the Q terminal.The symbol of the accumulation results of utilization output can judge whether the tendency of lockout failure.
The structure and the operation of lock detecting circuit have more than been narrated.
In addition, making the symbol of the weighted results number that carries out according to the state from comparator 261 outputs is and above-mentioned opposite symbol equally also can carry out lock-in detection work.
In addition, in the superincumbent explanation, the phase error signal that is obtained by the phase bit comparison has used the amplitude at the signal of zero crossing, also can calculate phase mass according to the value of front and back sampling point and use.The phase signal that uses in lock-in detection also is like this.
Be described in the application examples of the locking decision circuitry of using in the lock detecting circuit below.
Fig. 6 shows the structure of locking decision circuitry 27a, describes with reference to this figure.
Locking decision circuitry 27a shown in this figure is made of adder 371, limiter 372,2 triggers 373 and 374, selector 375, AND circuit 376, counter 377 and comparators 378.
Locking decision circuitry 27a sets the accumulative frequency of weighted results for setting to counter 377 in advance, when reaching the accumulative frequency of setting, estimates accumulated value, carries out the judgement of lock-in detection.In addition, by means of when reaching cumulative frequency,, can not be subject to past state influence ground and carry out the lock-in detection judgement early the accumulated value zero clearing.
Owing to utilize this locking decision circuitry 27a can be with the mean value of the weighted results of the set point number of counter as end value, thus can not be subject to the noise contribution imported influence and be that lock-out state is judged by unit with the set point number.According to the rapid detected locking judged result of locking decision circuitry 27a energy, for example can when released state, increase the loop gain of PLL, the response speed that acceleration is used to lock, perhaps when lock-out state, reduce the loop gain of PLL, obtain clock signal the noise signal composition frequency stabilization of input.In addition, owing to can carry out the demodulation work of not shown tracer signal and the processing of the information signal that obtains by demodulation etc., so the signal of this signal as the regeneration control of carrying out CD can be carried out the design of optical disk reproducing apparatus rightly.
The possibility of utilizing on the industry
Even in the signal of the signal of input being separated the timing input, contain more noise, phase The occasion of bit error can utilize digital PLL that this input signal is carried out demodulation, can be used for Judge whether normal to generate the clock signal of the decoding circuit work that makes input signal, according to judgement The result carries out judging for the locking of the digital PLL of control decoding circuit work.
Claims (2)
1. the lock detecting circuit of a digital PLL, this digital PLL utilizes phase comparator that the oscillation output signal that obtains from numerically-controlled oscillator is carried out bit comparison mutually with the input signal of importing from the outside, change the frequency of oscillation of above-mentioned numerically-controlled oscillator according to the error signal that obtains by this phase bit comparison, obtain above-mentioned oscillation output signal, the lock detecting circuit of above-mentioned digital PLL is connected with digital PLL, whether detection is synchronous with above-mentioned phase of input signals from the phase place of the oscillation output signal that this digital PLL obtains, it is characterized in that possessing:
Phase difference detection device is obtained phase place poor of above-mentioned phase of input signals and above-mentioned oscillation output signal, the absolute value respective phase difference signal of this phase difference that detects and try to achieve;
The weight assignment device, when by the detected above-mentioned phase signal of above-mentioned phase difference detection device during less than the reference level of predetermined regulation, think that above-mentioned digital PLL locks, distribute the 1st number, and when above-mentioned phase signal during greater than the reference level of afore mentioned rules, think that above-mentioned digital PLL locks, during each of regulation, distribute different the 2nd several of the polarity of polarity and above-mentioned the 1st number successively; And
The locking judgment means, having to add up with above-mentioned the 2nd number from above-mentioned the 1st number of above-mentioned weight assignment device output tries to achieve the portion that adds up of accumulated value, polarity according to the accumulated value that obtains by the above-mentioned portion of adding up, judge that above-mentioned digital PLL is that above-mentioned input signal is locked, and does not still lock it.
2. the lock detecting circuit of digital PLL as claimed in claim 1 is characterized in that,
Above-mentioned the 1st number that is distributed by above-mentioned weight assignment device is the absolute value little number of its absolute value than above-mentioned the 2nd number.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP102834/2004 | 2004-03-31 | ||
| JP2004102834 | 2004-03-31 |
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| Publication Number | Publication Date |
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| CN1677865A true CN1677865A (en) | 2005-10-05 |
| CN100346576C CN100346576C (en) | 2007-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100963570A Expired - Fee Related CN100346576C (en) | 2004-03-31 | 2004-11-26 | Locking-status judging circuit for digital PLL circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142836A (en) * | 2010-01-28 | 2011-08-03 | 日本电波工业株式会社 | PLL oscillator circuit |
| CN102193029A (en) * | 2010-03-19 | 2011-09-21 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN101867369B (en) * | 2009-04-17 | 2012-06-06 | 南亚科技股份有限公司 | Phase detection module and phase detection method |
| CN101621297B (en) * | 2009-08-03 | 2012-12-05 | 四川和芯微电子股份有限公司 | Detection method and circuit of frequency lock of phase lock loop |
| CN104914309A (en) * | 2015-05-22 | 2015-09-16 | 中国科学院等离子体物理研究所 | Phase difference measurement system based on HMC439QS16G chip |
| CN108521278A (en) * | 2018-04-11 | 2018-09-11 | 中国科学技术大学 | A kind of phase lock loop locks detection circuit based on time voltage converter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930008433B1 (en) * | 1991-05-15 | 1993-08-31 | 금성일렉트론 주식회사 | Duel pll's lock detect system |
| JP3695833B2 (en) * | 1996-04-05 | 2005-09-14 | 株式会社ルネサステクノロジ | PLL circuit |
-
2004
- 2004-11-26 CN CNB2004100963570A patent/CN100346576C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101867369B (en) * | 2009-04-17 | 2012-06-06 | 南亚科技股份有限公司 | Phase detection module and phase detection method |
| CN101621297B (en) * | 2009-08-03 | 2012-12-05 | 四川和芯微电子股份有限公司 | Detection method and circuit of frequency lock of phase lock loop |
| CN102142836A (en) * | 2010-01-28 | 2011-08-03 | 日本电波工业株式会社 | PLL oscillator circuit |
| CN102142836B (en) * | 2010-01-28 | 2013-06-19 | 日本电波工业株式会社 | PLL oscillator circuit |
| CN102193029A (en) * | 2010-03-19 | 2011-09-21 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN102193029B (en) * | 2010-03-19 | 2013-05-01 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN104914309A (en) * | 2015-05-22 | 2015-09-16 | 中国科学院等离子体物理研究所 | Phase difference measurement system based on HMC439QS16G chip |
| CN108521278A (en) * | 2018-04-11 | 2018-09-11 | 中国科学技术大学 | A kind of phase lock loop locks detection circuit based on time voltage converter |
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