CN1668021A - A FIFO memory with high reliability and implementing method thereof - Google Patents
A FIFO memory with high reliability and implementing method thereof Download PDFInfo
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Abstract
This invention discloses a FIFO memory including a memory, a read address counter, a write address counter and a full-space mark generation logic. Said two counters receive control signals belonging to them via the control signal bus separately and input the output signals to said memory, at the same time, said two counters input their own output signals to said mark generation logic. A realization method for a reliable FIFO memory is disclosed, the current state of said memory space in the FIFO memory is judged by comparing the counting values of the two counters in the mark generation logic and their own output marks are refreshed.
Description
Technical field
The present invention relates to pushup storage (FIFO), be meant a kind of high reliability pushup storage and its implementation especially with automatic correction function.
Background technology
The basic structure of pushup storage comprises referring to shown in Figure 1: memory 101, read address counter 102, write address counter 103, data cell counter 104 and empty full scale will produce logical one 05.The memory 101 general random asccess memory (RAM) that adopt among the FIFO, as: dual-ported memory (DPRAM), one-port memory (SPRAM) etc.Read address counter 102, write address counter 103 and data cell counter 104 are independently counted by the control signal that reception is sent from one group of control signal bus 106 respectively, the control signal that counter received can be provided by cell level FIFO self, also can be from the control device of outside.Count value after write address counter 103 and read address counter 102 will upgrade is sent to memory 101, and memory 101 is according to the count value of receiving, adjusts to read address and write address pointer in self.In addition, data cell counter 104 is sent to sky full scale will with its count value and produces logical one 05, empty full scale will produces the data cell count value that logical one 05 receives by judgement, produces corresponding empty sign or full scale will, limits the read-write operation to memory 101.Wherein, data cell described here is meant read and write data base unit in the process of FIFO.
FIFO relatively more commonly used at present has cell level FIFO and Frame level FIFO etc.Cell level FIFO generally carries out reading and writing data with the ATM(Asynchronous Transfer Mode) cell as base unit, also is that the data cell among the cell level FIFO is an ATM cell.Wherein, ATM cell is a kind of Frame of regular length, is the base unit of transmission data in the atm network, in atm device, generally all is to adopt cell level FIFO storage ATM cell.The memory of cell level FIFO logically is divided into the memory block of several same size usually, and each memory block is used to deposit an ATM cell.
Cell level FIFO reads address and write address separated into two parts respectively logically: high address and low order address.Certain memory block of memory inside is pointed in the high address, i.e. the high address corresponding ATM cell of address value, and low order address points to a concrete memory cell in the memory block.In receiving an ATM cell process, high-order write address remains unchanged, and has only the low level write address to change; After finishing ATM cell of reception, high-order write address changes, and the low level write address is changed to a fixing initial value, and the initial address of writing next cell with assurance is identical; Equally, in sending an ATM cell process, a high position is read the address and is remained unchanged, and has only low level to read address change; After finishing ATM cell of transmission, a high position is read address modification, and low level is read the address and is changed to a fixing initial value, and the initial address of reading next cell with assurance is identical.Thereby the read address counter of cell level FIFO includes high-order read address counter and low level read address counter two parts usually, and the write address counter of cell level FIFO includes high-order write address counter and low level write address counter two parts too.
The count value of data cell counter is the cell level in cell level FIFO, therefore is called the cell count device.When receiving or sending a cell, the cell count device among the cell level FIFO upgrades count value, the cell number that the maximum count value of cell count device can be stored corresponding to memory among this FIFO according to the control signal that receives.
The control signal of sending from the control bus of cell level FIFO generally comprises: read commencing signal, write commencing signal and be used to control the read-write enable signal of low order address rolling counters forward, or read end signal, write end signal and be used to control the read-write enable signal of low order address rolling counters forward.Two groups of control signals here can be selected arbitrarily by the FIFO designer, depend on that when design plan zero hour with read-write operation as the counting starting point, still with the finish time as the counting starting point.Be example as the counting starting point zero hour with read-write operation, read address counter among the cell level FIFO receives only to be read commencing signal and reads enable signal, according to reading the count value that commencing signal upgrades high-order read address counter, according to reading the count value that enable signal upgrades the low level read address counter; Write address counter receives only to be write commencing signal and writes enable signal, according to writing the count value that commencing signal upgrades high-order write address counter, according to writing the count value that enable signal upgrades the low level write address counter; The cell count device receives only reads commencing signal and write commencing signal, reads commencing signal then source count value is subtracted 1 if receive one, writes commencing signal then source count value is added 1 if receive one.
The empty full scale will of cell level FIFO produces logic and comprises two outputs: empty mark output end and full scale will output.Empty mark output end is sent to outside read through model to cell level FIFO sense data with empty marking signal; Full scale will output is sent to the outside writing module that cell level FIFO is carried out write operation with full scale will signal.The output of empty full scale will is represented the effective or invalid of empty full scale will by output high level or low level.Such as: represent effectively that when being output as high level low level represents when invalid that if FIFO is for full, then full scale will output is changed to high level, otherwise is low level; If FIFO is empty, then empty mark output end is changed to high level, otherwise is changed to low level.Empty full scale will produces logic output terminal and places high level to represent that effectively still low level is represented effectively, can be determined by designer oneself.Empty full scale will produces the current source count value of logic by the output of cell count device, judge the full state of the current sky of memory, and corresponding empty sign of generation or full scale will, sky or full scale will can produce back-pressure to the interface that reads or writes of FIFO, and stop outside memory to FIFO to read or write data.The sky sign and the full scale will of general cell level FIFO output are the cell levels.
Similarly also has Frame level FIFO with cell level FIFO, their common feature all is that memory is divided into several memory blocks, each memory block can only be deposited a data unit, the memory block of memory inside is pointed in the high address of counter, and low order address points to a concrete memory cell in the memory block.Difference is that the base unit of Frame level FIFO read-write operation is a Frame, can deposit a Frame in each memory block of its internal storage, a high position reads or writes corresponding Frame of an address value of address, and adopts the number of store frames of data among the data frame counter record data frame level FIFO.
Because read address counter, write address counter and data cell counter among the prior art FIFO all are to receive different control signals by the control signal bus, independently count, not related between the control signal separately.Therefore there is defective in FIFO in actual use meeting on reliability, promptly when the count value of reading address, write address or data cell counter that abnormal conditions cause FIFO inside occurring and make mistakes, FIFO can't accomplish automatic error correction, recovers normal automatically, causes reading and writing data to occur in sequence mistake.
Give an example: suppose that the cell number that certain cell level FIFO maximum can be stored is 4, before being subjected to unusual the interference high-order write address, a high position reads the address and source count value all is 0, being subjected to disturbing rear high-lying to read address generation saltus step unusually is 1, high-order write address and source count value remain unchanged, suppose to disturb after the disappearance, after writing 2 cells earlier, read 2 cells again as an access cycle, FIFO carries out 5 such read and write accesss to this cell level, the read-write situation of cell in memory, ginseng is shown in Table 1:
| Write cell | The cell of storing among the FIFO | Read cell | ||||||
| Initial condition | ??X | ??X | ??X | ??X | ||||
| The 1st visit | ??C0 | ??C1 | ??C0 | ??C1 | ??X | ??X | ??C1 | ??X |
| The 2nd visit | ??C2 | ??C3 | ??C0 | ??C1 | ??C2 | ??C3 | ??C3 | ??C0 |
| The 3rd visit | ??C4 | ??C5 | ??C4 | ??C5 | ??C2 | ??C3 | ??C5 | ??C2 |
| The 4th visit | ??C6 | ??C7 | ??C4 | ??C5 | ??C6 | ??C7 | ??C7 | ??C4 |
| The 5th visit | ??C8 | ??C9 | ??C8 | ??C9 | ??C6 | ??C7 | ??C9 | ??C6 |
Table 1
As can be seen from Table 1, in the read and write access process, the order that writes cell is: C0, C1, C2, C3, C4, C5, C6, C7, C8, C9; The order of reading cell then becomes: C1, X, C3, C0, C5, C2, C7, C4, C9, C6, and wherein, Cn represents the value of cell n, X represents the cell of no initializtion in the memory.As can be seen, because the high position that a disturbance causes is read address change, cause exporting the mistake that occurred in sequence of cell.Though disturb very fast disappearance, and the later work of this cell level FIFO all is in normal condition, and still, the read-write mistake of himself but can't obtain correcting, if and read and write access proceeds down, it is wrong that the order of reading cell from this cell level FIFO will remain.Equally, if what unusual saltus step took place is high-order write address value or source count value, cell level FIFO can not correct it automatically, and also can cause read-write mistake, may cause also for the mistake of cell count device count value that sky full scale will produces and make a mistake when logic produces empty full scale will this cell level FIFO.
From top example as can be seen, in case makeing mistakes, can't correct automatically or recover by the counter among the prior art FIFO, cause the data input/output sequence of FIFO to make a mistake, and the miscount of data cell counter also can cause empty full scale will and produce sky or the full scale will that logic produces mistake, the read-write mistake of FIFO is worsened more, if want to recover then must counters all among the FIFO be resetted, make all rolling counters forward values reset to initial condition, this will bring very burden to use.Particularly because when each counter of FIFO or empty full scale will produce the situation that logic makes mistakes, very difficult quilt in time finds, thereby causes the serious consequence of long-time reading and writing data mistake, makes the reliability of FIFO be difficult to be guaranteed.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of pushup storage of high reliability, can not need at work to reset again, just can correct the mistake that counter and empty full scale will produce logic automatically, guarantee the normal read-write order of FIFO, improve the reliability of FIFO.
Another main purpose of the present invention is to provide a kind of pushup storage implementation method of high reliability, make FIFO have automatic error correction function, even after rolling counters forward value or empty full scale will produce logic and exception error occurs, also can recover normal at work automatically, assurance is correct to the read-write order of FIFO, continue work reliably, thereby improve the reliability of FIFO.
According to the pushup storage of first goal of the invention a kind of high reliability provided by the invention, include memory, read address counter, write address counter and empty full scale will and produce logic;
Described read address counter and write address counter also input to described empty full scale will generation logic with output signal separately respectively; Described empty full scale will produces the output signal that logic receives read address counter and write address counter, and exports corresponding empty full scale will according to this signal.
The described read address counter of this pushup storage comprises high-order read address counter and low level read address counter, and described write address counter comprises high-order write address counter and low level write address counter; Described read address counter and write address counter are imported output signal that empty full scale will produces logic and are respectively a high position and read address value and high-order write address value.
The described pushup storage of this pushup storage is cell level pushup storage or Frame level pushup storage.
The storable data cell number of the described memory of this pushup storage lacks at least one than the memory actual capacity.
The described pushup storage of this pushup storage further includes the data cell counter, and described data cell counter receives the control signal that belongs to self by the control signal bus.
It is application-specific IC that the described empty full scale will of this pushup storage produces logic.
The invention provides a kind of pushup storage implementation method of high reliability according to another goal of the invention, described pushup storage includes memory, read address counter, write address counter and empty full scale will and produces logic, the read address counter of this pushup storage and write address counter respectively will be separately output signal input to sky full scale will and produce logic, empty full scale will produces logic and stops read or write to memory by output sky or full scale will; And may further comprise the steps:
A) control signal that will belong to read address counter and write address counter inputs to read address counter and write address counter respectively, and read address counter and write address counter upgrade the count value of self respectively according to the control signal of receiving;
B) current count value after read address counter and the write address counter renewal is inputed to sky full scale will respectively and produce logic;
C) produce the count value of passing through more current read address counter and write address counter in the logic in empty full scale will, judge the current full state of sky of memory in the pushup storage, upgrade empty full scale will and produce the empty full scale will that logic is exported.
The described step c) of this method specifically comprises:
C11) judge whether current read address counter count value is identical with the write address counter count value, if then enter step c12); Otherwise, judge not only non-NULL but also non-full of described memory current state, upgrade that self to be output as sky full scale will all invalid;
What c12) judge that this carries out described pushup storage is read operation or write operation, if read operation, the state of then judging current described memory upgrades being output as empty sign effectively for empty; If write operation, the state of then judging current described memory is for full, and it is effective that renewal is output as full scale will.
But the storage data units number that this method sets in advance memory in the described pushup storage lacks n than the memory actual capacity, and n is less than the memory actual capacity, but more than or equal to 1 integer, then described step c) specifically comprises:
C21) judge whether current read address counter count value is identical with the write address counter count value, if the state of then judging current described memory is for empty, output is empty to be indicated, otherwise, enter step c22);
C22) judge that whether current write address counter count value adds behind the n more than or equal to current read address counter count value, if, the state of then judging current described memory is for full, output full scale will, otherwise, judge the current not only non-NULL but also non-full of described memory, upgrade that self to be output as sky full scale will all invalid.
The described read address counter of this method comprises high-order read address counter and low level read address counter, and described write address counter comprises high-order write address counter and low level write address counter; Described write address counter count value is high-order write address value, and described read address counter count value is that a high position is read address value.
The described pushup storage of this method is cell level pushup storage or Frame level pushup storage.
From such scheme as can be seen, the pushup storage of high reliability disclosed by the invention and its implementation, produce in the output of write address counter and read address counter and empty full scale will between the input of logic and set up contact, utilize FIFO write address counter count value, internal logic between the full state of the sky of read address counter count value and memory is got in touch, produce empty full scale will by the count value that compares write address counter and read address counter, even making the rolling counters forward value of FIFO makes mistakes, also can recover normal rapidly automatically, avoid writing and read and occurring in sequence mistake of data, thereby efficiently solve prior art FIFO rolling counters forward value and read and write the problem that to recover automatically under the wrong situation that occurs in sequence, improved reliability and the fault-tolerant ability of FIFO greatly, and the present invention program possesses skills flexibly, realize simple, characteristics such as be widely used.
Description of drawings
Fig. 1 is the structural representation of prior art FIFO;
Fig. 2 is the structural representation of FIFO in the preferred embodiment of the present invention;
Fig. 3 is the workflow schematic diagram of first preferred embodiment of the present invention FIFO;
Fig. 4 is the workflow schematic diagram of second preferred embodiment FIFO of the present invention.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Cause the counter of cell level or Frame level FIFO can't carry out automatic error correction and the automatic basic reason of recovering in the prior art scheme, it all is independently to count according to the control signal of FIFO that a high position that is FIFO is read address, high-order write address and data cell count value, and empty full scale will to produce logic be that current count value by the judgment data location counter produces empty full scale will.Because not contact between the count value of each counter, cause the count value of certain counter to be made mistakes in case abnormal conditions occur like this, then cause easily the reading and writing data of FIFO is made mistakes in proper order, after particularly the count value of data cell counter is made mistakes, cause empty full scale will and produce the empty full scale will that logic produces mistake, the data write mistake is worsened more, and FIFO itself can't realize automatic recovery.
In the prior art, it is count value according to the data cell counter empty full scale will that decides its generation that empty full scale will produces logic.Usually, if the count value of data cell counter is 0, judge that then FIFO is empty, empty full scale will produces logic and produces empty sign, if the count value of data cell counter equals its maximum count value, judges that then FIFO is full, produces full scale will.
And in fact because empty full scale will produces that the high position of logical AND cell level or Frame level FIFO reads between address value and the high-order write address value is to have certain logical relation, empty full scale will produces logic can judge the full state of sky of memory among the current FIFO by the value that the high position that relatively counter write down is read address and high-order write address, and produces empty full scale will.Such as: when the high position of cell level or Frame level FIFO is read address value and equated with high-order write address value,, can judge that then the current state of this FIFO is for empty if be read operation to this operation that FIFO carried out; If to this operation that FIFO carried out is write operation, can judge that then the current state of this FIFO is for full.Like this owing to read to have introduced logical communication link between address value, high-order write address value and the empty full scale will, when the rolling counters forward value that can be implemented in FIFO is made mistakes, also can make FIFO recover its input cell order and output cell order automatically in the high position of FIFO.
Be example with cell level FIFO below, the structure of the pushup storage of high reliability of the present invention and the preferable embodiment of implementation method are elaborated.
The structure of the high reliability cell level FIFO of present embodiment referring to shown in Figure 2, comprising: memory 101, read address counter 102, write address counter 103 and empty full scale will produce logical one 05.Wherein, include high-order read address counter 102a, low level read address counter 102b two parts in read address counter 102 and the write address counter 103, and high-order write address counter 103a and low level write address counter 103b two parts, the read and write counter basis low level enable signal separate counts separately of low level.Empty full scale will produces logical one 05 can adopt application-specific IC (Asic).
The read address counter 102 among this cell level FIFO and the input of write address counter 103 all are connected with the control signal bus, unlike the prior art be that their high-order read address counter 102a and high-order write address counter 103a output signal also inputs to sky full scale will and produce logical one 05.Judge that the full state of sky of FIFO is inoperative because the cell count device of cell level FIFO produces logical one 05 to empty full scale will, therefore in the cell level FIFO of present embodiment, need not to be provided with cell level counter.
The read address counter of this FIFO and write address counter basis control signal separate counts separately, the high position of these two counter records of logical foundation is read address value and high-order write address value is judged the full state of the current sky of FIFO and empty full scale will produces, if a current high position is read address value and high-order write address value equates, and this operation to FIFO is read operation, then judge the current state of FIFO for empty, it is that empty standard is effective that sky full scale will generation logic is set; Equate if a current high position is read address value and high-order write address value, and this operation to FIFO is write operation, then judges the current state of FIFO for full, sky full scale will is set, and to produce logic be that full scale will is effective.
The workflow of this cell level FIFO is referring to shown in Figure 3:
High position after step 302, read address counter and write address counter will be upgraded respectively reads address value and high-order write address value is sent to sky full scale will generation logic.
Wherein because overhead sign of logic and full scale will can only individualisms, therefore, empty full scale will generation logic a mark output end is changed to effectively the other end can be changed to simultaneously invalid.
Even owing to the reason generation cell that read address counter, write address counter or empty full scale will produce logic is read and write mistake, also can realize automatic error correction and recovery automatically by such scheme cell level FIFO.
Still the example with table 1 illustrates, supposes that the memory maximum of cell level FIFO can be stored 4 cells.
When this cell level FIFO worked, supposing to be subjected to a preceding high-order write address of unusual interference and a high position to read the address all was 0, and it is that empty sign is effective that the empty full scale will of cell level FIFO produces logic.Being subjected to disturbing rear high-lying to read the address saltus step unusually is 1, and empty full scale will produces the high-order write address of logic by judging cell level FIFO and a high position, and to read the address different, thus the sky sign is put invalid.If be write operation next time, then after writing a cell, high-order write address also becomes 1, empty full scale will produces the high-order write address of logic determines and a high position, and to read the address identical, judge that again this is operating as write operation, thereby think that the state of cell level FIFO memory is full, full scale will is equipped with effect, thereby the interface of writing to cell level FIFO produces back-pressure, stop external data to write cell level FIFO, can only carry out read operation to cell level FIFO so next time, write operation can't be continued, thereby adjust read-write order, make it recover normal again this cell level FIFO.
As described above, according to writing the cycle order of reading 2 cells again behind 2 cells, then this cell level FIFO is carried out the result after such read and write access 5 times, ginseng is shown in Table 2:
| Write cell | The cell of storing among the cell level FIFO | Read cell | ||||||
| ??00 | ??01 | ??10 | ??11 | |||||
| Initial condition | ??X | ??X | ??X | ??X | ||||
| The 1st visit | ??C0 | ??C0 | ??X | ??X | ??X | ??C0 | ??X | |
| The 2nd visit | ??C1 | ??C2 | ??C0 | ??X | ??C1 | ??C2 | ??C1 | ??C2 |
| The 3rd visit | ??C3 | ??C4 | ??C3 | ??C4 | ??C1 | ??C2 | ??C3 | ??C4 |
| The 4th visit | ??C5 | ??C6 | ??C3 | ??C4 | ??C5 | ??C6 | ??C5 | ??C6 |
| The 5th visit | ??C7 | ??C8 | ??C7 | ??C8 | ??C5 | ??C6 | ??C7 | ??C8 |
Table 2
In the table 2, Cn represents the value of cell n, and X represents the cell of no initializtion in the memory.As can be seen from Table 2, because after writing the cell C0 of 00 position, empty full scale will produces logic and produces full scale will, and write operation has been stopped once, thereby make the order that writes cell be: C0, C1, C2, C3, C4, C5, C6, C7, C8 The order of reading cell still is: C0, C1, C2, C3, C4, C5, C6, C7, C8 ...As seen, the order of reading cell of memory is not compared with the order that writes cell and is changed among the cell level FIFO.
Owing to occur in the present embodiment high-order when reading situation that address value and high-order write address value equate at cell level FIFO, also need sky full scale will to produce logic by judging that this operation is the full state of sky that read operation or write operation are determined current storage, therefore comparatively complicated, in order to simplify this determining step that empty full scale will produces logic, can also take following described more simple proposal to realize.
The useful number that sets in advance memory block among the cell level FIFO in the present embodiment is lacked one or more than actual, such as: suppose few piece number be n, the memory block actual number is m among the cell level FIFO, 1≤n＜m, wherein n and m are integer, and then the storage availability piece number of memory is m-n.The sky sign of this cell level FIFO and full scale will produce according to following logical relation: read the address if high-order write address equals a high position, then empty sign is effective, otherwise empty sign is invalid; If high-order write address adds and equals a high position behind the n and read the address, then full scale will is effective, otherwise full scale will is invalid.In addition, if high-order write address read the situation of address greater than a high position after adding n, present embodiment is put too and completely is masked as effectively, after high-order write address adds n, read the address less than a high position after, need not to carry out special operational, FIFO can recover normal automatically.The preferable embodiment of the present invention is normally got n=1.
The workflow of this cell level FIFO is referring to shown in Figure 4:
High position after step 402, read address counter and write address counter will be upgraded respectively reads address value and high-order write address value is sent to sky full scale will generation logic.
Can reach the automatic error correction of cell level FIFO so, equally and recover source count value and the effect of cell read-write order.
Give an example, suppose a cell level FIFO memory m=8, n=3, it is 5 that a current high position is read the address, then when high-order write address was 5, it is identical with high-order write address that an empty full scale will generation logic determines high position is read the address, thinks that the memory of cell level FIFO is sky, put empty sign effectively, stop outside from cell level FIFO read data; When high-order write address is 2, empty full scale will produces after the value 3 that the current high-order write address value 2 of logic determines adds n must 5, think that cell level FIFO is for full, it is effective to put full scale will, stop writing of external data, write operation can't be continued, thereby adjust read-write order, make it recover normal again this cell level FIFO.Be not difficult to find out that this scheme still can realize technique effect of the present invention.
If abnormal conditions make height read address value and high write address value differs less than n, for example: high-order write address saltus step is 3, then current high-order write address value 3 adds after the value 3 of n must 6, greater than current high-order write address value 5, though at this moment high-order write address value and the high-order relation of reading between the address value do not meet logic, but empty full scale will produces when logic still can expire by memory and handles, put and completely be masked as effectively, and the outside writing data into memory of prevention, up to carrying out twice above read operation, after making memory state be judged to be non-expiring, just allow write operation.Be not difficult to find out that by such adjustment outside read-write order to FIFO can recover normal very soon.
In addition, if desired, also the data cell counter can be set among the FIFO of the present invention, difference with the prior art is that sky full scale will produces logic just according to the count value work of read address counter and write address counter, and the count value of data cell counter does not exert an influence to the generation of empty full scale will.
Described all schemes also can be equally applicable to have between the generation of the count value of read address counters such as Frame level FIFO, write address counter and empty full scale will the pushup storage of logical relation above the present invention.In addition, for being the FIFO that base unit carries out read-write operation with the byte, each count value of its data cell counter is represented a byte, the differentiation of not making high address and low order address at read address counter and the write address counter of such FIFO, each address bit is only represented a byte, and two kinds of address value and write address values are also only read in the output of read address counter and write address counter.The present invention program can be equally applicable to this class FIFO, and just the comparison of accordingly a high position being read between address value and the high-order write address value changes the comparison of reading between address value and the write address value into.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind of pushup storage of high reliability includes memory, read address counter, write address counter and empty full scale will and produces logic;
It is characterized in that: described read address counter and write address counter also input to described empty full scale will generation logic with output signal separately respectively; Described empty full scale will produces the output signal that logic receives read address counter and write address counter, and exports corresponding empty full scale will according to this signal.
According to the described pushup storage of claim 1, it is characterized in that 2, described read address counter comprises high-order read address counter and low level read address counter, described write address counter comprises high-order write address counter and low level write address counter;
Described read address counter and write address counter are imported output signal that empty full scale will produces logic and are respectively a high position and read address value and high-order write address value.
According to the described pushup storage of claim 2, it is characterized in that 3, described pushup storage is cell level pushup storage or Frame level pushup storage.
According to the described pushup storage of claim 1, it is characterized in that 4, the storable data cell number of described memory lacks at least one than the memory actual capacity.
According to the described pushup storage of claim 1, it is characterized in that 5, described pushup storage further includes the data cell counter, described data cell counter receives the control signal that belongs to self by the control signal bus.
According to the described pushup storage of claim 1, it is characterized in that 6, it is application-specific IC that described empty full scale will produces logic.
7, a kind of pushup storage implementation method of high reliability, it is characterized in that, described pushup storage includes memory, read address counter, write address counter and empty full scale will and produces logic, the read address counter of this pushup storage and write address counter respectively will be separately output signal input to sky full scale will and produce logic, empty full scale will produces logic and stops read or write to memory by output sky or full scale will; And may further comprise the steps:
A) control signal that will belong to read address counter and write address counter inputs to read address counter and write address counter respectively, and read address counter and write address counter upgrade the count value of self respectively according to the control signal of receiving;
B) current count value after read address counter and the write address counter renewal is inputed to sky full scale will respectively and produce logic;
C) produce the count value of passing through more current read address counter and write address counter in the logic in empty full scale will, judge the current full state of sky of memory in the pushup storage, upgrade empty full scale will and produce the empty full scale will that logic is exported.
According to the described method of claim 7, it is characterized in that 8, described step c) specifically comprises:
C11) judge whether current read address counter count value is identical with the write address counter count value, if then enter step c12); Otherwise, judge not only non-NULL but also non-full of described memory current state, upgrade that self to be output as sky full scale will all invalid;
What c12) judge that this carries out described pushup storage is read operation or write operation, if read operation, the state of then judging current described memory upgrades being output as empty sign effectively for empty; If write operation, the state of then judging current described memory is for full, and it is effective that renewal is output as full scale will.
9, according to the described method of claim 7, it is characterized in that, but the storage data units number that sets in advance memory in the described pushup storage lacks n than the memory actual capacity, n is less than the memory actual capacity, but the integer more than or equal to 1, then described step c) specifically comprises:
C21) judge whether current read address counter count value is identical with the write address counter count value, if the state of then judging current described memory is for empty, output is empty to be indicated, otherwise, enter step c22);
C22) judge that whether current write address counter count value adds behind the n more than or equal to current read address counter count value, if, the state of then judging current described memory is for full, output full scale will, otherwise, judge the current not only non-NULL but also non-full of described memory, upgrade that self to be output as sky full scale will all invalid.
According to claim 7,8 or 9 described methods, it is characterized in that 10, described read address counter comprises high-order read address counter and low level read address counter, described write address counter comprises high-order write address counter and low level write address counter;
Described write address counter count value is high-order write address value, and described read address counter count value is that a high position is read address value.
According to the described method of claim 10, it is characterized in that 11, described pushup storage is cell level pushup storage or Frame level pushup storage.
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Cited By (8)
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| CN100346289C (en) * | 2006-04-12 | 2007-10-31 | 华为技术有限公司 | FIFO memory and method for output empty full marker thereof |
| CN101281489B (en) * | 2007-04-03 | 2010-05-26 | 中兴通讯股份有限公司 | FIFO memory implementing method and apparatus |
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| CN100346289C (en) * | 2006-04-12 | 2007-10-31 | 华为技术有限公司 | FIFO memory and method for output empty full marker thereof |
| CN101154957B (en) * | 2006-09-30 | 2011-02-02 | 华为技术有限公司 | Turbo code interweaver and interweaved address transmission method |
| CN101281489B (en) * | 2007-04-03 | 2010-05-26 | 中兴通讯股份有限公司 | FIFO memory implementing method and apparatus |
| CN101552702B (en) * | 2008-12-31 | 2011-12-21 | 成都市华为赛门铁克科技有限公司 | Detection system and method for data processing system |
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| CN110082752A (en) * | 2019-04-23 | 2019-08-02 | 四川九洲空管科技有限责任公司 | A method of based on the processing of secondary radar inquisitor point mark data fault-tolerant |
| CN110082752B (en) * | 2019-04-23 | 2020-11-03 | 四川九洲空管科技有限责任公司 | Fault-tolerant processing method for trace point data based on secondary radar interrogator |
| WO2022083060A1 (en) * | 2020-10-21 | 2022-04-28 | 深圳市紫光同创电子有限公司 | Fifo memory and processing method for fifo memory |
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